1 // SPDX-License-Identifier: GPL-2.0+
4 * Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc
15 #include "mpc83xx_cpu.h"
18 * struct mpc83xx_cpu_priv - Private data for MPC83xx CPUs
19 * @e300_type: The e300 core type of the MPC83xx CPU
20 * @family: The MPC83xx family the CPU belongs to
21 * @type: The MPC83xx type of the CPU
22 * @is_e_processor: Flag indicating whether the CPU is a E processor or not
23 * @is_a_variant: Flag indicating whtther the CPU is a A variant or not
24 * @revid: The revision ID of the CPU
25 * @revid.major: The major part of the CPU's revision ID
26 * @revid.minor: The minor part of the CPU's revision ID
28 struct mpc83xx_cpu_priv {
29 enum e300_type e300_type;
30 enum mpc83xx_cpu_family family;
31 enum mpc83xx_cpu_type type;
42 /* Activate all CPUs from board_f.c */
43 return cpu_probe_all();
47 * get_spridr() - Read SPRIDR (System Part and Revision ID Register) of CPU
49 * Return: The SPRIDR value
51 static inline u32 get_spridr(void)
53 immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
55 return in_be32(&immr->sysconf.spridr);
59 * determine_type() - Determine CPU family of MPC83xx device
60 * @dev: CPU device from which to read CPU family from
62 static inline void determine_family(struct udevice *dev)
64 struct mpc83xx_cpu_priv *priv = dev_get_priv(dev);
65 /* Upper 12 bits of PARTID field (bits 0-23 in SPRIDR) */
66 const u32 PARTID_FAMILY_MASK = 0xFFF00000;
68 switch (bitfield_extract_by_mask(get_spridr(), PARTID_FAMILY_MASK)) {
71 priv->family = FAMILY_830X;
74 priv->family = FAMILY_831X;
77 priv->family = FAMILY_832X;
80 priv->family = FAMILY_834X;
83 priv->family = FAMILY_836X;
86 priv->family = FAMILY_837X;
89 priv->family = FAMILY_UNKNOWN;
94 * determine_type() - Determine CPU type of MPC83xx device
95 * @dev: CPU device from which to read CPU type from
97 static inline void determine_type(struct udevice *dev)
99 struct mpc83xx_cpu_priv *priv = dev_get_priv(dev);
100 /* Upper 16 bits of PVR (Processor Version Register) */
101 const u32 PCR_UPPER_MASK = 0xFFFF0000;
104 val = bitfield_extract_by_mask(get_spridr(), PCR_UPPER_MASK);
106 /* Mask out E-variant bit */
107 switch (val & 0xFFFE) {
109 priv->type = TYPE_8308;
112 priv->type = TYPE_8309;
115 priv->type = TYPE_8311;
118 priv->type = TYPE_8313;
121 priv->type = TYPE_8314;
124 priv->type = TYPE_8315;
127 priv->type = TYPE_8321;
130 priv->type = TYPE_8323;
133 priv->type = TYPE_8343;
136 priv->type = TYPE_8347_TBGA;
139 priv->type = TYPE_8347_PBGA;
142 priv->type = TYPE_8349;
145 priv->type = TYPE_8358_TBGA;
148 priv->type = TYPE_8358_PBGA;
151 priv->type = TYPE_8360;
154 priv->type = TYPE_8377;
157 priv->type = TYPE_8378;
160 priv->type = TYPE_8379;
163 priv->type = TYPE_UNKNOWN;
168 * determine_e300_type() - Determine e300 core type of MPC83xx device
169 * @dev: CPU device from which to read e300 core type from
171 static inline void determine_e300_type(struct udevice *dev)
173 struct mpc83xx_cpu_priv *priv = dev_get_priv(dev);
174 /* Upper 16 bits of PVR (Processor Version Register) */
175 const u32 PCR_UPPER_MASK = 0xFFFF0000;
178 switch ((pvr & PCR_UPPER_MASK) >> 16) {
180 priv->e300_type = E300C1;
183 priv->e300_type = E300C2;
186 priv->e300_type = E300C3;
189 priv->e300_type = E300C4;
192 priv->e300_type = E300_UNKNOWN;
197 * determine_revid() - Determine revision ID of CPU device
198 * @dev: CPU device from which to read revision ID
200 static inline void determine_revid(struct udevice *dev)
202 struct mpc83xx_cpu_priv *priv = dev_get_priv(dev);
203 u32 REVID_MAJOR_MASK;
204 u32 REVID_MINOR_MASK;
205 u32 spridr = get_spridr();
207 if (priv->family == FAMILY_834X) {
208 REVID_MAJOR_MASK = 0x0000FF00;
209 REVID_MINOR_MASK = 0x000000FF;
211 REVID_MAJOR_MASK = 0x000000F0;
212 REVID_MINOR_MASK = 0x0000000F;
215 priv->revid.major = bitfield_extract_by_mask(spridr, REVID_MAJOR_MASK);
216 priv->revid.minor = bitfield_extract_by_mask(spridr, REVID_MINOR_MASK);
220 * determine_cpu_data() - Determine CPU information from hardware
221 * @dev: CPU device from which to read information
223 static void determine_cpu_data(struct udevice *dev)
225 struct mpc83xx_cpu_priv *priv = dev_get_priv(dev);
226 const u32 E_FLAG_MASK = 0x00010000;
227 u32 spridr = get_spridr();
229 determine_family(dev);
231 determine_e300_type(dev);
232 determine_revid(dev);
234 if ((priv->family == FAMILY_834X ||
235 priv->family == FAMILY_836X) && priv->revid.major >= 2)
236 priv->is_a_variant = true;
238 priv->is_e_processor = !bitfield_extract_by_mask(spridr, E_FLAG_MASK);
241 static int mpc83xx_cpu_get_desc(struct udevice *dev, char *buf, int size)
243 struct mpc83xx_cpu_priv *priv = dev_get_priv(dev);
250 ret = clk_get_by_index(dev, 0, &core_clk);
252 debug("%s: Failed to get core clock (err = %d)\n",
257 ret = clk_get_by_index(dev, 1, &csb_clk);
259 debug("%s: Failed to get CSB clock (err = %d)\n",
264 determine_cpu_data(dev);
267 "%s, MPC%s%s%s, Rev: %d.%d at %s MHz, CSB: %s MHz",
268 e300_names[priv->e300_type],
269 cpu_type_names[priv->type],
270 priv->is_e_processor ? "E" : "",
271 priv->is_a_variant ? "A" : "",
274 strmhz(core_freq, clk_get_rate(&core_clk)),
275 strmhz(csb_freq, clk_get_rate(&csb_clk)));
280 static int mpc83xx_cpu_get_info(struct udevice *dev, struct cpu_info *info)
286 ret = clk_get_by_index(dev, 0, &clock);
288 debug("%s: Failed to get core clock (err = %d)\n",
293 freq = clk_get_rate(&clock);
295 debug("%s: Core clock speed is zero\n", dev->name);
299 info->cpu_freq = freq;
300 info->features = BIT(CPU_FEAT_L1_CACHE) | BIT(CPU_FEAT_MMU);
305 static int mpc83xx_cpu_get_count(struct udevice *dev)
307 /* We have one e300cX core */
311 static int mpc83xx_cpu_get_vendor(struct udevice *dev, char *buf, int size)
313 snprintf(buf, size, "NXP");
318 static const struct cpu_ops mpc83xx_cpu_ops = {
319 .get_desc = mpc83xx_cpu_get_desc,
320 .get_info = mpc83xx_cpu_get_info,
321 .get_count = mpc83xx_cpu_get_count,
322 .get_vendor = mpc83xx_cpu_get_vendor,
325 static int mpc83xx_cpu_probe(struct udevice *dev)
330 static const struct udevice_id mpc83xx_cpu_ids[] = {
331 { .compatible = "fsl,mpc83xx", },
332 { .compatible = "fsl,mpc8308", },
333 { .compatible = "fsl,mpc8309", },
334 { .compatible = "fsl,mpc8313", },
335 { .compatible = "fsl,mpc8315", },
336 { .compatible = "fsl,mpc832x", },
337 { .compatible = "fsl,mpc8349", },
338 { .compatible = "fsl,mpc8360", },
339 { .compatible = "fsl,mpc8379", },
343 U_BOOT_DRIVER(mpc83xx_cpu) = {
344 .name = "mpc83xx_cpu",
346 .of_match = mpc83xx_cpu_ids,
347 .probe = mpc83xx_cpu_probe,
348 .priv_auto_alloc_size = sizeof(struct mpc83xx_cpu_priv),
349 .ops = &mpc83xx_cpu_ops,
350 .flags = DM_FLAG_PRE_RELOC,