drivers/cpu/bmips_cpu.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
   4  *
   5  * Derived from linux/arch/mips/bcm63xx/cpu.c:
   6  *      Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
   7  *      Copyright (C) 2009 Florian Fainelli <florian@openwrt.org>
   8  */
   9
  10 #include <common.h>
  11 #include <cpu.h>
  12 #include <display_options.h>
  13 #include <dm.h>
  14 #include <errno.h>
  15 #include <init.h>
  16 #include <asm/io.h>
  17 #include <linux/bitops.h>
  18
  19 #define REV_CHIPID_SHIFT                16
  20 #define REV_CHIPID_MASK                 (0xffff << REV_CHIPID_SHIFT)
  21 #define REV_LONG_CHIPID_SHIFT           12
  22 #define REV_LONG_CHIPID_MASK            (0xfffff << REV_LONG_CHIPID_SHIFT)
  23 #define REV_REVID_SHIFT                 0
  24 #define REV_REVID_MASK                  (0xff << REV_REVID_SHIFT)
  25
  26 #define REG_BCM6328_OTP                 0x62c
  27 #define BCM6328_TP1_DISABLED            BIT(9)
  28
  29 #define REG_BCM6318_STRAP_OVRDBUS       0x900
  30 #define OVRDBUS_6318_FREQ_SHIFT         23
  31 #define OVRDBUS_6318_FREQ_MASK          (0x3 << OVRDBUS_6318_FREQ_SHIFT)
  32
  33 #define REG_BCM6328_MISC_STRAPBUS       0x1a40
  34 #define STRAPBUS_6328_FCVO_SHIFT        7
  35 #define STRAPBUS_6328_FCVO_MASK         (0x1f << STRAPBUS_6328_FCVO_SHIFT)
  36
  37 #define REG_BCM6348_PERF_MIPSPLLCFG     0x34
  38 #define MIPSPLLCFG_6348_M1CPU_SHIFT     6
  39 #define MIPSPLLCFG_6348_M1CPU_MASK      (0x7 << MIPSPLLCFG_6348_M1CPU_SHIFT)
  40 #define MIPSPLLCFG_6348_N2_SHIFT        15
  41 #define MIPSPLLCFG_6348_N2_MASK         (0x1F << MIPSPLLCFG_6348_N2_SHIFT)
  42 #define MIPSPLLCFG_6348_N1_SHIFT        20
  43 #define MIPSPLLCFG_6348_N1_MASK         (0x7 << MIPSPLLCFG_6348_N1_SHIFT)
  44
  45 #define REG_BCM6358_DDR_DMIPSPLLCFG     0x12b8
  46 #define DMIPSPLLCFG_6358_M1_SHIFT       0
  47 #define DMIPSPLLCFG_6358_M1_MASK        (0xff << DMIPSPLLCFG_6358_M1_SHIFT)
  48 #define DMIPSPLLCFG_6358_N1_SHIFT       23
  49 #define DMIPSPLLCFG_6358_N1_MASK        (0x3f << DMIPSPLLCFG_6358_N1_SHIFT)
  50 #define DMIPSPLLCFG_6358_N2_SHIFT       29
  51 #define DMIPSPLLCFG_6358_N2_MASK        (0x7 << DMIPSPLLCFG_6358_N2_SHIFT)
  52
  53 #define REG_BCM6362_MISC_STRAPBUS       0x1814
  54 #define STRAPBUS_6362_FCVO_SHIFT        1
  55 #define STRAPBUS_6362_FCVO_MASK         (0x1f << STRAPBUS_6362_FCVO_SHIFT)
  56
  57 #define REG_BCM6368_DDR_DMIPSPLLCFG     0x12a0
  58 #define DMIPSPLLCFG_6368_P1_SHIFT       0
  59 #define DMIPSPLLCFG_6368_P1_MASK        (0xf << DMIPSPLLCFG_6368_P1_SHIFT)
  60 #define DMIPSPLLCFG_6368_P2_SHIFT       4
  61 #define DMIPSPLLCFG_6368_P2_MASK        (0xf << DMIPSPLLCFG_6368_P2_SHIFT)
  62 #define DMIPSPLLCFG_6368_NDIV_SHIFT     16
  63 #define DMIPSPLLCFG_6368_NDIV_MASK      (0x1ff << DMIPSPLLCFG_6368_NDIV_SHIFT)
  64 #define REG_BCM6368_DDR_DMIPSPLLDIV     0x12a4
  65 #define DMIPSPLLDIV_6368_MDIV_SHIFT     0
  66 #define DMIPSPLLDIV_6368_MDIV_MASK      (0xff << DMIPSPLLDIV_6368_MDIV_SHIFT)
  67
  68 #define REG_BCM63268_MISC_STRAPBUS      0x1814
  69 #define STRAPBUS_63268_FCVO_SHIFT       21
  70 #define STRAPBUS_63268_FCVO_MASK        (0xf << STRAPBUS_63268_FCVO_SHIFT)
  71
  72 #define REG_BCM6838_OTP_BRCMBITS0       0x440
  73 #define VIPER_6838_FREQ_SHIFT           18
  74 #define VIPER_6838_FREQ_MASK            (0x7 << VIPER_6838_FREQ_SHIFT)
  75
  76 struct bmips_cpu_priv;
  77
  78 struct bmips_cpu_hw {
  79         int (*get_cpu_desc)(struct bmips_cpu_priv *priv, char *buf, int size);
  80         ulong (*get_cpu_freq)(struct bmips_cpu_priv *);
  81         int (*get_cpu_count)(struct bmips_cpu_priv *);
  82 };
  83
  84 struct bmips_cpu_priv {
  85         void __iomem *regs;
  86         const struct bmips_cpu_hw *hw;
  87 };
  88
  89 /* Specific CPU Ops */
  90 static int bmips_short_cpu_desc(struct bmips_cpu_priv *priv, char *buf,
  91                                 int size)
  92 {
  93         unsigned short cpu_id;
  94         unsigned char cpu_rev;
  95         u32 val;
  96
  97         val = readl_be(priv->regs);
  98         cpu_id = (val & REV_CHIPID_MASK) >> REV_CHIPID_SHIFT;
  99         cpu_rev = (val & REV_REVID_MASK) >> REV_REVID_SHIFT;
 100
 101         snprintf(buf, size, "BCM%04X%02X", cpu_id, cpu_rev);
 102
 103         return 0;
 104 }
 105
 106 static int bmips_long_cpu_desc(struct bmips_cpu_priv *priv, char *buf,
 107                                 int size)
 108 {
 109         unsigned int cpu_id;
 110         unsigned char cpu_rev;
 111         u32 val;
 112
 113         val = readl_be(priv->regs);
 114         cpu_id = (val & REV_LONG_CHIPID_MASK) >> REV_LONG_CHIPID_SHIFT;
 115         cpu_rev = (val & REV_REVID_MASK) >> REV_REVID_SHIFT;
 116
 117         snprintf(buf, size, "BCM%05X%02X", cpu_id, cpu_rev);
 118
 119         return 0;
 120 }
 121
 122 static ulong bcm3380_get_cpu_freq(struct bmips_cpu_priv *priv)
 123 {
 124         return 333000000;
 125 }
 126
 127 static ulong bcm6318_get_cpu_freq(struct bmips_cpu_priv *priv)
 128 {
 129         unsigned int mips_pll_fcvo;
 130
 131         mips_pll_fcvo = readl_be(priv->regs + REG_BCM6318_STRAP_OVRDBUS);
 132         mips_pll_fcvo = (mips_pll_fcvo & OVRDBUS_6318_FREQ_MASK)
 133                         >> OVRDBUS_6318_FREQ_SHIFT;
 134
 135         switch (mips_pll_fcvo) {
 136         case 0:
 137                 return 166000000;
 138         case 1:
 139                 return 400000000;
 140         case 2:
 141                 return 250000000;
 142         case 3:
 143                 return 333000000;
 144         default:
 145                 return 0;
 146         }
 147 }
 148
 149 static ulong bcm6328_get_cpu_freq(struct bmips_cpu_priv *priv)
 150 {
 151         unsigned int mips_pll_fcvo;
 152
 153         mips_pll_fcvo = readl_be(priv->regs + REG_BCM6328_MISC_STRAPBUS);
 154         mips_pll_fcvo = (mips_pll_fcvo & STRAPBUS_6328_FCVO_MASK)
 155                         >> STRAPBUS_6328_FCVO_SHIFT;
 156
 157         switch (mips_pll_fcvo) {
 158         case 0x12:
 159         case 0x14:
 160         case 0x19:
 161                 return 160000000;
 162         case 0x1c:
 163                 return 192000000;
 164         case 0x13:
 165         case 0x15:
 166                 return 200000000;
 167         case 0x1a:
 168                 return 384000000;
 169         case 0x16:
 170                 return 400000000;
 171         default:
 172                 return 320000000;
 173         }
 174 }
 175
 176 static ulong bcm6338_get_cpu_freq(struct bmips_cpu_priv *priv)
 177 {
 178         return 240000000;
 179 }
 180
 181 static ulong bcm6348_get_cpu_freq(struct bmips_cpu_priv *priv)
 182 {
 183         unsigned int tmp, n1, n2, m1;
 184
 185         tmp = readl_be(priv->regs + REG_BCM6348_PERF_MIPSPLLCFG);
 186         n1 = (tmp & MIPSPLLCFG_6348_N1_MASK) >> MIPSPLLCFG_6348_N1_SHIFT;
 187         n2 = (tmp & MIPSPLLCFG_6348_N2_MASK) >> MIPSPLLCFG_6348_N2_SHIFT;
 188         m1 = (tmp & MIPSPLLCFG_6348_M1CPU_MASK) >> MIPSPLLCFG_6348_M1CPU_SHIFT;
 189
 190         return (16 * 1000000 * (n1 + 1) * (n2 + 2)) / (m1 + 1);
 191 }
 192
 193 static ulong bcm6358_get_cpu_freq(struct bmips_cpu_priv *priv)
 194 {
 195         unsigned int tmp, n1, n2, m1;
 196
 197         tmp = readl_be(priv->regs + REG_BCM6358_DDR_DMIPSPLLCFG);
 198         n1 = (tmp & DMIPSPLLCFG_6358_N1_MASK) >> DMIPSPLLCFG_6358_N1_SHIFT;
 199         n2 = (tmp & DMIPSPLLCFG_6358_N2_MASK) >> DMIPSPLLCFG_6358_N2_SHIFT;
 200         m1 = (tmp & DMIPSPLLCFG_6358_M1_MASK) >> DMIPSPLLCFG_6358_M1_SHIFT;
 201
 202         return (16 * 1000000 * n1 * n2) / m1;
 203 }
 204
 205 static ulong bcm6362_get_cpu_freq(struct bmips_cpu_priv *priv)
 206 {
 207         unsigned int mips_pll_fcvo;
 208
 209         mips_pll_fcvo = readl_be(priv->regs + REG_BCM6362_MISC_STRAPBUS);
 210         mips_pll_fcvo = (mips_pll_fcvo & STRAPBUS_6362_FCVO_MASK)
 211                         >> STRAPBUS_6362_FCVO_SHIFT;
 212
 213         switch (mips_pll_fcvo) {
 214         case 0x03:
 215         case 0x0b:
 216         case 0x13:
 217         case 0x1b:
 218                 return 240000000;
 219         case 0x04:
 220         case 0x0c:
 221         case 0x14:
 222         case 0x1c:
 223                 return 160000000;
 224         case 0x05:
 225         case 0x0e:
 226         case 0x16:
 227         case 0x1e:
 228         case 0x1f:
 229                 return 400000000;
 230         case 0x06:
 231                 return 440000000;
 232         case 0x07:
 233         case 0x17:
 234                 return 384000000;
 235         case 0x15:
 236         case 0x1d:
 237                 return 200000000;
 238         default:
 239                 return 320000000;
 240         }
 241 }
 242
 243 static ulong bcm6368_get_cpu_freq(struct bmips_cpu_priv *priv)
 244 {
 245         unsigned int tmp, p1, p2, ndiv, m1;
 246
 247         tmp = readl_be(priv->regs + REG_BCM6368_DDR_DMIPSPLLCFG);
 248         p1 = (tmp & DMIPSPLLCFG_6368_P1_MASK) >> DMIPSPLLCFG_6368_P1_SHIFT;
 249         p2 = (tmp & DMIPSPLLCFG_6368_P2_MASK) >> DMIPSPLLCFG_6368_P2_SHIFT;
 250         ndiv = (tmp & DMIPSPLLCFG_6368_NDIV_MASK) >>
 251                DMIPSPLLCFG_6368_NDIV_SHIFT;
 252
 253         tmp = readl_be(priv->regs + REG_BCM6368_DDR_DMIPSPLLDIV);
 254         m1 = (tmp & DMIPSPLLDIV_6368_MDIV_MASK) >> DMIPSPLLDIV_6368_MDIV_SHIFT;
 255
 256         return (((64 * 1000000) / p1) * p2 * ndiv) / m1;
 257 }
 258
 259 static ulong bcm63268_get_cpu_freq(struct bmips_cpu_priv *priv)
 260 {
 261         unsigned int mips_pll_fcvo;
 262
 263         mips_pll_fcvo = readl_be(priv->regs + REG_BCM63268_MISC_STRAPBUS);
 264         mips_pll_fcvo = (mips_pll_fcvo & STRAPBUS_63268_FCVO_MASK)
 265                         >> STRAPBUS_63268_FCVO_SHIFT;
 266
 267         switch (mips_pll_fcvo) {
 268         case 0x3:
 269         case 0xe:
 270                 return 320000000;
 271         case 0xa:
 272                 return 333000000;
 273         case 0x2:
 274         case 0xb:
 275         case 0xf:
 276                 return 400000000;
 277         default:
 278                 return 0;
 279         }
 280 }
 281
 282 static ulong bcm6838_get_cpu_freq(struct bmips_cpu_priv *priv)
 283 {
 284         unsigned int mips_viper_freq;
 285
 286         mips_viper_freq = readl_be(priv->regs + REG_BCM6838_OTP_BRCMBITS0);
 287         mips_viper_freq = (mips_viper_freq & VIPER_6838_FREQ_MASK)
 288                 >> VIPER_6838_FREQ_SHIFT;
 289
 290         switch (mips_viper_freq) {
 291         case 0x0:
 292                 return 600000000;
 293         case 0x1:
 294                 return 400000000;
 295         case 0x2:
 296                 return 240000000;
 297         default:
 298                 return 0;
 299         }
 300 }
 301
 302 static int bcm6328_get_cpu_count(struct bmips_cpu_priv *priv)
 303 {
 304         u32 val = readl_be(priv->regs + REG_BCM6328_OTP);
 305
 306         if (val & BCM6328_TP1_DISABLED)
 307                 return 1;
 308         else
 309                 return 2;
 310 }
 311
 312 static int bcm6345_get_cpu_count(struct bmips_cpu_priv *priv)
 313 {
 314         return 1;
 315 }
 316
 317 static int bcm6358_get_cpu_count(struct bmips_cpu_priv *priv)
 318 {
 319         return 2;
 320 }
 321
 322 static const struct bmips_cpu_hw bmips_cpu_bcm3380 = {
 323         .get_cpu_desc = bmips_short_cpu_desc,
 324         .get_cpu_freq = bcm3380_get_cpu_freq,
 325         .get_cpu_count = bcm6358_get_cpu_count,
 326 };
 327
 328 static const struct bmips_cpu_hw bmips_cpu_bcm6318 = {
 329         .get_cpu_desc = bmips_short_cpu_desc,
 330         .get_cpu_freq = bcm6318_get_cpu_freq,
 331         .get_cpu_count = bcm6345_get_cpu_count,
 332 };
 333
 334 static const struct bmips_cpu_hw bmips_cpu_bcm6328 = {
 335         .get_cpu_desc = bmips_long_cpu_desc,
 336         .get_cpu_freq = bcm6328_get_cpu_freq,
 337         .get_cpu_count = bcm6328_get_cpu_count,
 338 };
 339
 340 static const struct bmips_cpu_hw bmips_cpu_bcm6338 = {
 341         .get_cpu_desc = bmips_short_cpu_desc,
 342         .get_cpu_freq = bcm6338_get_cpu_freq,
 343         .get_cpu_count = bcm6345_get_cpu_count,
 344 };
 345
 346 static const struct bmips_cpu_hw bmips_cpu_bcm6348 = {
 347         .get_cpu_desc = bmips_short_cpu_desc,
 348         .get_cpu_freq = bcm6348_get_cpu_freq,
 349         .get_cpu_count = bcm6345_get_cpu_count,
 350 };
 351
 352 static const struct bmips_cpu_hw bmips_cpu_bcm6358 = {
 353         .get_cpu_desc = bmips_short_cpu_desc,
 354         .get_cpu_freq = bcm6358_get_cpu_freq,
 355         .get_cpu_count = bcm6358_get_cpu_count,
 356 };
 357
 358 static const struct bmips_cpu_hw bmips_cpu_bcm6362 = {
 359         .get_cpu_desc = bmips_short_cpu_desc,
 360         .get_cpu_freq = bcm6362_get_cpu_freq,
 361         .get_cpu_count = bcm6358_get_cpu_count,
 362 };
 363
 364 static const struct bmips_cpu_hw bmips_cpu_bcm6368 = {
 365         .get_cpu_desc = bmips_short_cpu_desc,
 366         .get_cpu_freq = bcm6368_get_cpu_freq,
 367         .get_cpu_count = bcm6358_get_cpu_count,
 368 };
 369
 370 static const struct bmips_cpu_hw bmips_cpu_bcm63268 = {
 371         .get_cpu_desc = bmips_long_cpu_desc,
 372         .get_cpu_freq = bcm63268_get_cpu_freq,
 373         .get_cpu_count = bcm6358_get_cpu_count,
 374 };
 375
 376 static const struct bmips_cpu_hw bmips_cpu_bcm6838 = {
 377         .get_cpu_desc = bmips_short_cpu_desc,
 378         .get_cpu_freq = bcm6838_get_cpu_freq,
 379         .get_cpu_count = bcm6358_get_cpu_count,
 380 };
 381
 382 /* Generic CPU Ops */
 383 static int bmips_cpu_get_desc(const struct udevice *dev, char *buf, int size)
 384 {
 385         struct bmips_cpu_priv *priv = dev_get_priv(dev);
 386         const struct bmips_cpu_hw *hw = priv->hw;
 387
 388         return hw->get_cpu_desc(priv, buf, size);
 389 }
 390
 391 static int bmips_cpu_get_info(const struct udevice *dev, struct cpu_info *info)
 392 {
 393         struct bmips_cpu_priv *priv = dev_get_priv(dev);
 394         const struct bmips_cpu_hw *hw = priv->hw;
 395
 396         info->cpu_freq = hw->get_cpu_freq(priv);
 397         info->features = BIT(CPU_FEAT_L1_CACHE);
 398         info->features |= BIT(CPU_FEAT_MMU);
 399         info->features |= BIT(CPU_FEAT_DEVICE_ID);
 400
 401         return 0;
 402 }
 403
 404 static int bmips_cpu_get_count(const struct udevice *dev)
 405 {
 406         struct bmips_cpu_priv *priv = dev_get_priv(dev);
 407         const struct bmips_cpu_hw *hw = priv->hw;
 408
 409         return hw->get_cpu_count(priv);
 410 }
 411
 412 static int bmips_cpu_get_vendor(const struct udevice *dev, char *buf, int size)
 413 {
 414         snprintf(buf, size, "Broadcom");
 415
 416         return 0;
 417 }
 418
 419 static const struct cpu_ops bmips_cpu_ops = {
 420         .get_desc = bmips_cpu_get_desc,
 421         .get_info = bmips_cpu_get_info,
 422         .get_count = bmips_cpu_get_count,
 423         .get_vendor = bmips_cpu_get_vendor,
 424 };
 425
 426 /* BMIPS CPU driver */
 427 int bmips_cpu_bind(struct udevice *dev)
 428 {
 429         struct cpu_plat *plat = dev_get_parent_plat(dev);
 430
 431         plat->cpu_id = dev_read_u32_default(dev, "reg", -1);
 432         plat->device_id = read_c0_prid();
 433
 434         return 0;
 435 }
 436
 437 int bmips_cpu_probe(struct udevice *dev)
 438 {
 439         struct bmips_cpu_priv *priv = dev_get_priv(dev);
 440         const struct bmips_cpu_hw *hw =
 441                 (const struct bmips_cpu_hw *)dev_get_driver_data(dev);
 442
 443         priv->regs = dev_remap_addr(dev_get_parent(dev));
 444         if (!priv->regs)
 445                 return -EINVAL;
 446
 447         priv->hw = hw;
 448
 449         return 0;
 450 }
 451
 452 static const struct udevice_id bmips_cpu_ids[] = {
 453         {
 454                 .compatible = "brcm,bcm3380-cpu",
 455                 .data = (ulong)&bmips_cpu_bcm3380,
 456         }, {
 457                 .compatible = "brcm,bcm6318-cpu",
 458                 .data = (ulong)&bmips_cpu_bcm6318,
 459         }, {
 460                 .compatible = "brcm,bcm6328-cpu",
 461                 .data = (ulong)&bmips_cpu_bcm6328,
 462         }, {
 463                 .compatible = "brcm,bcm6338-cpu",
 464                 .data = (ulong)&bmips_cpu_bcm6338,
 465         }, {
 466                 .compatible = "brcm,bcm6348-cpu",
 467                 .data = (ulong)&bmips_cpu_bcm6348,
 468         }, {
 469                 .compatible = "brcm,bcm6358-cpu",
 470                 .data = (ulong)&bmips_cpu_bcm6358,
 471         }, {
 472                 .compatible = "brcm,bcm6362-cpu",
 473                 .data = (ulong)&bmips_cpu_bcm6362,
 474         }, {
 475                 .compatible = "brcm,bcm6368-cpu",
 476                 .data = (ulong)&bmips_cpu_bcm6368,
 477         }, {
 478                 .compatible = "brcm,bcm63268-cpu",
 479                 .data = (ulong)&bmips_cpu_bcm63268,
 480         }, {
 481                 .compatible = "brcm,bcm6838-cpu",
 482                 .data = (ulong)&bmips_cpu_bcm6838,
 483         },
 484         { /* sentinel */ }
 485 };
 486
 487 U_BOOT_DRIVER(bmips_cpu_drv) = {
 488         .name = "bmips_cpu",
 489         .id = UCLASS_CPU,
 490         .of_match = bmips_cpu_ids,
 491         .bind = bmips_cpu_bind,
 492         .probe = bmips_cpu_probe,
 493         .priv_auto      = sizeof(struct bmips_cpu_priv),
 494         .ops = &bmips_cpu_ops,
 495         .flags = DM_FLAG_PRE_RELOC,
 496 };
 497
 498 #ifdef CONFIG_DISPLAY_CPUINFO
 499 int print_cpuinfo(void)
 500 {
 501         struct cpu_info cpu;
 502         struct udevice *dev;
 503         int err;
 504         char desc[100];
 505
 506         err = uclass_get_device(UCLASS_CPU, 0, &dev);
 507         if (err)
 508                 return 0;
 509
 510         err = cpu_get_info(dev, &cpu);
 511         if (err)
 512                 return 0;
 513
 514         err = cpu_get_desc(dev, desc, sizeof(desc));
 515         if (err)
 516                 return 0;
 517
 518         printf("Chip ID: %s, MIPS: ", desc);
 519         print_freq(cpu.cpu_freq, "\n");
 520
 521         return 0;
 522 }
 523 #endif