1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2020 Microchip
5 * Author: Kamel Bouhara <kamel.bouhara@bootlin.com>
8 #include <linux/counter.h>
9 #include <linux/mfd/syscon.h>
10 #include <linux/module.h>
11 #include <linux/mutex.h>
13 #include <linux/of_device.h>
14 #include <linux/platform_device.h>
15 #include <linux/regmap.h>
16 #include <soc/at91/atmel_tcb.h>
18 #define ATMEL_TC_CMR_MASK (ATMEL_TC_LDRA_RISING | ATMEL_TC_LDRB_FALLING | \
19 ATMEL_TC_ETRGEDG_RISING | ATMEL_TC_LDBDIS | \
22 #define ATMEL_TC_QDEN BIT(8)
23 #define ATMEL_TC_POSEN BIT(9)
26 const struct atmel_tcb_config *tc_cfg;
27 struct counter_device counter;
28 struct regmap *regmap;
34 enum mchp_tc_count_function {
35 MCHP_TC_FUNCTION_INCREASE,
36 MCHP_TC_FUNCTION_QUADRATURE,
39 static const enum counter_function mchp_tc_count_functions[] = {
40 [MCHP_TC_FUNCTION_INCREASE] = COUNTER_FUNCTION_INCREASE,
41 [MCHP_TC_FUNCTION_QUADRATURE] = COUNTER_FUNCTION_QUADRATURE_X4,
44 enum mchp_tc_synapse_action {
45 MCHP_TC_SYNAPSE_ACTION_NONE = 0,
46 MCHP_TC_SYNAPSE_ACTION_RISING_EDGE,
47 MCHP_TC_SYNAPSE_ACTION_FALLING_EDGE,
48 MCHP_TC_SYNAPSE_ACTION_BOTH_EDGE
51 static const enum counter_synapse_action mchp_tc_synapse_actions[] = {
52 [MCHP_TC_SYNAPSE_ACTION_NONE] = COUNTER_SYNAPSE_ACTION_NONE,
53 [MCHP_TC_SYNAPSE_ACTION_RISING_EDGE] = COUNTER_SYNAPSE_ACTION_RISING_EDGE,
54 [MCHP_TC_SYNAPSE_ACTION_FALLING_EDGE] = COUNTER_SYNAPSE_ACTION_FALLING_EDGE,
55 [MCHP_TC_SYNAPSE_ACTION_BOTH_EDGE] = COUNTER_SYNAPSE_ACTION_BOTH_EDGES,
58 static struct counter_signal mchp_tc_count_signals[] = {
69 static struct counter_synapse mchp_tc_count_synapses[] = {
71 .actions_list = mchp_tc_synapse_actions,
72 .num_actions = ARRAY_SIZE(mchp_tc_synapse_actions),
73 .signal = &mchp_tc_count_signals[0]
76 .actions_list = mchp_tc_synapse_actions,
77 .num_actions = ARRAY_SIZE(mchp_tc_synapse_actions),
78 .signal = &mchp_tc_count_signals[1]
82 static int mchp_tc_count_function_get(struct counter_device *counter,
83 struct counter_count *count,
86 struct mchp_tc_data *const priv = counter->priv;
89 *function = MCHP_TC_FUNCTION_QUADRATURE;
91 *function = MCHP_TC_FUNCTION_INCREASE;
96 static int mchp_tc_count_function_set(struct counter_device *counter,
97 struct counter_count *count,
100 struct mchp_tc_data *const priv = counter->priv;
103 regmap_read(priv->regmap, ATMEL_TC_BMR, &bmr);
104 regmap_read(priv->regmap, ATMEL_TC_REG(priv->channel[0], CMR), &cmr);
106 /* Set capture mode */
107 cmr &= ~ATMEL_TC_WAVE;
110 case MCHP_TC_FUNCTION_INCREASE:
112 /* Set highest rate based on whether soc has gclk or not */
113 bmr &= ~(ATMEL_TC_QDEN | ATMEL_TC_POSEN);
114 if (priv->tc_cfg->has_gclk)
115 cmr |= ATMEL_TC_TIMER_CLOCK2;
117 cmr |= ATMEL_TC_TIMER_CLOCK1;
118 /* Setup the period capture mode */
119 cmr |= ATMEL_TC_CMR_MASK;
120 cmr &= ~(ATMEL_TC_ABETRG | ATMEL_TC_XC0);
122 case MCHP_TC_FUNCTION_QUADRATURE:
123 if (!priv->tc_cfg->has_qdec)
125 /* In QDEC mode settings both channels 0 and 1 are required */
126 if (priv->num_channels < 2 || priv->channel[0] != 0 ||
127 priv->channel[1] != 1) {
128 pr_err("Invalid channels number or id for quadrature mode\n");
132 bmr |= ATMEL_TC_QDEN | ATMEL_TC_POSEN;
133 cmr |= ATMEL_TC_ETRGEDG_RISING | ATMEL_TC_ABETRG | ATMEL_TC_XC0;
136 /* should never reach this path */
140 regmap_write(priv->regmap, ATMEL_TC_BMR, bmr);
141 regmap_write(priv->regmap, ATMEL_TC_REG(priv->channel[0], CMR), cmr);
143 /* Enable clock and trigger counter */
144 regmap_write(priv->regmap, ATMEL_TC_REG(priv->channel[0], CCR),
145 ATMEL_TC_CLKEN | ATMEL_TC_SWTRG);
147 if (priv->qdec_mode) {
148 regmap_write(priv->regmap,
149 ATMEL_TC_REG(priv->channel[1], CMR), cmr);
150 regmap_write(priv->regmap,
151 ATMEL_TC_REG(priv->channel[1], CCR),
152 ATMEL_TC_CLKEN | ATMEL_TC_SWTRG);
158 static int mchp_tc_count_signal_read(struct counter_device *counter,
159 struct counter_signal *signal,
160 enum counter_signal_level *lvl)
162 struct mchp_tc_data *const priv = counter->priv;
166 regmap_read(priv->regmap, ATMEL_TC_REG(priv->channel[0], SR), &sr);
169 sigstatus = (sr & ATMEL_TC_MTIOB);
171 sigstatus = (sr & ATMEL_TC_MTIOA);
173 *lvl = sigstatus ? COUNTER_SIGNAL_LEVEL_HIGH : COUNTER_SIGNAL_LEVEL_LOW;
178 static int mchp_tc_count_action_get(struct counter_device *counter,
179 struct counter_count *count,
180 struct counter_synapse *synapse,
183 struct mchp_tc_data *const priv = counter->priv;
186 if (priv->qdec_mode) {
187 *action = COUNTER_SYNAPSE_ACTION_BOTH_EDGES;
191 /* Only TIOA signal is evaluated in non-QDEC mode */
192 if (synapse->signal->id != 0) {
193 *action = COUNTER_SYNAPSE_ACTION_NONE;
197 regmap_read(priv->regmap, ATMEL_TC_REG(priv->channel[0], CMR), &cmr);
199 switch (cmr & ATMEL_TC_ETRGEDG) {
201 *action = MCHP_TC_SYNAPSE_ACTION_NONE;
203 case ATMEL_TC_ETRGEDG_RISING:
204 *action = MCHP_TC_SYNAPSE_ACTION_RISING_EDGE;
206 case ATMEL_TC_ETRGEDG_FALLING:
207 *action = MCHP_TC_SYNAPSE_ACTION_FALLING_EDGE;
209 case ATMEL_TC_ETRGEDG_BOTH:
210 *action = MCHP_TC_SYNAPSE_ACTION_BOTH_EDGE;
217 static int mchp_tc_count_action_set(struct counter_device *counter,
218 struct counter_count *count,
219 struct counter_synapse *synapse,
222 struct mchp_tc_data *const priv = counter->priv;
223 u32 edge = ATMEL_TC_ETRGEDG_NONE;
225 /* QDEC mode is rising edge only; only TIOA handled in non-QDEC mode */
226 if (priv->qdec_mode || synapse->signal->id != 0)
230 case MCHP_TC_SYNAPSE_ACTION_NONE:
231 edge = ATMEL_TC_ETRGEDG_NONE;
233 case MCHP_TC_SYNAPSE_ACTION_RISING_EDGE:
234 edge = ATMEL_TC_ETRGEDG_RISING;
236 case MCHP_TC_SYNAPSE_ACTION_FALLING_EDGE:
237 edge = ATMEL_TC_ETRGEDG_FALLING;
239 case MCHP_TC_SYNAPSE_ACTION_BOTH_EDGE:
240 edge = ATMEL_TC_ETRGEDG_BOTH;
243 /* should never reach this path */
247 return regmap_write_bits(priv->regmap,
248 ATMEL_TC_REG(priv->channel[0], CMR),
249 ATMEL_TC_ETRGEDG, edge);
252 static int mchp_tc_count_read(struct counter_device *counter,
253 struct counter_count *count,
256 struct mchp_tc_data *const priv = counter->priv;
259 regmap_read(priv->regmap, ATMEL_TC_REG(priv->channel[0], CV), &cnt);
265 static struct counter_count mchp_tc_counts[] = {
268 .name = "Timer Counter",
269 .functions_list = mchp_tc_count_functions,
270 .num_functions = ARRAY_SIZE(mchp_tc_count_functions),
271 .synapses = mchp_tc_count_synapses,
272 .num_synapses = ARRAY_SIZE(mchp_tc_count_synapses),
276 static const struct counter_ops mchp_tc_ops = {
277 .signal_read = mchp_tc_count_signal_read,
278 .count_read = mchp_tc_count_read,
279 .function_get = mchp_tc_count_function_get,
280 .function_set = mchp_tc_count_function_set,
281 .action_get = mchp_tc_count_action_get,
282 .action_set = mchp_tc_count_action_set
285 static const struct atmel_tcb_config tcb_rm9200_config = {
289 static const struct atmel_tcb_config tcb_sam9x5_config = {
293 static const struct atmel_tcb_config tcb_sama5d2_config = {
299 static const struct atmel_tcb_config tcb_sama5d3_config = {
304 static const struct of_device_id atmel_tc_of_match[] = {
305 { .compatible = "atmel,at91rm9200-tcb", .data = &tcb_rm9200_config, },
306 { .compatible = "atmel,at91sam9x5-tcb", .data = &tcb_sam9x5_config, },
307 { .compatible = "atmel,sama5d2-tcb", .data = &tcb_sama5d2_config, },
308 { .compatible = "atmel,sama5d3-tcb", .data = &tcb_sama5d3_config, },
312 static void mchp_tc_clk_remove(void *ptr)
314 clk_disable_unprepare((struct clk *)ptr);
317 static int mchp_tc_probe(struct platform_device *pdev)
319 struct device_node *np = pdev->dev.of_node;
320 const struct atmel_tcb_config *tcb_config;
321 const struct of_device_id *match;
322 struct mchp_tc_data *priv;
324 struct regmap *regmap;
329 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
333 platform_set_drvdata(pdev, priv);
335 match = of_match_node(atmel_tc_of_match, np->parent);
336 tcb_config = match->data;
338 dev_err(&pdev->dev, "No matching parent node found\n");
342 regmap = syscon_node_to_regmap(np->parent);
344 return PTR_ERR(regmap);
346 /* max. channels number is 2 when in QDEC mode */
347 priv->num_channels = of_property_count_u32_elems(np, "reg");
348 if (priv->num_channels < 0) {
349 dev_err(&pdev->dev, "Invalid or missing channel\n");
353 /* Register channels and initialize clocks */
354 for (i = 0; i < priv->num_channels; i++) {
355 ret = of_property_read_u32_index(np, "reg", i, &channel);
356 if (ret < 0 || channel > 2)
359 priv->channel[i] = channel;
361 snprintf(clk_name, sizeof(clk_name), "t%d_clk", channel);
363 clk[i] = of_clk_get_by_name(np->parent, clk_name);
364 if (IS_ERR(clk[i])) {
365 /* Fallback to t0_clk */
366 clk[i] = of_clk_get_by_name(np->parent, "t0_clk");
368 return PTR_ERR(clk[i]);
371 ret = clk_prepare_enable(clk[i]);
375 ret = devm_add_action_or_reset(&pdev->dev,
382 "Initialized capture mode on channel %d\n",
386 priv->tc_cfg = tcb_config;
387 priv->regmap = regmap;
388 priv->counter.name = dev_name(&pdev->dev);
389 priv->counter.parent = &pdev->dev;
390 priv->counter.ops = &mchp_tc_ops;
391 priv->counter.num_counts = ARRAY_SIZE(mchp_tc_counts);
392 priv->counter.counts = mchp_tc_counts;
393 priv->counter.num_signals = ARRAY_SIZE(mchp_tc_count_signals);
394 priv->counter.signals = mchp_tc_count_signals;
395 priv->counter.priv = priv;
397 return devm_counter_register(&pdev->dev, &priv->counter);
400 static const struct of_device_id mchp_tc_dt_ids[] = {
401 { .compatible = "microchip,tcb-capture", },
404 MODULE_DEVICE_TABLE(of, mchp_tc_dt_ids);
406 static struct platform_driver mchp_tc_driver = {
407 .probe = mchp_tc_probe,
409 .name = "microchip-tcb-capture",
410 .of_match_table = mchp_tc_dt_ids,
413 module_platform_driver(mchp_tc_driver);
415 MODULE_AUTHOR("Kamel Bouhara <kamel.bouhara@bootlin.com>");
416 MODULE_DESCRIPTION("Microchip TCB Capture driver");
417 MODULE_LICENSE("GPL v2");