drivers/counter/microchip-tcb-capture.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /**
   3  * Copyright (C) 2020 Microchip
   4  *
   5  * Author: Kamel Bouhara <kamel.bouhara@bootlin.com>
   6  */
   7 #include <linux/clk.h>
   8 #include <linux/counter.h>
   9 #include <linux/mfd/syscon.h>
  10 #include <linux/module.h>
  11 #include <linux/mutex.h>
  12 #include <linux/of.h>
  13 #include <linux/of_device.h>
  14 #include <linux/platform_device.h>
  15 #include <linux/regmap.h>
  16 #include <soc/at91/atmel_tcb.h>
  17
  18 #define ATMEL_TC_CMR_MASK       (ATMEL_TC_LDRA_RISING | ATMEL_TC_LDRB_FALLING | \
  19                                  ATMEL_TC_ETRGEDG_RISING | ATMEL_TC_LDBDIS | \
  20                                  ATMEL_TC_LDBSTOP)
  21
  22 #define ATMEL_TC_QDEN                   BIT(8)
  23 #define ATMEL_TC_POSEN                  BIT(9)
  24
  25 struct mchp_tc_data {
  26         const struct atmel_tcb_config *tc_cfg;
  27         struct counter_device counter;
  28         struct regmap *regmap;
  29         int qdec_mode;
  30         int num_channels;
  31         int channel[2];
  32 };
  33
  34 enum mchp_tc_count_function {
  35         MCHP_TC_FUNCTION_INCREASE,
  36         MCHP_TC_FUNCTION_QUADRATURE,
  37 };
  38
  39 static const enum counter_function mchp_tc_count_functions[] = {
  40         [MCHP_TC_FUNCTION_INCREASE] = COUNTER_FUNCTION_INCREASE,
  41         [MCHP_TC_FUNCTION_QUADRATURE] = COUNTER_FUNCTION_QUADRATURE_X4,
  42 };
  43
  44 enum mchp_tc_synapse_action {
  45         MCHP_TC_SYNAPSE_ACTION_NONE = 0,
  46         MCHP_TC_SYNAPSE_ACTION_RISING_EDGE,
  47         MCHP_TC_SYNAPSE_ACTION_FALLING_EDGE,
  48         MCHP_TC_SYNAPSE_ACTION_BOTH_EDGE
  49 };
  50
  51 static const enum counter_synapse_action mchp_tc_synapse_actions[] = {
  52         [MCHP_TC_SYNAPSE_ACTION_NONE] = COUNTER_SYNAPSE_ACTION_NONE,
  53         [MCHP_TC_SYNAPSE_ACTION_RISING_EDGE] = COUNTER_SYNAPSE_ACTION_RISING_EDGE,
  54         [MCHP_TC_SYNAPSE_ACTION_FALLING_EDGE] = COUNTER_SYNAPSE_ACTION_FALLING_EDGE,
  55         [MCHP_TC_SYNAPSE_ACTION_BOTH_EDGE] = COUNTER_SYNAPSE_ACTION_BOTH_EDGES,
  56 };
  57
  58 static struct counter_signal mchp_tc_count_signals[] = {
  59         {
  60                 .id = 0,
  61                 .name = "Channel A",
  62         },
  63         {
  64                 .id = 1,
  65                 .name = "Channel B",
  66         }
  67 };
  68
  69 static struct counter_synapse mchp_tc_count_synapses[] = {
  70         {
  71                 .actions_list = mchp_tc_synapse_actions,
  72                 .num_actions = ARRAY_SIZE(mchp_tc_synapse_actions),
  73                 .signal = &mchp_tc_count_signals[0]
  74         },
  75         {
  76                 .actions_list = mchp_tc_synapse_actions,
  77                 .num_actions = ARRAY_SIZE(mchp_tc_synapse_actions),
  78                 .signal = &mchp_tc_count_signals[1]
  79         }
  80 };
  81
  82 static int mchp_tc_count_function_get(struct counter_device *counter,
  83                                       struct counter_count *count,
  84                                       size_t *function)
  85 {
  86         struct mchp_tc_data *const priv = counter->priv;
  87
  88         if (priv->qdec_mode)
  89                 *function = MCHP_TC_FUNCTION_QUADRATURE;
  90         else
  91                 *function = MCHP_TC_FUNCTION_INCREASE;
  92
  93         return 0;
  94 }
  95
  96 static int mchp_tc_count_function_set(struct counter_device *counter,
  97                                       struct counter_count *count,
  98                                       size_t function)
  99 {
 100         struct mchp_tc_data *const priv = counter->priv;
 101         u32 bmr, cmr;
 102
 103         regmap_read(priv->regmap, ATMEL_TC_BMR, &bmr);
 104         regmap_read(priv->regmap, ATMEL_TC_REG(priv->channel[0], CMR), &cmr);
 105
 106         /* Set capture mode */
 107         cmr &= ~ATMEL_TC_WAVE;
 108
 109         switch (function) {
 110         case MCHP_TC_FUNCTION_INCREASE:
 111                 priv->qdec_mode = 0;
 112                 /* Set highest rate based on whether soc has gclk or not */
 113                 bmr &= ~(ATMEL_TC_QDEN | ATMEL_TC_POSEN);
 114                 if (priv->tc_cfg->has_gclk)
 115                         cmr |= ATMEL_TC_TIMER_CLOCK2;
 116                 else
 117                         cmr |= ATMEL_TC_TIMER_CLOCK1;
 118                 /* Setup the period capture mode */
 119                 cmr |=  ATMEL_TC_CMR_MASK;
 120                 cmr &= ~(ATMEL_TC_ABETRG | ATMEL_TC_XC0);
 121                 break;
 122         case MCHP_TC_FUNCTION_QUADRATURE:
 123                 if (!priv->tc_cfg->has_qdec)
 124                         return -EINVAL;
 125                 /* In QDEC mode settings both channels 0 and 1 are required */
 126                 if (priv->num_channels < 2 || priv->channel[0] != 0 ||
 127                     priv->channel[1] != 1) {
 128                         pr_err("Invalid channels number or id for quadrature mode\n");
 129                         return -EINVAL;
 130                 }
 131                 priv->qdec_mode = 1;
 132                 bmr |= ATMEL_TC_QDEN | ATMEL_TC_POSEN;
 133                 cmr |= ATMEL_TC_ETRGEDG_RISING | ATMEL_TC_ABETRG | ATMEL_TC_XC0;
 134                 break;
 135         default:
 136                 /* should never reach this path */
 137                 return -EINVAL;
 138         }
 139
 140         regmap_write(priv->regmap, ATMEL_TC_BMR, bmr);
 141         regmap_write(priv->regmap, ATMEL_TC_REG(priv->channel[0], CMR), cmr);
 142
 143         /* Enable clock and trigger counter */
 144         regmap_write(priv->regmap, ATMEL_TC_REG(priv->channel[0], CCR),
 145                      ATMEL_TC_CLKEN | ATMEL_TC_SWTRG);
 146
 147         if (priv->qdec_mode) {
 148                 regmap_write(priv->regmap,
 149                              ATMEL_TC_REG(priv->channel[1], CMR), cmr);
 150                 regmap_write(priv->regmap,
 151                              ATMEL_TC_REG(priv->channel[1], CCR),
 152                              ATMEL_TC_CLKEN | ATMEL_TC_SWTRG);
 153         }
 154
 155         return 0;
 156 }
 157
 158 static int mchp_tc_count_signal_read(struct counter_device *counter,
 159                                      struct counter_signal *signal,
 160                                      enum counter_signal_level *lvl)
 161 {
 162         struct mchp_tc_data *const priv = counter->priv;
 163         bool sigstatus;
 164         u32 sr;
 165
 166         regmap_read(priv->regmap, ATMEL_TC_REG(priv->channel[0], SR), &sr);
 167
 168         if (signal->id == 1)
 169                 sigstatus = (sr & ATMEL_TC_MTIOB);
 170         else
 171                 sigstatus = (sr & ATMEL_TC_MTIOA);
 172
 173         *lvl = sigstatus ? COUNTER_SIGNAL_LEVEL_HIGH : COUNTER_SIGNAL_LEVEL_LOW;
 174
 175         return 0;
 176 }
 177
 178 static int mchp_tc_count_action_get(struct counter_device *counter,
 179                                     struct counter_count *count,
 180                                     struct counter_synapse *synapse,
 181                                     size_t *action)
 182 {
 183         struct mchp_tc_data *const priv = counter->priv;
 184         u32 cmr;
 185
 186         if (priv->qdec_mode) {
 187                 *action = COUNTER_SYNAPSE_ACTION_BOTH_EDGES;
 188                 return 0;
 189         }
 190
 191         /* Only TIOA signal is evaluated in non-QDEC mode */
 192         if (synapse->signal->id != 0) {
 193                 *action = COUNTER_SYNAPSE_ACTION_NONE;
 194                 return 0;
 195         }
 196
 197         regmap_read(priv->regmap, ATMEL_TC_REG(priv->channel[0], CMR), &cmr);
 198
 199         switch (cmr & ATMEL_TC_ETRGEDG) {
 200         default:
 201                 *action = MCHP_TC_SYNAPSE_ACTION_NONE;
 202                 break;
 203         case ATMEL_TC_ETRGEDG_RISING:
 204                 *action = MCHP_TC_SYNAPSE_ACTION_RISING_EDGE;
 205                 break;
 206         case ATMEL_TC_ETRGEDG_FALLING:
 207                 *action = MCHP_TC_SYNAPSE_ACTION_FALLING_EDGE;
 208                 break;
 209         case ATMEL_TC_ETRGEDG_BOTH:
 210                 *action = MCHP_TC_SYNAPSE_ACTION_BOTH_EDGE;
 211                 break;
 212         }
 213
 214         return 0;
 215 }
 216
 217 static int mchp_tc_count_action_set(struct counter_device *counter,
 218                                     struct counter_count *count,
 219                                     struct counter_synapse *synapse,
 220                                     size_t action)
 221 {
 222         struct mchp_tc_data *const priv = counter->priv;
 223         u32 edge = ATMEL_TC_ETRGEDG_NONE;
 224
 225         /* QDEC mode is rising edge only; only TIOA handled in non-QDEC mode */
 226         if (priv->qdec_mode || synapse->signal->id != 0)
 227                 return -EINVAL;
 228
 229         switch (action) {
 230         case MCHP_TC_SYNAPSE_ACTION_NONE:
 231                 edge = ATMEL_TC_ETRGEDG_NONE;
 232                 break;
 233         case MCHP_TC_SYNAPSE_ACTION_RISING_EDGE:
 234                 edge = ATMEL_TC_ETRGEDG_RISING;
 235                 break;
 236         case MCHP_TC_SYNAPSE_ACTION_FALLING_EDGE:
 237                 edge = ATMEL_TC_ETRGEDG_FALLING;
 238                 break;
 239         case MCHP_TC_SYNAPSE_ACTION_BOTH_EDGE:
 240                 edge = ATMEL_TC_ETRGEDG_BOTH;
 241                 break;
 242         default:
 243                 /* should never reach this path */
 244                 return -EINVAL;
 245         }
 246
 247         return regmap_write_bits(priv->regmap,
 248                                 ATMEL_TC_REG(priv->channel[0], CMR),
 249                                 ATMEL_TC_ETRGEDG, edge);
 250 }
 251
 252 static int mchp_tc_count_read(struct counter_device *counter,
 253                               struct counter_count *count,
 254                               unsigned long *val)
 255 {
 256         struct mchp_tc_data *const priv = counter->priv;
 257         u32 cnt;
 258
 259         regmap_read(priv->regmap, ATMEL_TC_REG(priv->channel[0], CV), &cnt);
 260         *val = cnt;
 261
 262         return 0;
 263 }
 264
 265 static struct counter_count mchp_tc_counts[] = {
 266         {
 267                 .id = 0,
 268                 .name = "Timer Counter",
 269                 .functions_list = mchp_tc_count_functions,
 270                 .num_functions = ARRAY_SIZE(mchp_tc_count_functions),
 271                 .synapses = mchp_tc_count_synapses,
 272                 .num_synapses = ARRAY_SIZE(mchp_tc_count_synapses),
 273         },
 274 };
 275
 276 static const struct counter_ops mchp_tc_ops = {
 277         .signal_read  = mchp_tc_count_signal_read,
 278         .count_read   = mchp_tc_count_read,
 279         .function_get = mchp_tc_count_function_get,
 280         .function_set = mchp_tc_count_function_set,
 281         .action_get   = mchp_tc_count_action_get,
 282         .action_set   = mchp_tc_count_action_set
 283 };
 284
 285 static const struct atmel_tcb_config tcb_rm9200_config = {
 286                 .counter_width = 16,
 287 };
 288
 289 static const struct atmel_tcb_config tcb_sam9x5_config = {
 290                 .counter_width = 32,
 291 };
 292
 293 static const struct atmel_tcb_config tcb_sama5d2_config = {
 294                 .counter_width = 32,
 295                 .has_gclk = true,
 296                 .has_qdec = true,
 297 };
 298
 299 static const struct atmel_tcb_config tcb_sama5d3_config = {
 300                 .counter_width = 32,
 301                 .has_qdec = true,
 302 };
 303
 304 static const struct of_device_id atmel_tc_of_match[] = {
 305         { .compatible = "atmel,at91rm9200-tcb", .data = &tcb_rm9200_config, },
 306         { .compatible = "atmel,at91sam9x5-tcb", .data = &tcb_sam9x5_config, },
 307         { .compatible = "atmel,sama5d2-tcb", .data = &tcb_sama5d2_config, },
 308         { .compatible = "atmel,sama5d3-tcb", .data = &tcb_sama5d3_config, },
 309         { /* sentinel */ }
 310 };
 311
 312 static void mchp_tc_clk_remove(void *ptr)
 313 {
 314         clk_disable_unprepare((struct clk *)ptr);
 315 }
 316
 317 static int mchp_tc_probe(struct platform_device *pdev)
 318 {
 319         struct device_node *np = pdev->dev.of_node;
 320         const struct atmel_tcb_config *tcb_config;
 321         const struct of_device_id *match;
 322         struct mchp_tc_data *priv;
 323         char clk_name[7];
 324         struct regmap *regmap;
 325         struct clk *clk[3];
 326         int channel;
 327         int ret, i;
 328
 329         priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
 330         if (!priv)
 331                 return -ENOMEM;
 332
 333         platform_set_drvdata(pdev, priv);
 334
 335         match = of_match_node(atmel_tc_of_match, np->parent);
 336         tcb_config = match->data;
 337         if (!tcb_config) {
 338                 dev_err(&pdev->dev, "No matching parent node found\n");
 339                 return -ENODEV;
 340         }
 341
 342         regmap = syscon_node_to_regmap(np->parent);
 343         if (IS_ERR(regmap))
 344                 return PTR_ERR(regmap);
 345
 346         /* max. channels number is 2 when in QDEC mode */
 347         priv->num_channels = of_property_count_u32_elems(np, "reg");
 348         if (priv->num_channels < 0) {
 349                 dev_err(&pdev->dev, "Invalid or missing channel\n");
 350                 return -EINVAL;
 351         }
 352
 353         /* Register channels and initialize clocks */
 354         for (i = 0; i < priv->num_channels; i++) {
 355                 ret = of_property_read_u32_index(np, "reg", i, &channel);
 356                 if (ret < 0 || channel > 2)
 357                         return -ENODEV;
 358
 359                 priv->channel[i] = channel;
 360
 361                 snprintf(clk_name, sizeof(clk_name), "t%d_clk", channel);
 362
 363                 clk[i] = of_clk_get_by_name(np->parent, clk_name);
 364                 if (IS_ERR(clk[i])) {
 365                         /* Fallback to t0_clk */
 366                         clk[i] = of_clk_get_by_name(np->parent, "t0_clk");
 367                         if (IS_ERR(clk[i]))
 368                                 return PTR_ERR(clk[i]);
 369                 }
 370
 371                 ret = clk_prepare_enable(clk[i]);
 372                 if (ret)
 373                         return ret;
 374
 375                 ret = devm_add_action_or_reset(&pdev->dev,
 376                                                mchp_tc_clk_remove,
 377                                                clk[i]);
 378                 if (ret)
 379                         return ret;
 380
 381                 dev_dbg(&pdev->dev,
 382                         "Initialized capture mode on channel %d\n",
 383                         channel);
 384         }
 385
 386         priv->tc_cfg = tcb_config;
 387         priv->regmap = regmap;
 388         priv->counter.name = dev_name(&pdev->dev);
 389         priv->counter.parent = &pdev->dev;
 390         priv->counter.ops = &mchp_tc_ops;
 391         priv->counter.num_counts = ARRAY_SIZE(mchp_tc_counts);
 392         priv->counter.counts = mchp_tc_counts;
 393         priv->counter.num_signals = ARRAY_SIZE(mchp_tc_count_signals);
 394         priv->counter.signals = mchp_tc_count_signals;
 395         priv->counter.priv = priv;
 396
 397         return devm_counter_register(&pdev->dev, &priv->counter);
 398 }
 399
 400 static const struct of_device_id mchp_tc_dt_ids[] = {
 401         { .compatible = "microchip,tcb-capture", },
 402         { /* sentinel */ },
 403 };
 404 MODULE_DEVICE_TABLE(of, mchp_tc_dt_ids);
 405
 406 static struct platform_driver mchp_tc_driver = {
 407         .probe = mchp_tc_probe,
 408         .driver = {
 409                 .name = "microchip-tcb-capture",
 410                 .of_match_table = mchp_tc_dt_ids,
 411         },
 412 };
 413 module_platform_driver(mchp_tc_driver);
 414
 415 MODULE_AUTHOR("Kamel Bouhara <kamel.bouhara@bootlin.com>");
 416 MODULE_DESCRIPTION("Microchip TCB Capture driver");
 417 MODULE_LICENSE("GPL v2");