1 // SPDX-License-Identifier: GPL-2.0
3 * Counter driver for the ACCES 104-QUAD-8
4 * Copyright (C) 2016 William Breathitt Gray
6 * This driver supports the ACCES 104-QUAD-8 and ACCES 104-QUAD-4.
8 #include <linux/bitops.h>
9 #include <linux/counter.h>
10 #include <linux/device.h>
11 #include <linux/errno.h>
13 #include <linux/ioport.h>
14 #include <linux/isa.h>
15 #include <linux/kernel.h>
16 #include <linux/module.h>
17 #include <linux/moduleparam.h>
18 #include <linux/types.h>
20 #define QUAD8_EXTENT 32
22 static unsigned int base[max_num_isa_dev(QUAD8_EXTENT)];
23 static unsigned int num_quad8;
24 module_param_hw_array(base, uint, ioport, &num_quad8, 0);
25 MODULE_PARM_DESC(base, "ACCES 104-QUAD-8 base addresses");
27 #define QUAD8_NUM_COUNTERS 8
30 * struct quad8 - device private data structure
31 * @lock: lock to prevent clobbering device states during R/W ops
32 * @counter: instance of the counter_device
33 * @fck_prescaler: array of filter clock prescaler configurations
34 * @preset: array of preset values
35 * @count_mode: array of count mode configurations
36 * @quadrature_mode: array of quadrature mode configurations
37 * @quadrature_scale: array of quadrature mode scale configurations
38 * @ab_enable: array of A and B inputs enable configurations
39 * @preset_enable: array of set_to_preset_on_index attribute configurations
40 * @synchronous_mode: array of index function synchronous mode configurations
41 * @index_polarity: array of index function polarity configurations
42 * @cable_fault_enable: differential encoder cable status enable configurations
43 * @base: base port address of the device
47 struct counter_device counter;
48 unsigned int fck_prescaler[QUAD8_NUM_COUNTERS];
49 unsigned int preset[QUAD8_NUM_COUNTERS];
50 unsigned int count_mode[QUAD8_NUM_COUNTERS];
51 unsigned int quadrature_mode[QUAD8_NUM_COUNTERS];
52 unsigned int quadrature_scale[QUAD8_NUM_COUNTERS];
53 unsigned int ab_enable[QUAD8_NUM_COUNTERS];
54 unsigned int preset_enable[QUAD8_NUM_COUNTERS];
55 unsigned int synchronous_mode[QUAD8_NUM_COUNTERS];
56 unsigned int index_polarity[QUAD8_NUM_COUNTERS];
57 unsigned int cable_fault_enable;
61 #define QUAD8_REG_CHAN_OP 0x11
62 #define QUAD8_REG_INDEX_INPUT_LEVELS 0x16
63 #define QUAD8_DIFF_ENCODER_CABLE_STATUS 0x17
64 /* Borrow Toggle flip-flop */
65 #define QUAD8_FLAG_BT BIT(0)
66 /* Carry Toggle flip-flop */
67 #define QUAD8_FLAG_CT BIT(1)
69 #define QUAD8_FLAG_E BIT(4)
71 #define QUAD8_FLAG_UD BIT(5)
72 /* Reset and Load Signal Decoders */
73 #define QUAD8_CTR_RLD 0x00
74 /* Counter Mode Register */
75 #define QUAD8_CTR_CMR 0x20
76 /* Input / Output Control Register */
77 #define QUAD8_CTR_IOR 0x40
78 /* Index Control Register */
79 #define QUAD8_CTR_IDR 0x60
80 /* Reset Byte Pointer (three byte data pointer) */
81 #define QUAD8_RLD_RESET_BP 0x01
83 #define QUAD8_RLD_RESET_CNTR 0x02
84 /* Reset Borrow Toggle, Carry Toggle, Compare Toggle, and Sign flags */
85 #define QUAD8_RLD_RESET_FLAGS 0x04
86 /* Reset Error flag */
87 #define QUAD8_RLD_RESET_E 0x06
88 /* Preset Register to Counter */
89 #define QUAD8_RLD_PRESET_CNTR 0x08
90 /* Transfer Counter to Output Latch */
91 #define QUAD8_RLD_CNTR_OUT 0x10
92 /* Transfer Preset Register LSB to FCK Prescaler */
93 #define QUAD8_RLD_PRESET_PSC 0x18
94 #define QUAD8_CHAN_OP_ENABLE_COUNTERS 0x00
95 #define QUAD8_CHAN_OP_RESET_COUNTERS 0x01
96 #define QUAD8_CMR_QUADRATURE_X1 0x08
97 #define QUAD8_CMR_QUADRATURE_X2 0x10
98 #define QUAD8_CMR_QUADRATURE_X4 0x18
100 static int quad8_signal_read(struct counter_device *counter,
101 struct counter_signal *signal,
102 enum counter_signal_level *level)
104 const struct quad8 *const priv = counter->priv;
107 /* Only Index signal levels can be read */
111 state = inb(priv->base + QUAD8_REG_INDEX_INPUT_LEVELS)
112 & BIT(signal->id - 16);
114 *level = (state) ? COUNTER_SIGNAL_LEVEL_HIGH : COUNTER_SIGNAL_LEVEL_LOW;
119 static int quad8_count_read(struct counter_device *counter,
120 struct counter_count *count, unsigned long *val)
122 struct quad8 *const priv = counter->priv;
123 const int base_offset = priv->base + 2 * count->id;
129 flags = inb(base_offset + 1);
130 borrow = flags & QUAD8_FLAG_BT;
131 carry = !!(flags & QUAD8_FLAG_CT);
133 /* Borrow XOR Carry effectively doubles count range */
134 *val = (unsigned long)(borrow ^ carry) << 24;
136 mutex_lock(&priv->lock);
138 /* Reset Byte Pointer; transfer Counter to Output Latch */
139 outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP | QUAD8_RLD_CNTR_OUT,
142 for (i = 0; i < 3; i++)
143 *val |= (unsigned long)inb(base_offset) << (8 * i);
145 mutex_unlock(&priv->lock);
150 static int quad8_count_write(struct counter_device *counter,
151 struct counter_count *count, unsigned long val)
153 struct quad8 *const priv = counter->priv;
154 const int base_offset = priv->base + 2 * count->id;
157 /* Only 24-bit values are supported */
161 mutex_lock(&priv->lock);
163 /* Reset Byte Pointer */
164 outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP, base_offset + 1);
166 /* Counter can only be set via Preset Register */
167 for (i = 0; i < 3; i++)
168 outb(val >> (8 * i), base_offset);
170 /* Transfer Preset Register to Counter */
171 outb(QUAD8_CTR_RLD | QUAD8_RLD_PRESET_CNTR, base_offset + 1);
173 /* Reset Byte Pointer */
174 outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP, base_offset + 1);
176 /* Set Preset Register back to original value */
177 val = priv->preset[count->id];
178 for (i = 0; i < 3; i++)
179 outb(val >> (8 * i), base_offset);
181 /* Reset Borrow, Carry, Compare, and Sign flags */
182 outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_FLAGS, base_offset + 1);
183 /* Reset Error flag */
184 outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_E, base_offset + 1);
186 mutex_unlock(&priv->lock);
191 enum quad8_count_function {
192 QUAD8_COUNT_FUNCTION_PULSE_DIRECTION = 0,
193 QUAD8_COUNT_FUNCTION_QUADRATURE_X1,
194 QUAD8_COUNT_FUNCTION_QUADRATURE_X2,
195 QUAD8_COUNT_FUNCTION_QUADRATURE_X4
198 static const enum counter_function quad8_count_functions_list[] = {
199 [QUAD8_COUNT_FUNCTION_PULSE_DIRECTION] = COUNTER_FUNCTION_PULSE_DIRECTION,
200 [QUAD8_COUNT_FUNCTION_QUADRATURE_X1] = COUNTER_FUNCTION_QUADRATURE_X1_A,
201 [QUAD8_COUNT_FUNCTION_QUADRATURE_X2] = COUNTER_FUNCTION_QUADRATURE_X2_A,
202 [QUAD8_COUNT_FUNCTION_QUADRATURE_X4] = COUNTER_FUNCTION_QUADRATURE_X4
205 static int quad8_function_get(struct counter_device *counter,
206 struct counter_count *count, size_t *function)
208 struct quad8 *const priv = counter->priv;
209 const int id = count->id;
211 mutex_lock(&priv->lock);
213 if (priv->quadrature_mode[id])
214 switch (priv->quadrature_scale[id]) {
216 *function = QUAD8_COUNT_FUNCTION_QUADRATURE_X1;
219 *function = QUAD8_COUNT_FUNCTION_QUADRATURE_X2;
222 *function = QUAD8_COUNT_FUNCTION_QUADRATURE_X4;
226 *function = QUAD8_COUNT_FUNCTION_PULSE_DIRECTION;
228 mutex_unlock(&priv->lock);
233 static int quad8_function_set(struct counter_device *counter,
234 struct counter_count *count, size_t function)
236 struct quad8 *const priv = counter->priv;
237 const int id = count->id;
238 unsigned int *const quadrature_mode = priv->quadrature_mode + id;
239 unsigned int *const scale = priv->quadrature_scale + id;
240 unsigned int *const synchronous_mode = priv->synchronous_mode + id;
241 const int base_offset = priv->base + 2 * id + 1;
242 unsigned int mode_cfg;
243 unsigned int idr_cfg;
245 mutex_lock(&priv->lock);
247 mode_cfg = priv->count_mode[id] << 1;
248 idr_cfg = priv->index_polarity[id] << 1;
250 if (function == QUAD8_COUNT_FUNCTION_PULSE_DIRECTION) {
251 *quadrature_mode = 0;
253 /* Quadrature scaling only available in quadrature mode */
256 /* Synchronous function not supported in non-quadrature mode */
257 if (*synchronous_mode) {
258 *synchronous_mode = 0;
259 /* Disable synchronous function mode */
260 outb(QUAD8_CTR_IDR | idr_cfg, base_offset);
263 *quadrature_mode = 1;
266 case QUAD8_COUNT_FUNCTION_QUADRATURE_X1:
268 mode_cfg |= QUAD8_CMR_QUADRATURE_X1;
270 case QUAD8_COUNT_FUNCTION_QUADRATURE_X2:
272 mode_cfg |= QUAD8_CMR_QUADRATURE_X2;
274 case QUAD8_COUNT_FUNCTION_QUADRATURE_X4:
276 mode_cfg |= QUAD8_CMR_QUADRATURE_X4;
279 /* should never reach this path */
280 mutex_unlock(&priv->lock);
285 /* Load mode configuration to Counter Mode Register */
286 outb(QUAD8_CTR_CMR | mode_cfg, base_offset);
288 mutex_unlock(&priv->lock);
293 static void quad8_direction_get(struct counter_device *counter,
294 struct counter_count *count, enum counter_count_direction *direction)
296 const struct quad8 *const priv = counter->priv;
297 unsigned int ud_flag;
298 const unsigned int flag_addr = priv->base + 2 * count->id + 1;
300 /* U/D flag: nonzero = up, zero = down */
301 ud_flag = inb(flag_addr) & QUAD8_FLAG_UD;
303 *direction = (ud_flag) ? COUNTER_COUNT_DIRECTION_FORWARD :
304 COUNTER_COUNT_DIRECTION_BACKWARD;
307 enum quad8_synapse_action {
308 QUAD8_SYNAPSE_ACTION_NONE = 0,
309 QUAD8_SYNAPSE_ACTION_RISING_EDGE,
310 QUAD8_SYNAPSE_ACTION_FALLING_EDGE,
311 QUAD8_SYNAPSE_ACTION_BOTH_EDGES
314 static const enum counter_synapse_action quad8_index_actions_list[] = {
315 [QUAD8_SYNAPSE_ACTION_NONE] = COUNTER_SYNAPSE_ACTION_NONE,
316 [QUAD8_SYNAPSE_ACTION_RISING_EDGE] = COUNTER_SYNAPSE_ACTION_RISING_EDGE
319 static const enum counter_synapse_action quad8_synapse_actions_list[] = {
320 [QUAD8_SYNAPSE_ACTION_NONE] = COUNTER_SYNAPSE_ACTION_NONE,
321 [QUAD8_SYNAPSE_ACTION_RISING_EDGE] = COUNTER_SYNAPSE_ACTION_RISING_EDGE,
322 [QUAD8_SYNAPSE_ACTION_FALLING_EDGE] = COUNTER_SYNAPSE_ACTION_FALLING_EDGE,
323 [QUAD8_SYNAPSE_ACTION_BOTH_EDGES] = COUNTER_SYNAPSE_ACTION_BOTH_EDGES
326 static int quad8_action_get(struct counter_device *counter,
327 struct counter_count *count, struct counter_synapse *synapse,
330 struct quad8 *const priv = counter->priv;
333 const size_t signal_a_id = count->synapses[0].signal->id;
334 enum counter_count_direction direction;
336 /* Handle Index signals */
337 if (synapse->signal->id >= 16) {
338 if (priv->preset_enable[count->id])
339 *action = QUAD8_SYNAPSE_ACTION_RISING_EDGE;
341 *action = QUAD8_SYNAPSE_ACTION_NONE;
346 err = quad8_function_get(counter, count, &function);
350 /* Default action mode */
351 *action = QUAD8_SYNAPSE_ACTION_NONE;
353 /* Determine action mode based on current count function mode */
355 case QUAD8_COUNT_FUNCTION_PULSE_DIRECTION:
356 if (synapse->signal->id == signal_a_id)
357 *action = QUAD8_SYNAPSE_ACTION_RISING_EDGE;
359 case QUAD8_COUNT_FUNCTION_QUADRATURE_X1:
360 if (synapse->signal->id == signal_a_id) {
361 quad8_direction_get(counter, count, &direction);
363 if (direction == COUNTER_COUNT_DIRECTION_FORWARD)
364 *action = QUAD8_SYNAPSE_ACTION_RISING_EDGE;
366 *action = QUAD8_SYNAPSE_ACTION_FALLING_EDGE;
369 case QUAD8_COUNT_FUNCTION_QUADRATURE_X2:
370 if (synapse->signal->id == signal_a_id)
371 *action = QUAD8_SYNAPSE_ACTION_BOTH_EDGES;
373 case QUAD8_COUNT_FUNCTION_QUADRATURE_X4:
374 *action = QUAD8_SYNAPSE_ACTION_BOTH_EDGES;
377 /* should never reach this path */
382 static const struct counter_ops quad8_ops = {
383 .signal_read = quad8_signal_read,
384 .count_read = quad8_count_read,
385 .count_write = quad8_count_write,
386 .function_get = quad8_function_get,
387 .function_set = quad8_function_set,
388 .action_get = quad8_action_get
391 static const char *const quad8_index_polarity_modes[] = {
396 static int quad8_index_polarity_get(struct counter_device *counter,
397 struct counter_signal *signal, size_t *index_polarity)
399 const struct quad8 *const priv = counter->priv;
400 const size_t channel_id = signal->id - 16;
402 *index_polarity = priv->index_polarity[channel_id];
407 static int quad8_index_polarity_set(struct counter_device *counter,
408 struct counter_signal *signal, size_t index_polarity)
410 struct quad8 *const priv = counter->priv;
411 const size_t channel_id = signal->id - 16;
412 const int base_offset = priv->base + 2 * channel_id + 1;
413 unsigned int idr_cfg = index_polarity << 1;
415 mutex_lock(&priv->lock);
417 idr_cfg |= priv->synchronous_mode[channel_id];
419 priv->index_polarity[channel_id] = index_polarity;
421 /* Load Index Control configuration to Index Control Register */
422 outb(QUAD8_CTR_IDR | idr_cfg, base_offset);
424 mutex_unlock(&priv->lock);
429 static struct counter_signal_enum_ext quad8_index_pol_enum = {
430 .items = quad8_index_polarity_modes,
431 .num_items = ARRAY_SIZE(quad8_index_polarity_modes),
432 .get = quad8_index_polarity_get,
433 .set = quad8_index_polarity_set
436 static const char *const quad8_synchronous_modes[] = {
441 static int quad8_synchronous_mode_get(struct counter_device *counter,
442 struct counter_signal *signal, size_t *synchronous_mode)
444 const struct quad8 *const priv = counter->priv;
445 const size_t channel_id = signal->id - 16;
447 *synchronous_mode = priv->synchronous_mode[channel_id];
452 static int quad8_synchronous_mode_set(struct counter_device *counter,
453 struct counter_signal *signal, size_t synchronous_mode)
455 struct quad8 *const priv = counter->priv;
456 const size_t channel_id = signal->id - 16;
457 const int base_offset = priv->base + 2 * channel_id + 1;
458 unsigned int idr_cfg = synchronous_mode;
460 mutex_lock(&priv->lock);
462 idr_cfg |= priv->index_polarity[channel_id] << 1;
464 /* Index function must be non-synchronous in non-quadrature mode */
465 if (synchronous_mode && !priv->quadrature_mode[channel_id]) {
466 mutex_unlock(&priv->lock);
470 priv->synchronous_mode[channel_id] = synchronous_mode;
472 /* Load Index Control configuration to Index Control Register */
473 outb(QUAD8_CTR_IDR | idr_cfg, base_offset);
475 mutex_unlock(&priv->lock);
480 static struct counter_signal_enum_ext quad8_syn_mode_enum = {
481 .items = quad8_synchronous_modes,
482 .num_items = ARRAY_SIZE(quad8_synchronous_modes),
483 .get = quad8_synchronous_mode_get,
484 .set = quad8_synchronous_mode_set
487 static ssize_t quad8_count_floor_read(struct counter_device *counter,
488 struct counter_count *count, void *private, char *buf)
490 /* Only a floor of 0 is supported */
491 return sprintf(buf, "0\n");
494 static int quad8_count_mode_get(struct counter_device *counter,
495 struct counter_count *count, size_t *cnt_mode)
497 const struct quad8 *const priv = counter->priv;
499 /* Map 104-QUAD-8 count mode to Generic Counter count mode */
500 switch (priv->count_mode[count->id]) {
502 *cnt_mode = COUNTER_COUNT_MODE_NORMAL;
505 *cnt_mode = COUNTER_COUNT_MODE_RANGE_LIMIT;
508 *cnt_mode = COUNTER_COUNT_MODE_NON_RECYCLE;
511 *cnt_mode = COUNTER_COUNT_MODE_MODULO_N;
518 static int quad8_count_mode_set(struct counter_device *counter,
519 struct counter_count *count, size_t cnt_mode)
521 struct quad8 *const priv = counter->priv;
522 unsigned int mode_cfg;
523 const int base_offset = priv->base + 2 * count->id + 1;
525 /* Map Generic Counter count mode to 104-QUAD-8 count mode */
527 case COUNTER_COUNT_MODE_NORMAL:
530 case COUNTER_COUNT_MODE_RANGE_LIMIT:
533 case COUNTER_COUNT_MODE_NON_RECYCLE:
536 case COUNTER_COUNT_MODE_MODULO_N:
540 /* should never reach this path */
544 mutex_lock(&priv->lock);
546 priv->count_mode[count->id] = cnt_mode;
548 /* Set count mode configuration value */
549 mode_cfg = cnt_mode << 1;
551 /* Add quadrature mode configuration */
552 if (priv->quadrature_mode[count->id])
553 mode_cfg |= (priv->quadrature_scale[count->id] + 1) << 3;
555 /* Load mode configuration to Counter Mode Register */
556 outb(QUAD8_CTR_CMR | mode_cfg, base_offset);
558 mutex_unlock(&priv->lock);
563 static struct counter_count_enum_ext quad8_cnt_mode_enum = {
564 .items = counter_count_mode_str,
565 .num_items = ARRAY_SIZE(counter_count_mode_str),
566 .get = quad8_count_mode_get,
567 .set = quad8_count_mode_set
570 static ssize_t quad8_count_direction_read(struct counter_device *counter,
571 struct counter_count *count, void *priv, char *buf)
573 enum counter_count_direction dir;
575 quad8_direction_get(counter, count, &dir);
577 return sprintf(buf, "%s\n", counter_count_direction_str[dir]);
580 static ssize_t quad8_count_enable_read(struct counter_device *counter,
581 struct counter_count *count, void *private, char *buf)
583 const struct quad8 *const priv = counter->priv;
585 return sprintf(buf, "%u\n", priv->ab_enable[count->id]);
588 static ssize_t quad8_count_enable_write(struct counter_device *counter,
589 struct counter_count *count, void *private, const char *buf, size_t len)
591 struct quad8 *const priv = counter->priv;
592 const int base_offset = priv->base + 2 * count->id;
595 unsigned int ior_cfg;
597 err = kstrtobool(buf, &ab_enable);
601 mutex_lock(&priv->lock);
603 priv->ab_enable[count->id] = ab_enable;
605 ior_cfg = ab_enable | priv->preset_enable[count->id] << 1;
607 /* Load I/O control configuration */
608 outb(QUAD8_CTR_IOR | ior_cfg, base_offset + 1);
610 mutex_unlock(&priv->lock);
615 static const char *const quad8_noise_error_states[] = {
616 "No excessive noise is present at the count inputs",
617 "Excessive noise is present at the count inputs"
620 static int quad8_error_noise_get(struct counter_device *counter,
621 struct counter_count *count, size_t *noise_error)
623 const struct quad8 *const priv = counter->priv;
624 const int base_offset = priv->base + 2 * count->id + 1;
626 *noise_error = !!(inb(base_offset) & QUAD8_FLAG_E);
631 static struct counter_count_enum_ext quad8_error_noise_enum = {
632 .items = quad8_noise_error_states,
633 .num_items = ARRAY_SIZE(quad8_noise_error_states),
634 .get = quad8_error_noise_get
637 static ssize_t quad8_count_preset_read(struct counter_device *counter,
638 struct counter_count *count, void *private, char *buf)
640 const struct quad8 *const priv = counter->priv;
642 return sprintf(buf, "%u\n", priv->preset[count->id]);
645 static void quad8_preset_register_set(struct quad8 *const priv, const int id,
646 const unsigned int preset)
648 const unsigned int base_offset = priv->base + 2 * id;
651 priv->preset[id] = preset;
653 /* Reset Byte Pointer */
654 outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP, base_offset + 1);
656 /* Set Preset Register */
657 for (i = 0; i < 3; i++)
658 outb(preset >> (8 * i), base_offset);
661 static ssize_t quad8_count_preset_write(struct counter_device *counter,
662 struct counter_count *count, void *private, const char *buf, size_t len)
664 struct quad8 *const priv = counter->priv;
668 ret = kstrtouint(buf, 0, &preset);
672 /* Only 24-bit values are supported */
673 if (preset > 0xFFFFFF)
676 mutex_lock(&priv->lock);
678 quad8_preset_register_set(priv, count->id, preset);
680 mutex_unlock(&priv->lock);
685 static ssize_t quad8_count_ceiling_read(struct counter_device *counter,
686 struct counter_count *count, void *private, char *buf)
688 struct quad8 *const priv = counter->priv;
690 mutex_lock(&priv->lock);
692 /* Range Limit and Modulo-N count modes use preset value as ceiling */
693 switch (priv->count_mode[count->id]) {
696 mutex_unlock(&priv->lock);
697 return sprintf(buf, "%u\n", priv->preset[count->id]);
700 mutex_unlock(&priv->lock);
702 /* By default 0x1FFFFFF (25 bits unsigned) is maximum count */
703 return sprintf(buf, "33554431\n");
706 static ssize_t quad8_count_ceiling_write(struct counter_device *counter,
707 struct counter_count *count, void *private, const char *buf, size_t len)
709 struct quad8 *const priv = counter->priv;
710 unsigned int ceiling;
713 ret = kstrtouint(buf, 0, &ceiling);
717 /* Only 24-bit values are supported */
718 if (ceiling > 0xFFFFFF)
721 mutex_lock(&priv->lock);
723 /* Range Limit and Modulo-N count modes use preset value as ceiling */
724 switch (priv->count_mode[count->id]) {
727 quad8_preset_register_set(priv, count->id, ceiling);
728 mutex_unlock(&priv->lock);
732 mutex_unlock(&priv->lock);
737 static ssize_t quad8_count_preset_enable_read(struct counter_device *counter,
738 struct counter_count *count, void *private, char *buf)
740 const struct quad8 *const priv = counter->priv;
742 return sprintf(buf, "%u\n", !priv->preset_enable[count->id]);
745 static ssize_t quad8_count_preset_enable_write(struct counter_device *counter,
746 struct counter_count *count, void *private, const char *buf, size_t len)
748 struct quad8 *const priv = counter->priv;
749 const int base_offset = priv->base + 2 * count->id + 1;
752 unsigned int ior_cfg;
754 ret = kstrtobool(buf, &preset_enable);
758 /* Preset enable is active low in Input/Output Control register */
759 preset_enable = !preset_enable;
761 mutex_lock(&priv->lock);
763 priv->preset_enable[count->id] = preset_enable;
765 ior_cfg = priv->ab_enable[count->id] | (unsigned int)preset_enable << 1;
767 /* Load I/O control configuration to Input / Output Control Register */
768 outb(QUAD8_CTR_IOR | ior_cfg, base_offset);
770 mutex_unlock(&priv->lock);
775 static ssize_t quad8_signal_cable_fault_read(struct counter_device *counter,
776 struct counter_signal *signal,
777 void *private, char *buf)
779 struct quad8 *const priv = counter->priv;
780 const size_t channel_id = signal->id / 2;
785 mutex_lock(&priv->lock);
787 disabled = !(priv->cable_fault_enable & BIT(channel_id));
790 mutex_unlock(&priv->lock);
794 /* Logic 0 = cable fault */
795 status = inb(priv->base + QUAD8_DIFF_ENCODER_CABLE_STATUS);
797 mutex_unlock(&priv->lock);
799 /* Mask respective channel and invert logic */
800 fault = !(status & BIT(channel_id));
802 return sprintf(buf, "%u\n", fault);
805 static ssize_t quad8_signal_cable_fault_enable_read(
806 struct counter_device *counter, struct counter_signal *signal,
807 void *private, char *buf)
809 const struct quad8 *const priv = counter->priv;
810 const size_t channel_id = signal->id / 2;
811 const unsigned int enb = !!(priv->cable_fault_enable & BIT(channel_id));
813 return sprintf(buf, "%u\n", enb);
816 static ssize_t quad8_signal_cable_fault_enable_write(
817 struct counter_device *counter, struct counter_signal *signal,
818 void *private, const char *buf, size_t len)
820 struct quad8 *const priv = counter->priv;
821 const size_t channel_id = signal->id / 2;
824 unsigned int cable_fault_enable;
826 ret = kstrtobool(buf, &enable);
830 mutex_lock(&priv->lock);
833 priv->cable_fault_enable |= BIT(channel_id);
835 priv->cable_fault_enable &= ~BIT(channel_id);
837 /* Enable is active low in Differential Encoder Cable Status register */
838 cable_fault_enable = ~priv->cable_fault_enable;
840 outb(cable_fault_enable, priv->base + QUAD8_DIFF_ENCODER_CABLE_STATUS);
842 mutex_unlock(&priv->lock);
847 static ssize_t quad8_signal_fck_prescaler_read(struct counter_device *counter,
848 struct counter_signal *signal, void *private, char *buf)
850 const struct quad8 *const priv = counter->priv;
851 const size_t channel_id = signal->id / 2;
853 return sprintf(buf, "%u\n", priv->fck_prescaler[channel_id]);
856 static ssize_t quad8_signal_fck_prescaler_write(struct counter_device *counter,
857 struct counter_signal *signal, void *private, const char *buf,
860 struct quad8 *const priv = counter->priv;
861 const size_t channel_id = signal->id / 2;
862 const int base_offset = priv->base + 2 * channel_id;
866 ret = kstrtou8(buf, 0, &prescaler);
870 mutex_lock(&priv->lock);
872 priv->fck_prescaler[channel_id] = prescaler;
874 /* Reset Byte Pointer */
875 outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP, base_offset + 1);
877 /* Set filter clock factor */
878 outb(prescaler, base_offset);
879 outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP | QUAD8_RLD_PRESET_PSC,
882 mutex_unlock(&priv->lock);
887 static const struct counter_signal_ext quad8_signal_ext[] = {
889 .name = "cable_fault",
890 .read = quad8_signal_cable_fault_read
893 .name = "cable_fault_enable",
894 .read = quad8_signal_cable_fault_enable_read,
895 .write = quad8_signal_cable_fault_enable_write
898 .name = "filter_clock_prescaler",
899 .read = quad8_signal_fck_prescaler_read,
900 .write = quad8_signal_fck_prescaler_write
904 static const struct counter_signal_ext quad8_index_ext[] = {
905 COUNTER_SIGNAL_ENUM("index_polarity", &quad8_index_pol_enum),
906 COUNTER_SIGNAL_ENUM_AVAILABLE("index_polarity", &quad8_index_pol_enum),
907 COUNTER_SIGNAL_ENUM("synchronous_mode", &quad8_syn_mode_enum),
908 COUNTER_SIGNAL_ENUM_AVAILABLE("synchronous_mode", &quad8_syn_mode_enum)
911 #define QUAD8_QUAD_SIGNAL(_id, _name) { \
914 .ext = quad8_signal_ext, \
915 .num_ext = ARRAY_SIZE(quad8_signal_ext) \
918 #define QUAD8_INDEX_SIGNAL(_id, _name) { \
921 .ext = quad8_index_ext, \
922 .num_ext = ARRAY_SIZE(quad8_index_ext) \
925 static struct counter_signal quad8_signals[] = {
926 QUAD8_QUAD_SIGNAL(0, "Channel 1 Quadrature A"),
927 QUAD8_QUAD_SIGNAL(1, "Channel 1 Quadrature B"),
928 QUAD8_QUAD_SIGNAL(2, "Channel 2 Quadrature A"),
929 QUAD8_QUAD_SIGNAL(3, "Channel 2 Quadrature B"),
930 QUAD8_QUAD_SIGNAL(4, "Channel 3 Quadrature A"),
931 QUAD8_QUAD_SIGNAL(5, "Channel 3 Quadrature B"),
932 QUAD8_QUAD_SIGNAL(6, "Channel 4 Quadrature A"),
933 QUAD8_QUAD_SIGNAL(7, "Channel 4 Quadrature B"),
934 QUAD8_QUAD_SIGNAL(8, "Channel 5 Quadrature A"),
935 QUAD8_QUAD_SIGNAL(9, "Channel 5 Quadrature B"),
936 QUAD8_QUAD_SIGNAL(10, "Channel 6 Quadrature A"),
937 QUAD8_QUAD_SIGNAL(11, "Channel 6 Quadrature B"),
938 QUAD8_QUAD_SIGNAL(12, "Channel 7 Quadrature A"),
939 QUAD8_QUAD_SIGNAL(13, "Channel 7 Quadrature B"),
940 QUAD8_QUAD_SIGNAL(14, "Channel 8 Quadrature A"),
941 QUAD8_QUAD_SIGNAL(15, "Channel 8 Quadrature B"),
942 QUAD8_INDEX_SIGNAL(16, "Channel 1 Index"),
943 QUAD8_INDEX_SIGNAL(17, "Channel 2 Index"),
944 QUAD8_INDEX_SIGNAL(18, "Channel 3 Index"),
945 QUAD8_INDEX_SIGNAL(19, "Channel 4 Index"),
946 QUAD8_INDEX_SIGNAL(20, "Channel 5 Index"),
947 QUAD8_INDEX_SIGNAL(21, "Channel 6 Index"),
948 QUAD8_INDEX_SIGNAL(22, "Channel 7 Index"),
949 QUAD8_INDEX_SIGNAL(23, "Channel 8 Index")
952 #define QUAD8_COUNT_SYNAPSES(_id) { \
954 .actions_list = quad8_synapse_actions_list, \
955 .num_actions = ARRAY_SIZE(quad8_synapse_actions_list), \
956 .signal = quad8_signals + 2 * (_id) \
959 .actions_list = quad8_synapse_actions_list, \
960 .num_actions = ARRAY_SIZE(quad8_synapse_actions_list), \
961 .signal = quad8_signals + 2 * (_id) + 1 \
964 .actions_list = quad8_index_actions_list, \
965 .num_actions = ARRAY_SIZE(quad8_index_actions_list), \
966 .signal = quad8_signals + 2 * (_id) + 16 \
970 static struct counter_synapse quad8_count_synapses[][3] = {
971 QUAD8_COUNT_SYNAPSES(0), QUAD8_COUNT_SYNAPSES(1),
972 QUAD8_COUNT_SYNAPSES(2), QUAD8_COUNT_SYNAPSES(3),
973 QUAD8_COUNT_SYNAPSES(4), QUAD8_COUNT_SYNAPSES(5),
974 QUAD8_COUNT_SYNAPSES(6), QUAD8_COUNT_SYNAPSES(7)
977 static const struct counter_count_ext quad8_count_ext[] = {
980 .read = quad8_count_ceiling_read,
981 .write = quad8_count_ceiling_write
985 .read = quad8_count_floor_read
987 COUNTER_COUNT_ENUM("count_mode", &quad8_cnt_mode_enum),
988 COUNTER_COUNT_ENUM_AVAILABLE("count_mode", &quad8_cnt_mode_enum),
991 .read = quad8_count_direction_read
995 .read = quad8_count_enable_read,
996 .write = quad8_count_enable_write
998 COUNTER_COUNT_ENUM("error_noise", &quad8_error_noise_enum),
999 COUNTER_COUNT_ENUM_AVAILABLE("error_noise", &quad8_error_noise_enum),
1002 .read = quad8_count_preset_read,
1003 .write = quad8_count_preset_write
1006 .name = "preset_enable",
1007 .read = quad8_count_preset_enable_read,
1008 .write = quad8_count_preset_enable_write
1012 #define QUAD8_COUNT(_id, _cntname) { \
1014 .name = (_cntname), \
1015 .functions_list = quad8_count_functions_list, \
1016 .num_functions = ARRAY_SIZE(quad8_count_functions_list), \
1017 .synapses = quad8_count_synapses[(_id)], \
1018 .num_synapses = 2, \
1019 .ext = quad8_count_ext, \
1020 .num_ext = ARRAY_SIZE(quad8_count_ext) \
1023 static struct counter_count quad8_counts[] = {
1024 QUAD8_COUNT(0, "Channel 1 Count"),
1025 QUAD8_COUNT(1, "Channel 2 Count"),
1026 QUAD8_COUNT(2, "Channel 3 Count"),
1027 QUAD8_COUNT(3, "Channel 4 Count"),
1028 QUAD8_COUNT(4, "Channel 5 Count"),
1029 QUAD8_COUNT(5, "Channel 6 Count"),
1030 QUAD8_COUNT(6, "Channel 7 Count"),
1031 QUAD8_COUNT(7, "Channel 8 Count")
1034 static int quad8_probe(struct device *dev, unsigned int id)
1038 unsigned int base_offset;
1040 if (!devm_request_region(dev, base[id], QUAD8_EXTENT, dev_name(dev))) {
1041 dev_err(dev, "Unable to lock port addresses (0x%X-0x%X)\n",
1042 base[id], base[id] + QUAD8_EXTENT);
1046 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
1050 /* Initialize Counter device and driver data */
1051 priv->counter.name = dev_name(dev);
1052 priv->counter.parent = dev;
1053 priv->counter.ops = &quad8_ops;
1054 priv->counter.counts = quad8_counts;
1055 priv->counter.num_counts = ARRAY_SIZE(quad8_counts);
1056 priv->counter.signals = quad8_signals;
1057 priv->counter.num_signals = ARRAY_SIZE(quad8_signals);
1058 priv->counter.priv = priv;
1059 priv->base = base[id];
1061 /* Initialize mutex */
1062 mutex_init(&priv->lock);
1064 /* Reset all counters and disable interrupt function */
1065 outb(QUAD8_CHAN_OP_RESET_COUNTERS, base[id] + QUAD8_REG_CHAN_OP);
1066 /* Set initial configuration for all counters */
1067 for (i = 0; i < QUAD8_NUM_COUNTERS; i++) {
1068 base_offset = base[id] + 2 * i;
1069 /* Reset Byte Pointer */
1070 outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP, base_offset + 1);
1071 /* Reset filter clock factor */
1072 outb(0, base_offset);
1073 outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP | QUAD8_RLD_PRESET_PSC,
1075 /* Reset Byte Pointer */
1076 outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP, base_offset + 1);
1077 /* Reset Preset Register */
1078 for (j = 0; j < 3; j++)
1079 outb(0x00, base_offset);
1080 /* Reset Borrow, Carry, Compare, and Sign flags */
1081 outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_FLAGS, base_offset + 1);
1082 /* Reset Error flag */
1083 outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_E, base_offset + 1);
1084 /* Binary encoding; Normal count; non-quadrature mode */
1085 outb(QUAD8_CTR_CMR, base_offset + 1);
1086 /* Disable A and B inputs; preset on index; FLG1 as Carry */
1087 outb(QUAD8_CTR_IOR, base_offset + 1);
1088 /* Disable index function; negative index polarity */
1089 outb(QUAD8_CTR_IDR, base_offset + 1);
1091 /* Disable Differential Encoder Cable Status for all channels */
1092 outb(0xFF, base[id] + QUAD8_DIFF_ENCODER_CABLE_STATUS);
1093 /* Enable all counters */
1094 outb(QUAD8_CHAN_OP_ENABLE_COUNTERS, base[id] + QUAD8_REG_CHAN_OP);
1096 return devm_counter_register(dev, &priv->counter);
1099 static struct isa_driver quad8_driver = {
1100 .probe = quad8_probe,
1102 .name = "104-quad-8"
1106 module_isa_driver(quad8_driver, num_quad8);
1108 MODULE_AUTHOR("William Breathitt Gray <vilhelm.gray@gmail.com>");
1109 MODULE_DESCRIPTION("ACCES 104-QUAD-8 driver");
1110 MODULE_LICENSE("GPL v2");