1 menu "Generic Driver Options"
4 bool "Enable Driver Model"
6 This config option enables Driver Model. This brings in the core
7 support, including scanning of platform data on start-up. If
8 CONFIG_OF_CONTROL is enabled, the device tree will be scanned also
12 bool "Enable Driver Model for SPL"
15 Enable driver model in SPL. You will need to provide a
16 suitable malloc() implementation. If you are not using the
17 full malloc() enabled by CONFIG_SYS_SPL_MALLOC_START,
18 consider using CONFIG_SYS_MALLOC_SIMPLE. In that case you
19 must provide CONFIG_SPL_SYS_MALLOC_F_LEN to set the size.
20 In most cases driver model will only allocate a few uclasses
21 and devices in SPL, so 1KB should be enable. See
22 CONFIG_SPL_SYS_MALLOC_F_LEN for more details on how to enable it.
25 bool "Enable Driver Model for TPL"
28 Enable driver model in TPL. You will need to provide a
29 suitable malloc() implementation. If you are not using the
30 full malloc() enabled by CONFIG_SYS_SPL_MALLOC_START,
31 consider using CONFIG_SYS_MALLOC_SIMPLE. In that case you
32 must provide CONFIG_SPL_SYS_MALLOC_F_LEN to set the size.
33 In most cases driver model will only allocate a few uclasses
34 and devices in SPL, so 1KB should be enough. See
35 CONFIG_SPL_SYS_MALLOC_F_LEN for more details on how to enable it.
36 Disable this for very small implementations.
39 bool "Enable warnings in driver model"
43 Enable this to see warnings related to driver model.
45 Warnings may help with debugging, such as when expected devices do
46 not bind correctly. If the option is disabled, dm_warn() is compiled
47 out - it will do nothing when called.
50 bool "Enable warnings in driver model wuth SPL"
53 Enable this to see warnings related to driver model in SPL
55 The dm_warn() function can use up quite a bit of space for its
56 strings. By default this is disabled for SPL builds to save space.
58 Warnings may help with debugging, such as when expected devices do
59 not bind correctly. If the option is disabled, dm_warn() is compiled
60 out - it will do nothing when called.
63 bool "Enable debug messages in driver model core"
66 Say Y here if you want to compile in debug messages in DM core.
68 config DM_DEVICE_REMOVE
69 bool "Support device removal"
73 We can save some code space by dropping support for removing a
76 Note that this may have undesirable results in the USB subsystem as
77 it causes unplugged devices to linger around in the dm-tree, and it
78 causes USB host controllers to not be stopped when booting the OS.
80 config SPL_DM_DEVICE_REMOVE
81 bool "Support device removal in SPL"
85 We can save some code space by dropping support for removing a
86 device. This is not normally required in SPL, so by default this
87 option is disabled for SPL.
90 bool "Support stdio registration"
94 Normally serial drivers register with stdio so that they can be used
95 as normal output devices. In SPL we don't normally use stdio, so
96 we can omit this feature.
99 bool "Support numbered aliases in device tree"
103 Most boards will have a '/aliases' node containing the path to
104 numbered devices (e.g. serial0 = &serial0). This feature can be
105 disabled if it is not required.
107 config SPL_DM_SEQ_ALIAS
108 bool "Support numbered aliases in device tree in SPL"
112 Most boards will have a '/aliases' node containing the path to
113 numbered devices (e.g. serial0 = &serial0). This feature can be
114 disabled if it is not required, to save code space in SPL.
116 config SPL_DM_INLINE_OFNODE
117 bool "Inline some ofnode functions which are seldom used in SPL"
121 This applies to several ofnode functions (see ofnode.h) which are
122 seldom used. Inlining them can help reduce code size.
124 config TPL_DM_INLINE_OFNODE
125 bool "Inline some ofnode functions which are seldom used in TPL"
129 This applies to several ofnode functions (see ofnode.h) which are
130 seldom used. Inlining them can help reduce code size.
133 bool "Support per-device DMA constraints"
137 Enable this to extract per-device DMA constraints, only supported on
138 device-tree systems for now. This is needed in order translate
139 addresses on systems where different buses have different views of
140 the physical address space.
143 bool "Support register maps"
146 Hardware peripherals tend to have one or more sets of registers
147 which can be accessed to control the hardware. A register map
148 models this with a simple read/write interface. It can in principle
149 support any bus type (I2C, SPI) but so far this only supports
150 direct memory access.
153 bool "Support register maps in SPL"
156 Hardware peripherals tend to have one or more sets of registers
157 which can be accessed to control the hardware. A register map
158 models this with a simple read/write interface. It can in principle
159 support any bus type (I2C, SPI) but so far this only supports
160 direct memory access.
163 bool "Support register maps in TPL"
166 Hardware peripherals tend to have one or more sets of registers
167 which can be accessed to control the hardware. A register map
168 models this with a simple read/write interface. It can in principle
169 support any bus type (I2C, SPI) but so far this only supports
170 direct memory access.
173 bool "Support system controllers"
176 Many SoCs have a number of system controllers which are dealt with
177 as a group by a single driver. Some common functionality is provided
178 by this uclass, including accessing registers via regmap and
179 assigning a unique number to each.
182 bool "Support system controllers in SPL"
183 depends on SPL_REGMAP
185 Many SoCs have a number of system controllers which are dealt with
186 as a group by a single driver. Some common functionality is provided
187 by this uclass, including accessing registers via regmap and
188 assigning a unique number to each.
191 bool "Support system controllers in TPL"
192 depends on TPL_REGMAP
194 Many SoCs have a number of system controllers which are dealt with
195 as a group by a single driver. Some common functionality is provided
196 by this uclass, including accessing registers via regmap and
197 assigning a unique number to each.
200 bool "Managed device resources"
203 This option enables the Managed device resources core support.
204 Device resources managed by the devres framework are automatically
205 released whether initialization fails half-way or the device gets
208 If this option is disabled, devres functions fall back to
209 non-managed variants. For example, devres_alloc() to kzalloc(),
210 devm_kmalloc() to kmalloc(), etc.
213 bool "Managed device resources debugging functions"
216 If this option is enabled, devres debug messages are printed.
217 Also, a function is available to dump a list of device resources.
218 Select this if you are having a problem with devres or want to
219 debug resource management for a managed device.
221 If you are unsure about this, Say N here.
224 bool "Support simple-bus driver"
225 depends on DM && OF_CONTROL
228 Supports the 'simple-bus' driver, which is used on some systems.
230 config SPL_SIMPLE_BUS
231 bool "Support simple-bus driver in SPL"
232 depends on SPL_DM && SPL_OF_CONTROL
235 Supports the 'simple-bus' driver, which is used on some systems
239 bool "Support simple-pm-bus driver"
240 depends on DM && OF_CONTROL && CLK && POWER_DOMAIN
242 Supports the 'simple-pm-bus' driver, which is used for busses that
243 have power domains and/or clocks which need to be enabled before use.
246 bool "Translate addresses using fdt_translate_address"
247 depends on DM && OF_CONTROL
250 If this option is enabled, the reg property will be translated
251 using the fdt_translate_address() function. This is necessary
252 on some platforms (e.g. MVEBU) using complex "ranges"
253 properties in many nodes. As this translation is not handled
254 correctly in the default simple_bus_translate() function.
256 If this option is not enabled, simple_bus_translate() will be
257 used for the address translation. This function is faster and
258 smaller in size than fdt_translate_address().
260 config OF_TRANSLATE_ZERO_SIZE_CELLS
261 bool "Enable translation for zero size cells"
262 depends on OF_TRANSLATE
265 The routine used to translate an FDT address into a physical CPU
266 address was developed by IBM. It considers that crossing any level
267 with #size-cells = <0> makes translation impossible, even if it is
268 not the way it was specified.
269 Enabling this option makes translation possible even in the case
270 of crossing levels with #size-cells = <0>.
272 config SPL_OF_TRANSLATE
273 bool "Translate addresses using fdt_translate_address in SPL"
274 depends on SPL_DM && SPL_OF_CONTROL
277 If this option is enabled, the reg property will be translated
278 using the fdt_translate_address() function. This is necessary
279 on some platforms (e.g. MVEBU) using complex "ranges"
280 properties in many nodes. As this translation is not handled
281 correctly in the default simple_bus_translate() function.
283 If this option is not enabled, simple_bus_translate() will be
284 used for the address translation. This function is faster and
285 smaller in size than fdt_translate_address().
287 config TRANSLATION_OFFSET
288 bool "Platforms specific translation offset"
289 depends on DM && OF_CONTROL
291 Some platforms need a special address translation. Those
292 platforms (e.g. mvebu in SPL) can configure a translation
293 offset by enabling this option and setting the translation_offset
294 variable in the GD in their platform- / board-specific code.
298 depends on OF_TRANSLATE
300 Is this option is enabled then support for the ISA bus will
301 be included for addresses read from DT. This is something that
302 should be known to be required or not based upon the board
303 being targeted, and whether or not it makes use of an ISA bus.
305 The bus is matched based upon its node name equalling "isa". The
306 busses #address-cells should equal 2, with the first cell being
307 used to hold flags & flag 0x1 indicating that the address range
308 should be accessed using I/O port in/out accessors. The second
309 cell holds the offset into ISA bus address space. The #size-cells
310 property should equal 1, and of course holds the size of the
311 address range used by a device.
313 If this option is not enabled then support for the ISA bus is
314 not included and any such busses used in DT will be treated as
315 typical simple-bus compatible busses. This will lead to
316 mistranslation of device addresses, so ensure that this is
317 enabled if your board does include an ISA bus.
319 config DM_DEV_READ_INLINE
321 default y if !OF_LIVE
324 bool "Support ACPI table generation in driver model"
325 default y if SANDBOX || (GENERATE_ACPI_TABLE && !QEMU)
327 This option enables generation of ACPI tables using driver-model
328 devices. It adds a new operation struct to each driver, to support
329 things like generating device-specific tables and returning the ACPI
333 bool "Support ACPI table generation for Intel SoCs"
336 This option adds some functions used for programatic generation of
337 ACPI tables on Intel SoCs. This provides features for writing CPU
338 information such as P states and T stages. Also included is a way
339 to create a GNVS table and set it up.
342 bool "Include bounce buffer API"
344 Some peripherals support DMA from a subset of physically
345 addressable memory only. To support such peripherals, the
346 bounce buffer API uses a temporary buffer: it copies data
347 to/from DMA regions while managing cache operations.
349 A second possible use of bounce buffers is their ability to
350 provide aligned buffers for DMA operations.