drivers/clocksource/timer-ti-dm.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * linux/arch/arm/plat-omap/dmtimer.c
   4  *
   5  * OMAP Dual-Mode Timers
   6  *
   7  * Copyright (C) 2010 Texas Instruments Incorporated - https://www.ti.com/
   8  * Tarun Kanti DebBarma <tarun.kanti@ti.com>
   9  * Thara Gopinath <thara@ti.com>
  10  *
  11  * dmtimer adaptation to platform_driver.
  12  *
  13  * Copyright (C) 2005 Nokia Corporation
  14  * OMAP2 support by Juha Yrjola
  15  * API improvements and OMAP2 clock framework support by Timo Teras
  16  *
  17  * Copyright (C) 2009 Texas Instruments
  18  * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
  19  */
  20
  21 #include <linux/clk.h>
  22 #include <linux/clk-provider.h>
  23 #include <linux/cpu_pm.h>
  24 #include <linux/module.h>
  25 #include <linux/io.h>
  26 #include <linux/device.h>
  27 #include <linux/err.h>
  28 #include <linux/pm_runtime.h>
  29 #include <linux/of.h>
  30 #include <linux/of_device.h>
  31 #include <linux/platform_device.h>
  32 #include <linux/platform_data/dmtimer-omap.h>
  33
  34 #include <clocksource/timer-ti-dm.h>
  35
  36 /*
  37  * timer errata flags
  38  *
  39  * Errata i103/i767 impacts all OMAP3/4/5 devices including AM33xx. This
  40  * errata prevents us from using posted mode on these devices, unless the
  41  * timer counter register is never read. For more details please refer to
  42  * the OMAP3/4/5 errata documents.
  43  */
  44 #define OMAP_TIMER_ERRATA_I103_I767                     0x80000000
  45
  46 /* posted mode types */
  47 #define OMAP_TIMER_NONPOSTED                    0x00
  48 #define OMAP_TIMER_POSTED                       0x01
  49
  50 /* register offsets with the write pending bit encoded */
  51 #define WPSHIFT                                 16
  52
  53 #define OMAP_TIMER_WAKEUP_EN_REG                (_OMAP_TIMER_WAKEUP_EN_OFFSET \
  54                                                         | (WP_NONE << WPSHIFT))
  55
  56 #define OMAP_TIMER_CTRL_REG                     (_OMAP_TIMER_CTRL_OFFSET \
  57                                                         | (WP_TCLR << WPSHIFT))
  58
  59 #define OMAP_TIMER_COUNTER_REG                  (_OMAP_TIMER_COUNTER_OFFSET \
  60                                                         | (WP_TCRR << WPSHIFT))
  61
  62 #define OMAP_TIMER_LOAD_REG                     (_OMAP_TIMER_LOAD_OFFSET \
  63                                                         | (WP_TLDR << WPSHIFT))
  64
  65 #define OMAP_TIMER_TRIGGER_REG                  (_OMAP_TIMER_TRIGGER_OFFSET \
  66                                                         | (WP_TTGR << WPSHIFT))
  67
  68 #define OMAP_TIMER_WRITE_PEND_REG               (_OMAP_TIMER_WRITE_PEND_OFFSET \
  69                                                         | (WP_NONE << WPSHIFT))
  70
  71 #define OMAP_TIMER_MATCH_REG                    (_OMAP_TIMER_MATCH_OFFSET \
  72                                                         | (WP_TMAR << WPSHIFT))
  73
  74 #define OMAP_TIMER_CAPTURE_REG                  (_OMAP_TIMER_CAPTURE_OFFSET \
  75                                                         | (WP_NONE << WPSHIFT))
  76
  77 #define OMAP_TIMER_IF_CTRL_REG                  (_OMAP_TIMER_IF_CTRL_OFFSET \
  78                                                         | (WP_NONE << WPSHIFT))
  79
  80 #define OMAP_TIMER_CAPTURE2_REG                 (_OMAP_TIMER_CAPTURE2_OFFSET \
  81                                                         | (WP_NONE << WPSHIFT))
  82
  83 #define OMAP_TIMER_TICK_POS_REG                 (_OMAP_TIMER_TICK_POS_OFFSET \
  84                                                         | (WP_TPIR << WPSHIFT))
  85
  86 #define OMAP_TIMER_TICK_NEG_REG                 (_OMAP_TIMER_TICK_NEG_OFFSET \
  87                                                         | (WP_TNIR << WPSHIFT))
  88
  89 #define OMAP_TIMER_TICK_COUNT_REG               (_OMAP_TIMER_TICK_COUNT_OFFSET \
  90                                                         | (WP_TCVR << WPSHIFT))
  91
  92 #define OMAP_TIMER_TICK_INT_MASK_SET_REG                                \
  93                 (_OMAP_TIMER_TICK_INT_MASK_SET_OFFSET | (WP_TOCR << WPSHIFT))
  94
  95 #define OMAP_TIMER_TICK_INT_MASK_COUNT_REG                              \
  96                 (_OMAP_TIMER_TICK_INT_MASK_COUNT_OFFSET | (WP_TOWR << WPSHIFT))
  97
  98 struct timer_regs {
  99         u32 ocp_cfg;
 100         u32 tidr;
 101         u32 tier;
 102         u32 twer;
 103         u32 tclr;
 104         u32 tcrr;
 105         u32 tldr;
 106         u32 ttrg;
 107         u32 twps;
 108         u32 tmar;
 109         u32 tcar1;
 110         u32 tsicr;
 111         u32 tcar2;
 112         u32 tpir;
 113         u32 tnir;
 114         u32 tcvr;
 115         u32 tocr;
 116         u32 towr;
 117 };
 118
 119 struct dmtimer {
 120         struct omap_dm_timer cookie;
 121         int id;
 122         int irq;
 123         struct clk *fclk;
 124
 125         void __iomem    *io_base;
 126         int             irq_stat;       /* TISR/IRQSTATUS interrupt status */
 127         int             irq_ena;        /* irq enable */
 128         int             irq_dis;        /* irq disable, only on v2 ip */
 129         void __iomem    *pend;          /* write pending */
 130         void __iomem    *func_base;     /* function register base */
 131
 132         atomic_t enabled;
 133         unsigned long rate;
 134         unsigned reserved:1;
 135         unsigned posted:1;
 136         unsigned omap1:1;
 137         struct timer_regs context;
 138         int revision;
 139         u32 capability;
 140         u32 errata;
 141         struct platform_device *pdev;
 142         struct list_head node;
 143         struct notifier_block nb;
 144 };
 145
 146 static u32 omap_reserved_systimers;
 147 static LIST_HEAD(omap_timer_list);
 148 static DEFINE_SPINLOCK(dm_timer_lock);
 149
 150 enum {
 151         REQUEST_ANY = 0,
 152         REQUEST_BY_ID,
 153         REQUEST_BY_CAP,
 154         REQUEST_BY_NODE,
 155 };
 156
 157 /**
 158  * dmtimer_read - read timer registers in posted and non-posted mode
 159  * @timer:      timer pointer over which read operation to perform
 160  * @reg:        lowest byte holds the register offset
 161  *
 162  * The posted mode bit is encoded in reg. Note that in posted mode, write
 163  * pending bit must be checked. Otherwise a read of a non completed write
 164  * will produce an error.
 165  */
 166 static inline u32 dmtimer_read(struct dmtimer *timer, u32 reg)
 167 {
 168         u16 wp, offset;
 169
 170         wp = reg >> WPSHIFT;
 171         offset = reg & 0xff;
 172
 173         /* Wait for a possible write pending bit in posted mode */
 174         if (wp && timer->posted)
 175                 while (readl_relaxed(timer->pend) & wp)
 176                         cpu_relax();
 177
 178         return readl_relaxed(timer->func_base + offset);
 179 }
 180
 181 /**
 182  * dmtimer_write - write timer registers in posted and non-posted mode
 183  * @timer:      timer pointer over which write operation is to perform
 184  * @reg:        lowest byte holds the register offset
 185  * @value:      data to write into the register
 186  *
 187  * The posted mode bit is encoded in reg. Note that in posted mode, the write
 188  * pending bit must be checked. Otherwise a write on a register which has a
 189  * pending write will be lost.
 190  */
 191 static inline void dmtimer_write(struct dmtimer *timer, u32 reg, u32 val)
 192 {
 193         u16 wp, offset;
 194
 195         wp = reg >> WPSHIFT;
 196         offset = reg & 0xff;
 197
 198         /* Wait for a possible write pending bit in posted mode */
 199         if (wp && timer->posted)
 200                 while (readl_relaxed(timer->pend) & wp)
 201                         cpu_relax();
 202
 203         writel_relaxed(val, timer->func_base + offset);
 204 }
 205
 206 static inline void __omap_dm_timer_init_regs(struct dmtimer *timer)
 207 {
 208         u32 tidr;
 209
 210         /* Assume v1 ip if bits [31:16] are zero */
 211         tidr = readl_relaxed(timer->io_base);
 212         if (!(tidr >> 16)) {
 213                 timer->revision = 1;
 214                 timer->irq_stat = OMAP_TIMER_V1_STAT_OFFSET;
 215                 timer->irq_ena = OMAP_TIMER_V1_INT_EN_OFFSET;
 216                 timer->irq_dis = OMAP_TIMER_V1_INT_EN_OFFSET;
 217                 timer->pend = timer->io_base + _OMAP_TIMER_WRITE_PEND_OFFSET;
 218                 timer->func_base = timer->io_base;
 219         } else {
 220                 timer->revision = 2;
 221                 timer->irq_stat = OMAP_TIMER_V2_IRQSTATUS - OMAP_TIMER_V2_FUNC_OFFSET;
 222                 timer->irq_ena = OMAP_TIMER_V2_IRQENABLE_SET - OMAP_TIMER_V2_FUNC_OFFSET;
 223                 timer->irq_dis = OMAP_TIMER_V2_IRQENABLE_CLR - OMAP_TIMER_V2_FUNC_OFFSET;
 224                 timer->pend = timer->io_base +
 225                         _OMAP_TIMER_WRITE_PEND_OFFSET +
 226                                 OMAP_TIMER_V2_FUNC_OFFSET;
 227                 timer->func_base = timer->io_base + OMAP_TIMER_V2_FUNC_OFFSET;
 228         }
 229 }
 230
 231 /*
 232  * __omap_dm_timer_enable_posted - enables write posted mode
 233  * @timer:      pointer to timer instance handle
 234  *
 235  * Enables the write posted mode for the timer. When posted mode is enabled
 236  * writes to certain timer registers are immediately acknowledged by the
 237  * internal bus and hence prevents stalling the CPU waiting for the write to
 238  * complete. Enabling this feature can improve performance for writing to the
 239  * timer registers.
 240  */
 241 static inline void __omap_dm_timer_enable_posted(struct dmtimer *timer)
 242 {
 243         if (timer->posted)
 244                 return;
 245
 246         if (timer->errata & OMAP_TIMER_ERRATA_I103_I767) {
 247                 timer->posted = OMAP_TIMER_NONPOSTED;
 248                 dmtimer_write(timer, OMAP_TIMER_IF_CTRL_REG, 0);
 249                 return;
 250         }
 251
 252         dmtimer_write(timer, OMAP_TIMER_IF_CTRL_REG, OMAP_TIMER_CTRL_POSTED);
 253         timer->context.tsicr = OMAP_TIMER_CTRL_POSTED;
 254         timer->posted = OMAP_TIMER_POSTED;
 255 }
 256
 257 static inline void __omap_dm_timer_stop(struct dmtimer *timer,
 258                                         unsigned long rate)
 259 {
 260         u32 l;
 261
 262         l = dmtimer_read(timer, OMAP_TIMER_CTRL_REG);
 263         if (l & OMAP_TIMER_CTRL_ST) {
 264                 l &= ~0x1;
 265                 dmtimer_write(timer, OMAP_TIMER_CTRL_REG, l);
 266 #ifdef CONFIG_ARCH_OMAP2PLUS
 267                 /* Readback to make sure write has completed */
 268                 dmtimer_read(timer, OMAP_TIMER_CTRL_REG);
 269                 /*
 270                  * Wait for functional clock period x 3.5 to make sure that
 271                  * timer is stopped
 272                  */
 273                 udelay(3500000 / rate + 1);
 274 #endif
 275         }
 276
 277         /* Ack possibly pending interrupt */
 278         dmtimer_write(timer, timer->irq_stat, OMAP_TIMER_INT_OVERFLOW);
 279 }
 280
 281 static inline void __omap_dm_timer_int_enable(struct dmtimer *timer,
 282                                               unsigned int value)
 283 {
 284         dmtimer_write(timer, timer->irq_ena, value);
 285         dmtimer_write(timer, OMAP_TIMER_WAKEUP_EN_REG, value);
 286 }
 287
 288 static inline unsigned int
 289 __omap_dm_timer_read_counter(struct dmtimer *timer)
 290 {
 291         return dmtimer_read(timer, OMAP_TIMER_COUNTER_REG);
 292 }
 293
 294 static inline void __omap_dm_timer_write_status(struct dmtimer *timer,
 295                                                 unsigned int value)
 296 {
 297         dmtimer_write(timer, timer->irq_stat, value);
 298 }
 299
 300 static void omap_timer_restore_context(struct dmtimer *timer)
 301 {
 302         dmtimer_write(timer, OMAP_TIMER_OCP_CFG_OFFSET, timer->context.ocp_cfg);
 303
 304         dmtimer_write(timer, OMAP_TIMER_WAKEUP_EN_REG, timer->context.twer);
 305         dmtimer_write(timer, OMAP_TIMER_COUNTER_REG, timer->context.tcrr);
 306         dmtimer_write(timer, OMAP_TIMER_LOAD_REG, timer->context.tldr);
 307         dmtimer_write(timer, OMAP_TIMER_MATCH_REG, timer->context.tmar);
 308         dmtimer_write(timer, OMAP_TIMER_IF_CTRL_REG, timer->context.tsicr);
 309         dmtimer_write(timer, timer->irq_ena, timer->context.tier);
 310         dmtimer_write(timer, OMAP_TIMER_CTRL_REG, timer->context.tclr);
 311 }
 312
 313 static void omap_timer_save_context(struct dmtimer *timer)
 314 {
 315         timer->context.ocp_cfg = dmtimer_read(timer, OMAP_TIMER_OCP_CFG_OFFSET);
 316
 317         timer->context.tclr = dmtimer_read(timer, OMAP_TIMER_CTRL_REG);
 318         timer->context.twer = dmtimer_read(timer, OMAP_TIMER_WAKEUP_EN_REG);
 319         timer->context.tldr = dmtimer_read(timer, OMAP_TIMER_LOAD_REG);
 320         timer->context.tmar = dmtimer_read(timer, OMAP_TIMER_MATCH_REG);
 321         timer->context.tier = dmtimer_read(timer, timer->irq_ena);
 322         timer->context.tsicr = dmtimer_read(timer, OMAP_TIMER_IF_CTRL_REG);
 323 }
 324
 325 static int omap_timer_context_notifier(struct notifier_block *nb,
 326                                        unsigned long cmd, void *v)
 327 {
 328         struct dmtimer *timer;
 329
 330         timer = container_of(nb, struct dmtimer, nb);
 331
 332         switch (cmd) {
 333         case CPU_CLUSTER_PM_ENTER:
 334                 if ((timer->capability & OMAP_TIMER_ALWON) ||
 335                     !atomic_read(&timer->enabled))
 336                         break;
 337                 omap_timer_save_context(timer);
 338                 break;
 339         case CPU_CLUSTER_PM_ENTER_FAILED:       /* No need to restore context */
 340                 break;
 341         case CPU_CLUSTER_PM_EXIT:
 342                 if ((timer->capability & OMAP_TIMER_ALWON) ||
 343                     !atomic_read(&timer->enabled))
 344                         break;
 345                 omap_timer_restore_context(timer);
 346                 break;
 347         }
 348
 349         return NOTIFY_OK;
 350 }
 351
 352 static int omap_dm_timer_reset(struct dmtimer *timer)
 353 {
 354         u32 l, timeout = 100000;
 355
 356         if (timer->revision != 1)
 357                 return -EINVAL;
 358
 359         dmtimer_write(timer, OMAP_TIMER_IF_CTRL_REG, 0x06);
 360
 361         do {
 362                 l = dmtimer_read(timer, OMAP_TIMER_V1_SYS_STAT_OFFSET);
 363         } while (!l && timeout--);
 364
 365         if (!timeout) {
 366                 dev_err(&timer->pdev->dev, "Timer failed to reset\n");
 367                 return -ETIMEDOUT;
 368         }
 369
 370         /* Configure timer for smart-idle mode */
 371         l = dmtimer_read(timer, OMAP_TIMER_OCP_CFG_OFFSET);
 372         l |= 0x2 << 0x3;
 373         dmtimer_write(timer, OMAP_TIMER_OCP_CFG_OFFSET, l);
 374
 375         timer->posted = 0;
 376
 377         return 0;
 378 }
 379
 380 /*
 381  * Functions exposed to PWM and remoteproc drivers via platform_data.
 382  * Do not use these in the driver, these will get deprecated and will
 383  * will be replaced by Linux generic framework functions such as
 384  * chained interrupts and clock framework.
 385  */
 386 static struct dmtimer *to_dmtimer(struct omap_dm_timer *cookie)
 387 {
 388         if (!cookie)
 389                 return NULL;
 390
 391         return container_of(cookie, struct dmtimer, cookie);
 392 }
 393
 394 static int omap_dm_timer_set_source(struct omap_dm_timer *cookie, int source)
 395 {
 396         int ret;
 397         const char *parent_name;
 398         struct clk *parent;
 399         struct dmtimer_platform_data *pdata;
 400         struct dmtimer *timer;
 401
 402         timer = to_dmtimer(cookie);
 403         if (unlikely(!timer) || IS_ERR(timer->fclk))
 404                 return -EINVAL;
 405
 406         switch (source) {
 407         case OMAP_TIMER_SRC_SYS_CLK:
 408                 parent_name = "timer_sys_ck";
 409                 break;
 410         case OMAP_TIMER_SRC_32_KHZ:
 411                 parent_name = "timer_32k_ck";
 412                 break;
 413         case OMAP_TIMER_SRC_EXT_CLK:
 414                 parent_name = "timer_ext_ck";
 415                 break;
 416         default:
 417                 return -EINVAL;
 418         }
 419
 420         pdata = timer->pdev->dev.platform_data;
 421
 422         /*
 423          * FIXME: Used for OMAP1 devices only because they do not currently
 424          * use the clock framework to set the parent clock. To be removed
 425          * once OMAP1 migrated to using clock framework for dmtimers
 426          */
 427         if (timer->omap1 && pdata && pdata->set_timer_src)
 428                 return pdata->set_timer_src(timer->pdev, source);
 429
 430 #if defined(CONFIG_COMMON_CLK)
 431         /* Check if the clock has configurable parents */
 432         if (clk_hw_get_num_parents(__clk_get_hw(timer->fclk)) < 2)
 433                 return 0;
 434 #endif
 435
 436         parent = clk_get(&timer->pdev->dev, parent_name);
 437         if (IS_ERR(parent)) {
 438                 pr_err("%s: %s not found\n", __func__, parent_name);
 439                 return -EINVAL;
 440         }
 441
 442         ret = clk_set_parent(timer->fclk, parent);
 443         if (ret < 0)
 444                 pr_err("%s: failed to set %s as parent\n", __func__,
 445                         parent_name);
 446
 447         clk_put(parent);
 448
 449         return ret;
 450 }
 451
 452 static void omap_dm_timer_enable(struct omap_dm_timer *cookie)
 453 {
 454         struct dmtimer *timer = to_dmtimer(cookie);
 455         struct device *dev = &timer->pdev->dev;
 456         int rc;
 457
 458         rc = pm_runtime_resume_and_get(dev);
 459         if (rc)
 460                 dev_err(dev, "could not enable timer\n");
 461 }
 462
 463 static void omap_dm_timer_disable(struct omap_dm_timer *cookie)
 464 {
 465         struct dmtimer *timer = to_dmtimer(cookie);
 466         struct device *dev = &timer->pdev->dev;
 467
 468         pm_runtime_put_sync(dev);
 469 }
 470
 471 static int omap_dm_timer_prepare(struct dmtimer *timer)
 472 {
 473         struct device *dev = &timer->pdev->dev;
 474         int rc;
 475
 476         rc = pm_runtime_resume_and_get(dev);
 477         if (rc)
 478                 return rc;
 479
 480         if (timer->capability & OMAP_TIMER_NEEDS_RESET) {
 481                 rc = omap_dm_timer_reset(timer);
 482                 if (rc) {
 483                         pm_runtime_put_sync(dev);
 484                         return rc;
 485                 }
 486         }
 487
 488         __omap_dm_timer_enable_posted(timer);
 489         pm_runtime_put_sync(dev);
 490
 491         return 0;
 492 }
 493
 494 static inline u32 omap_dm_timer_reserved_systimer(int id)
 495 {
 496         return (omap_reserved_systimers & (1 << (id - 1))) ? 1 : 0;
 497 }
 498
 499 static struct dmtimer *_omap_dm_timer_request(int req_type, void *data)
 500 {
 501         struct dmtimer *timer = NULL, *t;
 502         struct device_node *np = NULL;
 503         unsigned long flags;
 504         u32 cap = 0;
 505         int id = 0;
 506
 507         switch (req_type) {
 508         case REQUEST_BY_ID:
 509                 id = *(int *)data;
 510                 break;
 511         case REQUEST_BY_CAP:
 512                 cap = *(u32 *)data;
 513                 break;
 514         case REQUEST_BY_NODE:
 515                 np = (struct device_node *)data;
 516                 break;
 517         default:
 518                 /* REQUEST_ANY */
 519                 break;
 520         }
 521
 522         spin_lock_irqsave(&dm_timer_lock, flags);
 523         list_for_each_entry(t, &omap_timer_list, node) {
 524                 if (t->reserved)
 525                         continue;
 526
 527                 switch (req_type) {
 528                 case REQUEST_BY_ID:
 529                         if (id == t->pdev->id) {
 530                                 timer = t;
 531                                 timer->reserved = 1;
 532                                 goto found;
 533                         }
 534                         break;
 535                 case REQUEST_BY_CAP:
 536                         if (cap == (t->capability & cap)) {
 537                                 /*
 538                                  * If timer is not NULL, we have already found
 539                                  * one timer. But it was not an exact match
 540                                  * because it had more capabilities than what
 541                                  * was required. Therefore, unreserve the last
 542                                  * timer found and see if this one is a better
 543                                  * match.
 544                                  */
 545                                 if (timer)
 546                                         timer->reserved = 0;
 547                                 timer = t;
 548                                 timer->reserved = 1;
 549
 550                                 /* Exit loop early if we find an exact match */
 551                                 if (t->capability == cap)
 552                                         goto found;
 553                         }
 554                         break;
 555                 case REQUEST_BY_NODE:
 556                         if (np == t->pdev->dev.of_node) {
 557                                 timer = t;
 558                                 timer->reserved = 1;
 559                                 goto found;
 560                         }
 561                         break;
 562                 default:
 563                         /* REQUEST_ANY */
 564                         timer = t;
 565                         timer->reserved = 1;
 566                         goto found;
 567                 }
 568         }
 569 found:
 570         spin_unlock_irqrestore(&dm_timer_lock, flags);
 571
 572         if (timer && omap_dm_timer_prepare(timer)) {
 573                 timer->reserved = 0;
 574                 timer = NULL;
 575         }
 576
 577         if (!timer)
 578                 pr_debug("%s: timer request failed!\n", __func__);
 579
 580         return timer;
 581 }
 582
 583 static struct omap_dm_timer *omap_dm_timer_request(void)
 584 {
 585         struct dmtimer *timer;
 586
 587         timer = _omap_dm_timer_request(REQUEST_ANY, NULL);
 588         if (!timer)
 589                 return NULL;
 590
 591         return &timer->cookie;
 592 }
 593
 594 static struct omap_dm_timer *omap_dm_timer_request_specific(int id)
 595 {
 596         struct dmtimer *timer;
 597
 598         /* Requesting timer by ID is not supported when device tree is used */
 599         if (of_have_populated_dt()) {
 600                 pr_warn("%s: Please use omap_dm_timer_request_by_node()\n",
 601                         __func__);
 602                 return NULL;
 603         }
 604
 605         timer = _omap_dm_timer_request(REQUEST_BY_ID, &id);
 606         if (!timer)
 607                 return NULL;
 608
 609         return &timer->cookie;
 610 }
 611
 612 /**
 613  * omap_dm_timer_request_by_node - Request a timer by device-tree node
 614  * @np:         Pointer to device-tree timer node
 615  *
 616  * Request a timer based upon a device node pointer. Returns pointer to
 617  * timer handle on success and a NULL pointer on failure.
 618  */
 619 static struct omap_dm_timer *omap_dm_timer_request_by_node(struct device_node *np)
 620 {
 621         struct dmtimer *timer;
 622
 623         if (!np)
 624                 return NULL;
 625
 626         timer = _omap_dm_timer_request(REQUEST_BY_NODE, np);
 627         if (!timer)
 628                 return NULL;
 629
 630         return &timer->cookie;
 631 }
 632
 633 static int omap_dm_timer_free(struct omap_dm_timer *cookie)
 634 {
 635         struct dmtimer *timer;
 636         struct device *dev;
 637         int rc;
 638
 639         timer = to_dmtimer(cookie);
 640         if (unlikely(!timer))
 641                 return -EINVAL;
 642
 643         WARN_ON(!timer->reserved);
 644         timer->reserved = 0;
 645
 646         dev = &timer->pdev->dev;
 647         rc = pm_runtime_resume_and_get(dev);
 648         if (rc)
 649                 return rc;
 650
 651         /* Clear timer configuration */
 652         dmtimer_write(timer, OMAP_TIMER_CTRL_REG, 0);
 653
 654         pm_runtime_put_sync(dev);
 655
 656         return 0;
 657 }
 658
 659 static int omap_dm_timer_get_irq(struct omap_dm_timer *cookie)
 660 {
 661         struct dmtimer *timer = to_dmtimer(cookie);
 662         if (timer)
 663                 return timer->irq;
 664         return -EINVAL;
 665 }
 666
 667 #if defined(CONFIG_ARCH_OMAP1)
 668 #include <linux/soc/ti/omap1-io.h>
 669
 670 static struct clk *omap_dm_timer_get_fclk(struct omap_dm_timer *cookie)
 671 {
 672         return NULL;
 673 }
 674
 675 /**
 676  * omap_dm_timer_modify_idlect_mask - Check if any running timers use ARMXOR
 677  * @inputmask: current value of idlect mask
 678  */
 679 __u32 omap_dm_timer_modify_idlect_mask(__u32 inputmask)
 680 {
 681         int i = 0;
 682         struct dmtimer *timer = NULL;
 683         unsigned long flags;
 684
 685         /* If ARMXOR cannot be idled this function call is unnecessary */
 686         if (!(inputmask & (1 << 1)))
 687                 return inputmask;
 688
 689         /* If any active timer is using ARMXOR return modified mask */
 690         spin_lock_irqsave(&dm_timer_lock, flags);
 691         list_for_each_entry(timer, &omap_timer_list, node) {
 692                 u32 l;
 693
 694                 l = dmtimer_read(timer, OMAP_TIMER_CTRL_REG);
 695                 if (l & OMAP_TIMER_CTRL_ST) {
 696                         if (((omap_readl(MOD_CONF_CTRL_1) >> (i * 2)) & 0x03) == 0)
 697                                 inputmask &= ~(1 << 1);
 698                         else
 699                                 inputmask &= ~(1 << 2);
 700                 }
 701                 i++;
 702         }
 703         spin_unlock_irqrestore(&dm_timer_lock, flags);
 704
 705         return inputmask;
 706 }
 707
 708 #else
 709
 710 static struct clk *omap_dm_timer_get_fclk(struct omap_dm_timer *cookie)
 711 {
 712         struct dmtimer *timer = to_dmtimer(cookie);
 713
 714         if (timer && !IS_ERR(timer->fclk))
 715                 return timer->fclk;
 716         return NULL;
 717 }
 718
 719 __u32 omap_dm_timer_modify_idlect_mask(__u32 inputmask)
 720 {
 721         BUG();
 722
 723         return 0;
 724 }
 725
 726 #endif
 727
 728 static int omap_dm_timer_start(struct omap_dm_timer *cookie)
 729 {
 730         struct dmtimer *timer;
 731         struct device *dev;
 732         int rc;
 733         u32 l;
 734
 735         timer = to_dmtimer(cookie);
 736         if (unlikely(!timer))
 737                 return -EINVAL;
 738
 739         dev = &timer->pdev->dev;
 740
 741         rc = pm_runtime_resume_and_get(dev);
 742         if (rc)
 743                 return rc;
 744
 745         l = dmtimer_read(timer, OMAP_TIMER_CTRL_REG);
 746         if (!(l & OMAP_TIMER_CTRL_ST)) {
 747                 l |= OMAP_TIMER_CTRL_ST;
 748                 dmtimer_write(timer, OMAP_TIMER_CTRL_REG, l);
 749         }
 750
 751         return 0;
 752 }
 753
 754 static int omap_dm_timer_stop(struct omap_dm_timer *cookie)
 755 {
 756         struct dmtimer *timer;
 757         struct device *dev;
 758         unsigned long rate = 0;
 759
 760         timer = to_dmtimer(cookie);
 761         if (unlikely(!timer))
 762                 return -EINVAL;
 763
 764         dev = &timer->pdev->dev;
 765
 766         if (!timer->omap1)
 767                 rate = clk_get_rate(timer->fclk);
 768
 769         __omap_dm_timer_stop(timer, rate);
 770
 771         pm_runtime_put_sync(dev);
 772
 773         return 0;
 774 }
 775
 776 static int omap_dm_timer_set_load(struct omap_dm_timer *cookie,
 777                                   unsigned int load)
 778 {
 779         struct dmtimer *timer;
 780         struct device *dev;
 781         int rc;
 782
 783         timer = to_dmtimer(cookie);
 784         if (unlikely(!timer))
 785                 return -EINVAL;
 786
 787         dev = &timer->pdev->dev;
 788         rc = pm_runtime_resume_and_get(dev);
 789         if (rc)
 790                 return rc;
 791
 792         dmtimer_write(timer, OMAP_TIMER_LOAD_REG, load);
 793
 794         pm_runtime_put_sync(dev);
 795
 796         return 0;
 797 }
 798
 799 static int omap_dm_timer_set_match(struct omap_dm_timer *cookie, int enable,
 800                                    unsigned int match)
 801 {
 802         struct dmtimer *timer;
 803         struct device *dev;
 804         int rc;
 805         u32 l;
 806
 807         timer = to_dmtimer(cookie);
 808         if (unlikely(!timer))
 809                 return -EINVAL;
 810
 811         dev = &timer->pdev->dev;
 812         rc = pm_runtime_resume_and_get(dev);
 813         if (rc)
 814                 return rc;
 815
 816         l = dmtimer_read(timer, OMAP_TIMER_CTRL_REG);
 817         if (enable)
 818                 l |= OMAP_TIMER_CTRL_CE;
 819         else
 820                 l &= ~OMAP_TIMER_CTRL_CE;
 821         dmtimer_write(timer, OMAP_TIMER_MATCH_REG, match);
 822         dmtimer_write(timer, OMAP_TIMER_CTRL_REG, l);
 823
 824         pm_runtime_put_sync(dev);
 825
 826         return 0;
 827 }
 828
 829 static int omap_dm_timer_set_pwm(struct omap_dm_timer *cookie, int def_on,
 830                                  int toggle, int trigger, int autoreload)
 831 {
 832         struct dmtimer *timer;
 833         struct device *dev;
 834         int rc;
 835         u32 l;
 836
 837         timer = to_dmtimer(cookie);
 838         if (unlikely(!timer))
 839                 return -EINVAL;
 840
 841         dev = &timer->pdev->dev;
 842         rc = pm_runtime_resume_and_get(dev);
 843         if (rc)
 844                 return rc;
 845
 846         l = dmtimer_read(timer, OMAP_TIMER_CTRL_REG);
 847         l &= ~(OMAP_TIMER_CTRL_GPOCFG | OMAP_TIMER_CTRL_SCPWM |
 848                OMAP_TIMER_CTRL_PT | (0x03 << 10) | OMAP_TIMER_CTRL_AR);
 849         if (def_on)
 850                 l |= OMAP_TIMER_CTRL_SCPWM;
 851         if (toggle)
 852                 l |= OMAP_TIMER_CTRL_PT;
 853         l |= trigger << 10;
 854         if (autoreload)
 855                 l |= OMAP_TIMER_CTRL_AR;
 856         dmtimer_write(timer, OMAP_TIMER_CTRL_REG, l);
 857
 858         pm_runtime_put_sync(dev);
 859
 860         return 0;
 861 }
 862
 863 static int omap_dm_timer_get_pwm_status(struct omap_dm_timer *cookie)
 864 {
 865         struct dmtimer *timer;
 866         struct device *dev;
 867         int rc;
 868         u32 l;
 869
 870         timer = to_dmtimer(cookie);
 871         if (unlikely(!timer))
 872                 return -EINVAL;
 873
 874         dev = &timer->pdev->dev;
 875         rc = pm_runtime_resume_and_get(dev);
 876         if (rc)
 877                 return rc;
 878
 879         l = dmtimer_read(timer, OMAP_TIMER_CTRL_REG);
 880
 881         pm_runtime_put_sync(dev);
 882
 883         return l;
 884 }
 885
 886 static int omap_dm_timer_set_prescaler(struct omap_dm_timer *cookie,
 887                                        int prescaler)
 888 {
 889         struct dmtimer *timer;
 890         struct device *dev;
 891         int rc;
 892         u32 l;
 893
 894         timer = to_dmtimer(cookie);
 895         if (unlikely(!timer) || prescaler < -1 || prescaler > 7)
 896                 return -EINVAL;
 897
 898         dev = &timer->pdev->dev;
 899         rc = pm_runtime_resume_and_get(dev);
 900         if (rc)
 901                 return rc;
 902
 903         l = dmtimer_read(timer, OMAP_TIMER_CTRL_REG);
 904         l &= ~(OMAP_TIMER_CTRL_PRE | (0x07 << 2));
 905         if (prescaler >= 0) {
 906                 l |= OMAP_TIMER_CTRL_PRE;
 907                 l |= prescaler << 2;
 908         }
 909         dmtimer_write(timer, OMAP_TIMER_CTRL_REG, l);
 910
 911         pm_runtime_put_sync(dev);
 912
 913         return 0;
 914 }
 915
 916 static int omap_dm_timer_set_int_enable(struct omap_dm_timer *cookie,
 917                                         unsigned int value)
 918 {
 919         struct dmtimer *timer;
 920         struct device *dev;
 921         int rc;
 922
 923         timer = to_dmtimer(cookie);
 924         if (unlikely(!timer))
 925                 return -EINVAL;
 926
 927         dev = &timer->pdev->dev;
 928         rc = pm_runtime_resume_and_get(dev);
 929         if (rc)
 930                 return rc;
 931
 932         __omap_dm_timer_int_enable(timer, value);
 933
 934         pm_runtime_put_sync(dev);
 935
 936         return 0;
 937 }
 938
 939 /**
 940  * omap_dm_timer_set_int_disable - disable timer interrupts
 941  * @timer:      pointer to timer handle
 942  * @mask:       bit mask of interrupts to be disabled
 943  *
 944  * Disables the specified timer interrupts for a timer.
 945  */
 946 static int omap_dm_timer_set_int_disable(struct omap_dm_timer *cookie, u32 mask)
 947 {
 948         struct dmtimer *timer;
 949         struct device *dev;
 950         u32 l = mask;
 951         int rc;
 952
 953         timer = to_dmtimer(cookie);
 954         if (unlikely(!timer))
 955                 return -EINVAL;
 956
 957         dev = &timer->pdev->dev;
 958         rc = pm_runtime_resume_and_get(dev);
 959         if (rc)
 960                 return rc;
 961
 962         if (timer->revision == 1)
 963                 l = dmtimer_read(timer, timer->irq_ena) & ~mask;
 964
 965         dmtimer_write(timer, timer->irq_dis, l);
 966         l = dmtimer_read(timer, OMAP_TIMER_WAKEUP_EN_REG) & ~mask;
 967         dmtimer_write(timer, OMAP_TIMER_WAKEUP_EN_REG, l);
 968
 969         pm_runtime_put_sync(dev);
 970
 971         return 0;
 972 }
 973
 974 static unsigned int omap_dm_timer_read_status(struct omap_dm_timer *cookie)
 975 {
 976         struct dmtimer *timer;
 977         unsigned int l;
 978
 979         timer = to_dmtimer(cookie);
 980         if (unlikely(!timer || !atomic_read(&timer->enabled))) {
 981                 pr_err("%s: timer not available or enabled.\n", __func__);
 982                 return 0;
 983         }
 984
 985         l = dmtimer_read(timer, timer->irq_stat);
 986
 987         return l;
 988 }
 989
 990 static int omap_dm_timer_write_status(struct omap_dm_timer *cookie, unsigned int value)
 991 {
 992         struct dmtimer *timer;
 993
 994         timer = to_dmtimer(cookie);
 995         if (unlikely(!timer || !atomic_read(&timer->enabled)))
 996                 return -EINVAL;
 997
 998         __omap_dm_timer_write_status(timer, value);
 999
1000         return 0;
1001 }
1002
1003 static unsigned int omap_dm_timer_read_counter(struct omap_dm_timer *cookie)
1004 {
1005         struct dmtimer *timer;
1006
1007         timer = to_dmtimer(cookie);
1008         if (unlikely(!timer || !atomic_read(&timer->enabled))) {
1009                 pr_err("%s: timer not iavailable or enabled.\n", __func__);
1010                 return 0;
1011         }
1012
1013         return __omap_dm_timer_read_counter(timer);
1014 }
1015
1016 static int omap_dm_timer_write_counter(struct omap_dm_timer *cookie, unsigned int value)
1017 {
1018         struct dmtimer *timer;
1019
1020         timer = to_dmtimer(cookie);
1021         if (unlikely(!timer || !atomic_read(&timer->enabled))) {
1022                 pr_err("%s: timer not available or enabled.\n", __func__);
1023                 return -EINVAL;
1024         }
1025
1026         dmtimer_write(timer, OMAP_TIMER_COUNTER_REG, value);
1027
1028         /* Save the context */
1029         timer->context.tcrr = value;
1030         return 0;
1031 }
1032
1033 static int __maybe_unused omap_dm_timer_runtime_suspend(struct device *dev)
1034 {
1035         struct dmtimer *timer = dev_get_drvdata(dev);
1036
1037         atomic_set(&timer->enabled, 0);
1038
1039         if (timer->capability & OMAP_TIMER_ALWON || !timer->func_base)
1040                 return 0;
1041
1042         omap_timer_save_context(timer);
1043
1044         return 0;
1045 }
1046
1047 static int __maybe_unused omap_dm_timer_runtime_resume(struct device *dev)
1048 {
1049         struct dmtimer *timer = dev_get_drvdata(dev);
1050
1051         if (!(timer->capability & OMAP_TIMER_ALWON) && timer->func_base)
1052                 omap_timer_restore_context(timer);
1053
1054         atomic_set(&timer->enabled, 1);
1055
1056         return 0;
1057 }
1058
1059 static const struct dev_pm_ops omap_dm_timer_pm_ops = {
1060         SET_RUNTIME_PM_OPS(omap_dm_timer_runtime_suspend,
1061                            omap_dm_timer_runtime_resume, NULL)
1062 };
1063
1064 static const struct of_device_id omap_timer_match[];
1065
1066 /**
1067  * omap_dm_timer_probe - probe function called for every registered device
1068  * @pdev:       pointer to current timer platform device
1069  *
1070  * Called by driver framework at the end of device registration for all
1071  * timer devices.
1072  */
1073 static int omap_dm_timer_probe(struct platform_device *pdev)
1074 {
1075         unsigned long flags;
1076         struct dmtimer *timer;
1077         struct device *dev = &pdev->dev;
1078         const struct dmtimer_platform_data *pdata;
1079         int ret;
1080
1081         pdata = of_device_get_match_data(dev);
1082         if (!pdata)
1083                 pdata = dev_get_platdata(dev);
1084         else
1085                 dev->platform_data = (void *)pdata;
1086
1087         if (!pdata) {
1088                 dev_err(dev, "%s: no platform data.\n", __func__);
1089                 return -ENODEV;
1090         }
1091
1092         timer = devm_kzalloc(dev, sizeof(*timer), GFP_KERNEL);
1093         if (!timer)
1094                 return  -ENOMEM;
1095
1096         timer->irq = platform_get_irq(pdev, 0);
1097         if (timer->irq < 0)
1098                 return timer->irq;
1099
1100         timer->io_base = devm_platform_ioremap_resource(pdev, 0);
1101         if (IS_ERR(timer->io_base))
1102                 return PTR_ERR(timer->io_base);
1103
1104         platform_set_drvdata(pdev, timer);
1105
1106         if (dev->of_node) {
1107                 if (of_property_read_bool(dev->of_node, "ti,timer-alwon"))
1108                         timer->capability |= OMAP_TIMER_ALWON;
1109                 if (of_property_read_bool(dev->of_node, "ti,timer-dsp"))
1110                         timer->capability |= OMAP_TIMER_HAS_DSP_IRQ;
1111                 if (of_property_read_bool(dev->of_node, "ti,timer-pwm"))
1112                         timer->capability |= OMAP_TIMER_HAS_PWM;
1113                 if (of_property_read_bool(dev->of_node, "ti,timer-secure"))
1114                         timer->capability |= OMAP_TIMER_SECURE;
1115         } else {
1116                 timer->id = pdev->id;
1117                 timer->capability = pdata->timer_capability;
1118                 timer->reserved = omap_dm_timer_reserved_systimer(timer->id);
1119         }
1120
1121         timer->omap1 = timer->capability & OMAP_TIMER_NEEDS_RESET;
1122
1123         /* OMAP1 devices do not yet use the clock framework for dmtimers */
1124         if (!timer->omap1) {
1125                 timer->fclk = devm_clk_get(dev, "fck");
1126                 if (IS_ERR(timer->fclk))
1127                         return PTR_ERR(timer->fclk);
1128         } else {
1129                 timer->fclk = ERR_PTR(-ENODEV);
1130         }
1131
1132         if (!(timer->capability & OMAP_TIMER_ALWON)) {
1133                 timer->nb.notifier_call = omap_timer_context_notifier;
1134                 cpu_pm_register_notifier(&timer->nb);
1135         }
1136
1137         timer->errata = pdata->timer_errata;
1138
1139         timer->pdev = pdev;
1140
1141         pm_runtime_enable(dev);
1142
1143         if (!timer->reserved) {
1144                 ret = pm_runtime_resume_and_get(dev);
1145                 if (ret) {
1146                         dev_err(dev, "%s: pm_runtime_get_sync failed!\n",
1147                                 __func__);
1148                         goto err_disable;
1149                 }
1150                 __omap_dm_timer_init_regs(timer);
1151
1152                 /* Clear timer configuration */
1153                 dmtimer_write(timer, OMAP_TIMER_CTRL_REG, 0);
1154
1155                 pm_runtime_put(dev);
1156         }
1157
1158         /* add the timer element to the list */
1159         spin_lock_irqsave(&dm_timer_lock, flags);
1160         list_add_tail(&timer->node, &omap_timer_list);
1161         spin_unlock_irqrestore(&dm_timer_lock, flags);
1162
1163         dev_dbg(dev, "Device Probed.\n");
1164
1165         return 0;
1166
1167 err_disable:
1168         pm_runtime_disable(dev);
1169         return ret;
1170 }
1171
1172 /**
1173  * omap_dm_timer_remove - cleanup a registered timer device
1174  * @pdev:       pointer to current timer platform device
1175  *
1176  * Called by driver framework whenever a timer device is unregistered.
1177  * In addition to freeing platform resources it also deletes the timer
1178  * entry from the local list.
1179  */
1180 static void omap_dm_timer_remove(struct platform_device *pdev)
1181 {
1182         struct dmtimer *timer;
1183         unsigned long flags;
1184         int ret = -EINVAL;
1185
1186         spin_lock_irqsave(&dm_timer_lock, flags);
1187         list_for_each_entry(timer, &omap_timer_list, node)
1188                 if (!strcmp(dev_name(&timer->pdev->dev),
1189                             dev_name(&pdev->dev))) {
1190                         if (!(timer->capability & OMAP_TIMER_ALWON))
1191                                 cpu_pm_unregister_notifier(&timer->nb);
1192                         list_del(&timer->node);
1193                         ret = 0;
1194                         break;
1195                 }
1196         spin_unlock_irqrestore(&dm_timer_lock, flags);
1197
1198         pm_runtime_disable(&pdev->dev);
1199
1200         if (ret)
1201                 dev_err(&pdev->dev, "Unable to determine timer entry in list of drivers on remove\n");
1202 }
1203
1204 static const struct omap_dm_timer_ops dmtimer_ops = {
1205         .request_by_node = omap_dm_timer_request_by_node,
1206         .request_specific = omap_dm_timer_request_specific,
1207         .request = omap_dm_timer_request,
1208         .set_source = omap_dm_timer_set_source,
1209         .get_irq = omap_dm_timer_get_irq,
1210         .set_int_enable = omap_dm_timer_set_int_enable,
1211         .set_int_disable = omap_dm_timer_set_int_disable,
1212         .free = omap_dm_timer_free,
1213         .enable = omap_dm_timer_enable,
1214         .disable = omap_dm_timer_disable,
1215         .get_fclk = omap_dm_timer_get_fclk,
1216         .start = omap_dm_timer_start,
1217         .stop = omap_dm_timer_stop,
1218         .set_load = omap_dm_timer_set_load,
1219         .set_match = omap_dm_timer_set_match,
1220         .set_pwm = omap_dm_timer_set_pwm,
1221         .get_pwm_status = omap_dm_timer_get_pwm_status,
1222         .set_prescaler = omap_dm_timer_set_prescaler,
1223         .read_counter = omap_dm_timer_read_counter,
1224         .write_counter = omap_dm_timer_write_counter,
1225         .read_status = omap_dm_timer_read_status,
1226         .write_status = omap_dm_timer_write_status,
1227 };
1228
1229 static const struct dmtimer_platform_data omap3plus_pdata = {
1230         .timer_errata = OMAP_TIMER_ERRATA_I103_I767,
1231         .timer_ops = &dmtimer_ops,
1232 };
1233
1234 static const struct dmtimer_platform_data am6_pdata = {
1235         .timer_ops = &dmtimer_ops,
1236 };
1237
1238 static const struct of_device_id omap_timer_match[] = {
1239         {
1240                 .compatible = "ti,omap2420-timer",
1241         },
1242         {
1243                 .compatible = "ti,omap3430-timer",
1244                 .data = &omap3plus_pdata,
1245         },
1246         {
1247                 .compatible = "ti,omap4430-timer",
1248                 .data = &omap3plus_pdata,
1249         },
1250         {
1251                 .compatible = "ti,omap5430-timer",
1252                 .data = &omap3plus_pdata,
1253         },
1254         {
1255                 .compatible = "ti,am335x-timer",
1256                 .data = &omap3plus_pdata,
1257         },
1258         {
1259                 .compatible = "ti,am335x-timer-1ms",
1260                 .data = &omap3plus_pdata,
1261         },
1262         {
1263                 .compatible = "ti,dm816-timer",
1264                 .data = &omap3plus_pdata,
1265         },
1266         {
1267                 .compatible = "ti,am654-timer",
1268                 .data = &am6_pdata,
1269         },
1270         {},
1271 };
1272 MODULE_DEVICE_TABLE(of, omap_timer_match);
1273
1274 static struct platform_driver omap_dm_timer_driver = {
1275         .probe  = omap_dm_timer_probe,
1276         .remove_new = omap_dm_timer_remove,
1277         .driver = {
1278                 .name   = "omap_timer",
1279                 .of_match_table = omap_timer_match,
1280                 .pm = &omap_dm_timer_pm_ops,
1281         },
1282 };
1283
1284 module_platform_driver(omap_dm_timer_driver);
1285
1286 MODULE_DESCRIPTION("OMAP Dual-Mode Timer Driver");
1287 MODULE_AUTHOR("Texas Instruments Inc");