drivers/clocksource/timer-ti-dm.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * linux/arch/arm/plat-omap/dmtimer.c
   4  *
   5  * OMAP Dual-Mode Timers
   6  *
   7  * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
   8  * Tarun Kanti DebBarma <tarun.kanti@ti.com>
   9  * Thara Gopinath <thara@ti.com>
  10  *
  11  * dmtimer adaptation to platform_driver.
  12  *
  13  * Copyright (C) 2005 Nokia Corporation
  14  * OMAP2 support by Juha Yrjola
  15  * API improvements and OMAP2 clock framework support by Timo Teras
  16  *
  17  * Copyright (C) 2009 Texas Instruments
  18  * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
  19  */
  20
  21 #include <linux/clk.h>
  22 #include <linux/clk-provider.h>
  23 #include <linux/cpu_pm.h>
  24 #include <linux/module.h>
  25 #include <linux/io.h>
  26 #include <linux/device.h>
  27 #include <linux/err.h>
  28 #include <linux/pm_runtime.h>
  29 #include <linux/of.h>
  30 #include <linux/of_device.h>
  31 #include <linux/platform_device.h>
  32 #include <linux/platform_data/dmtimer-omap.h>
  33
  34 #include <clocksource/timer-ti-dm.h>
  35
  36 static u32 omap_reserved_systimers;
  37 static LIST_HEAD(omap_timer_list);
  38 static DEFINE_SPINLOCK(dm_timer_lock);
  39
  40 enum {
  41         REQUEST_ANY = 0,
  42         REQUEST_BY_ID,
  43         REQUEST_BY_CAP,
  44         REQUEST_BY_NODE,
  45 };
  46
  47 /**
  48  * omap_dm_timer_read_reg - read timer registers in posted and non-posted mode
  49  * @timer:      timer pointer over which read operation to perform
  50  * @reg:        lowest byte holds the register offset
  51  *
  52  * The posted mode bit is encoded in reg. Note that in posted mode write
  53  * pending bit must be checked. Otherwise a read of a non completed write
  54  * will produce an error.
  55  */
  56 static inline u32 omap_dm_timer_read_reg(struct omap_dm_timer *timer, u32 reg)
  57 {
  58         WARN_ON((reg & 0xff) < _OMAP_TIMER_WAKEUP_EN_OFFSET);
  59         return __omap_dm_timer_read(timer, reg, timer->posted);
  60 }
  61
  62 /**
  63  * omap_dm_timer_write_reg - write timer registers in posted and non-posted mode
  64  * @timer:      timer pointer over which write operation is to perform
  65  * @reg:        lowest byte holds the register offset
  66  * @value:      data to write into the register
  67  *
  68  * The posted mode bit is encoded in reg. Note that in posted mode the write
  69  * pending bit must be checked. Otherwise a write on a register which has a
  70  * pending write will be lost.
  71  */
  72 static void omap_dm_timer_write_reg(struct omap_dm_timer *timer, u32 reg,
  73                                                 u32 value)
  74 {
  75         WARN_ON((reg & 0xff) < _OMAP_TIMER_WAKEUP_EN_OFFSET);
  76         __omap_dm_timer_write(timer, reg, value, timer->posted);
  77 }
  78
  79 static void omap_timer_restore_context(struct omap_dm_timer *timer)
  80 {
  81         omap_dm_timer_write_reg(timer, OMAP_TIMER_WAKEUP_EN_REG,
  82                                 timer->context.twer);
  83         omap_dm_timer_write_reg(timer, OMAP_TIMER_COUNTER_REG,
  84                                 timer->context.tcrr);
  85         omap_dm_timer_write_reg(timer, OMAP_TIMER_LOAD_REG,
  86                                 timer->context.tldr);
  87         omap_dm_timer_write_reg(timer, OMAP_TIMER_MATCH_REG,
  88                                 timer->context.tmar);
  89         omap_dm_timer_write_reg(timer, OMAP_TIMER_IF_CTRL_REG,
  90                                 timer->context.tsicr);
  91         writel_relaxed(timer->context.tier, timer->irq_ena);
  92         omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG,
  93                                 timer->context.tclr);
  94 }
  95
  96 static void omap_timer_save_context(struct omap_dm_timer *timer)
  97 {
  98         timer->context.tclr =
  99                         omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
 100         timer->context.twer =
 101                         omap_dm_timer_read_reg(timer, OMAP_TIMER_WAKEUP_EN_REG);
 102         timer->context.tldr =
 103                         omap_dm_timer_read_reg(timer, OMAP_TIMER_LOAD_REG);
 104         timer->context.tmar =
 105                         omap_dm_timer_read_reg(timer, OMAP_TIMER_MATCH_REG);
 106         timer->context.tier = readl_relaxed(timer->irq_ena);
 107         timer->context.tsicr =
 108                         omap_dm_timer_read_reg(timer, OMAP_TIMER_IF_CTRL_REG);
 109 }
 110
 111 static int omap_timer_context_notifier(struct notifier_block *nb,
 112                                        unsigned long cmd, void *v)
 113 {
 114         struct omap_dm_timer *timer;
 115
 116         timer = container_of(nb, struct omap_dm_timer, nb);
 117
 118         switch (cmd) {
 119         case CPU_CLUSTER_PM_ENTER:
 120                 if ((timer->capability & OMAP_TIMER_ALWON) ||
 121                     !atomic_read(&timer->enabled))
 122                         break;
 123                 omap_timer_save_context(timer);
 124                 break;
 125         case CPU_CLUSTER_PM_ENTER_FAILED:
 126         case CPU_CLUSTER_PM_EXIT:
 127                 if ((timer->capability & OMAP_TIMER_ALWON) ||
 128                     !atomic_read(&timer->enabled))
 129                         break;
 130                 omap_timer_restore_context(timer);
 131                 break;
 132         }
 133
 134         return NOTIFY_OK;
 135 }
 136
 137 static int omap_dm_timer_reset(struct omap_dm_timer *timer)
 138 {
 139         u32 l, timeout = 100000;
 140
 141         if (timer->revision != 1)
 142                 return -EINVAL;
 143
 144         omap_dm_timer_write_reg(timer, OMAP_TIMER_IF_CTRL_REG, 0x06);
 145
 146         do {
 147                 l = __omap_dm_timer_read(timer,
 148                                          OMAP_TIMER_V1_SYS_STAT_OFFSET, 0);
 149         } while (!l && timeout--);
 150
 151         if (!timeout) {
 152                 dev_err(&timer->pdev->dev, "Timer failed to reset\n");
 153                 return -ETIMEDOUT;
 154         }
 155
 156         /* Configure timer for smart-idle mode */
 157         l = __omap_dm_timer_read(timer, OMAP_TIMER_OCP_CFG_OFFSET, 0);
 158         l |= 0x2 << 0x3;
 159         __omap_dm_timer_write(timer, OMAP_TIMER_OCP_CFG_OFFSET, l, 0);
 160
 161         timer->posted = 0;
 162
 163         return 0;
 164 }
 165
 166 static int omap_dm_timer_set_source(struct omap_dm_timer *timer, int source)
 167 {
 168         int ret;
 169         const char *parent_name;
 170         struct clk *parent;
 171         struct dmtimer_platform_data *pdata;
 172
 173         if (unlikely(!timer) || IS_ERR(timer->fclk))
 174                 return -EINVAL;
 175
 176         switch (source) {
 177         case OMAP_TIMER_SRC_SYS_CLK:
 178                 parent_name = "timer_sys_ck";
 179                 break;
 180         case OMAP_TIMER_SRC_32_KHZ:
 181                 parent_name = "timer_32k_ck";
 182                 break;
 183         case OMAP_TIMER_SRC_EXT_CLK:
 184                 parent_name = "timer_ext_ck";
 185                 break;
 186         default:
 187                 return -EINVAL;
 188         }
 189
 190         pdata = timer->pdev->dev.platform_data;
 191
 192         /*
 193          * FIXME: Used for OMAP1 devices only because they do not currently
 194          * use the clock framework to set the parent clock. To be removed
 195          * once OMAP1 migrated to using clock framework for dmtimers
 196          */
 197         if (pdata && pdata->set_timer_src)
 198                 return pdata->set_timer_src(timer->pdev, source);
 199
 200 #if defined(CONFIG_COMMON_CLK)
 201         /* Check if the clock has configurable parents */
 202         if (clk_hw_get_num_parents(__clk_get_hw(timer->fclk)) < 2)
 203                 return 0;
 204 #endif
 205
 206         parent = clk_get(&timer->pdev->dev, parent_name);
 207         if (IS_ERR(parent)) {
 208                 pr_err("%s: %s not found\n", __func__, parent_name);
 209                 return -EINVAL;
 210         }
 211
 212         ret = clk_set_parent(timer->fclk, parent);
 213         if (ret < 0)
 214                 pr_err("%s: failed to set %s as parent\n", __func__,
 215                         parent_name);
 216
 217         clk_put(parent);
 218
 219         return ret;
 220 }
 221
 222 static void omap_dm_timer_enable(struct omap_dm_timer *timer)
 223 {
 224         pm_runtime_get_sync(&timer->pdev->dev);
 225 }
 226
 227 static void omap_dm_timer_disable(struct omap_dm_timer *timer)
 228 {
 229         pm_runtime_put_sync(&timer->pdev->dev);
 230 }
 231
 232 static int omap_dm_timer_prepare(struct omap_dm_timer *timer)
 233 {
 234         int rc;
 235
 236         /*
 237          * FIXME: OMAP1 devices do not use the clock framework for dmtimers so
 238          * do not call clk_get() for these devices.
 239          */
 240         if (!(timer->capability & OMAP_TIMER_NEEDS_RESET)) {
 241                 timer->fclk = clk_get(&timer->pdev->dev, "fck");
 242                 if (WARN_ON_ONCE(IS_ERR(timer->fclk))) {
 243                         dev_err(&timer->pdev->dev, ": No fclk handle.\n");
 244                         return -EINVAL;
 245                 }
 246         }
 247
 248         omap_dm_timer_enable(timer);
 249
 250         if (timer->capability & OMAP_TIMER_NEEDS_RESET) {
 251                 rc = omap_dm_timer_reset(timer);
 252                 if (rc) {
 253                         omap_dm_timer_disable(timer);
 254                         return rc;
 255                 }
 256         }
 257
 258         __omap_dm_timer_enable_posted(timer);
 259         omap_dm_timer_disable(timer);
 260
 261         rc = omap_dm_timer_set_source(timer, OMAP_TIMER_SRC_32_KHZ);
 262
 263         return rc;
 264 }
 265
 266 static inline u32 omap_dm_timer_reserved_systimer(int id)
 267 {
 268         return (omap_reserved_systimers & (1 << (id - 1))) ? 1 : 0;
 269 }
 270
 271 int omap_dm_timer_reserve_systimer(int id)
 272 {
 273         if (omap_dm_timer_reserved_systimer(id))
 274                 return -ENODEV;
 275
 276         omap_reserved_systimers |= (1 << (id - 1));
 277
 278         return 0;
 279 }
 280
 281 static struct omap_dm_timer *_omap_dm_timer_request(int req_type, void *data)
 282 {
 283         struct omap_dm_timer *timer = NULL, *t;
 284         struct device_node *np = NULL;
 285         unsigned long flags;
 286         u32 cap = 0;
 287         int id = 0;
 288
 289         switch (req_type) {
 290         case REQUEST_BY_ID:
 291                 id = *(int *)data;
 292                 break;
 293         case REQUEST_BY_CAP:
 294                 cap = *(u32 *)data;
 295                 break;
 296         case REQUEST_BY_NODE:
 297                 np = (struct device_node *)data;
 298                 break;
 299         default:
 300                 /* REQUEST_ANY */
 301                 break;
 302         }
 303
 304         spin_lock_irqsave(&dm_timer_lock, flags);
 305         list_for_each_entry(t, &omap_timer_list, node) {
 306                 if (t->reserved)
 307                         continue;
 308
 309                 switch (req_type) {
 310                 case REQUEST_BY_ID:
 311                         if (id == t->pdev->id) {
 312                                 timer = t;
 313                                 timer->reserved = 1;
 314                                 goto found;
 315                         }
 316                         break;
 317                 case REQUEST_BY_CAP:
 318                         if (cap == (t->capability & cap)) {
 319                                 /*
 320                                  * If timer is not NULL, we have already found
 321                                  * one timer. But it was not an exact match
 322                                  * because it had more capabilities than what
 323                                  * was required. Therefore, unreserve the last
 324                                  * timer found and see if this one is a better
 325                                  * match.
 326                                  */
 327                                 if (timer)
 328                                         timer->reserved = 0;
 329                                 timer = t;
 330                                 timer->reserved = 1;
 331
 332                                 /* Exit loop early if we find an exact match */
 333                                 if (t->capability == cap)
 334                                         goto found;
 335                         }
 336                         break;
 337                 case REQUEST_BY_NODE:
 338                         if (np == t->pdev->dev.of_node) {
 339                                 timer = t;
 340                                 timer->reserved = 1;
 341                                 goto found;
 342                         }
 343                         break;
 344                 default:
 345                         /* REQUEST_ANY */
 346                         timer = t;
 347                         timer->reserved = 1;
 348                         goto found;
 349                 }
 350         }
 351 found:
 352         spin_unlock_irqrestore(&dm_timer_lock, flags);
 353
 354         if (timer && omap_dm_timer_prepare(timer)) {
 355                 timer->reserved = 0;
 356                 timer = NULL;
 357         }
 358
 359         if (!timer)
 360                 pr_debug("%s: timer request failed!\n", __func__);
 361
 362         return timer;
 363 }
 364
 365 static struct omap_dm_timer *omap_dm_timer_request(void)
 366 {
 367         return _omap_dm_timer_request(REQUEST_ANY, NULL);
 368 }
 369
 370 static struct omap_dm_timer *omap_dm_timer_request_specific(int id)
 371 {
 372         /* Requesting timer by ID is not supported when device tree is used */
 373         if (of_have_populated_dt()) {
 374                 pr_warn("%s: Please use omap_dm_timer_request_by_node()\n",
 375                         __func__);
 376                 return NULL;
 377         }
 378
 379         return _omap_dm_timer_request(REQUEST_BY_ID, &id);
 380 }
 381
 382 /**
 383  * omap_dm_timer_request_by_cap - Request a timer by capability
 384  * @cap:        Bit mask of capabilities to match
 385  *
 386  * Find a timer based upon capabilities bit mask. Callers of this function
 387  * should use the definitions found in the plat/dmtimer.h file under the
 388  * comment "timer capabilities used in hwmod database". Returns pointer to
 389  * timer handle on success and a NULL pointer on failure.
 390  */
 391 struct omap_dm_timer *omap_dm_timer_request_by_cap(u32 cap)
 392 {
 393         return _omap_dm_timer_request(REQUEST_BY_CAP, &cap);
 394 }
 395
 396 /**
 397  * omap_dm_timer_request_by_node - Request a timer by device-tree node
 398  * @np:         Pointer to device-tree timer node
 399  *
 400  * Request a timer based upon a device node pointer. Returns pointer to
 401  * timer handle on success and a NULL pointer on failure.
 402  */
 403 static struct omap_dm_timer *omap_dm_timer_request_by_node(struct device_node *np)
 404 {
 405         if (!np)
 406                 return NULL;
 407
 408         return _omap_dm_timer_request(REQUEST_BY_NODE, np);
 409 }
 410
 411 static int omap_dm_timer_free(struct omap_dm_timer *timer)
 412 {
 413         if (unlikely(!timer))
 414                 return -EINVAL;
 415
 416         clk_put(timer->fclk);
 417
 418         WARN_ON(!timer->reserved);
 419         timer->reserved = 0;
 420         return 0;
 421 }
 422
 423 int omap_dm_timer_get_irq(struct omap_dm_timer *timer)
 424 {
 425         if (timer)
 426                 return timer->irq;
 427         return -EINVAL;
 428 }
 429
 430 #if defined(CONFIG_ARCH_OMAP1)
 431 #include <mach/hardware.h>
 432
 433 static struct clk *omap_dm_timer_get_fclk(struct omap_dm_timer *timer)
 434 {
 435         return NULL;
 436 }
 437
 438 /**
 439  * omap_dm_timer_modify_idlect_mask - Check if any running timers use ARMXOR
 440  * @inputmask: current value of idlect mask
 441  */
 442 __u32 omap_dm_timer_modify_idlect_mask(__u32 inputmask)
 443 {
 444         int i = 0;
 445         struct omap_dm_timer *timer = NULL;
 446         unsigned long flags;
 447
 448         /* If ARMXOR cannot be idled this function call is unnecessary */
 449         if (!(inputmask & (1 << 1)))
 450                 return inputmask;
 451
 452         /* If any active timer is using ARMXOR return modified mask */
 453         spin_lock_irqsave(&dm_timer_lock, flags);
 454         list_for_each_entry(timer, &omap_timer_list, node) {
 455                 u32 l;
 456
 457                 l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
 458                 if (l & OMAP_TIMER_CTRL_ST) {
 459                         if (((omap_readl(MOD_CONF_CTRL_1) >> (i * 2)) & 0x03) == 0)
 460                                 inputmask &= ~(1 << 1);
 461                         else
 462                                 inputmask &= ~(1 << 2);
 463                 }
 464                 i++;
 465         }
 466         spin_unlock_irqrestore(&dm_timer_lock, flags);
 467
 468         return inputmask;
 469 }
 470
 471 #else
 472
 473 static struct clk *omap_dm_timer_get_fclk(struct omap_dm_timer *timer)
 474 {
 475         if (timer && !IS_ERR(timer->fclk))
 476                 return timer->fclk;
 477         return NULL;
 478 }
 479
 480 __u32 omap_dm_timer_modify_idlect_mask(__u32 inputmask)
 481 {
 482         BUG();
 483
 484         return 0;
 485 }
 486
 487 #endif
 488
 489 int omap_dm_timer_trigger(struct omap_dm_timer *timer)
 490 {
 491         if (unlikely(!timer || !atomic_read(&timer->enabled))) {
 492                 pr_err("%s: timer not available or enabled.\n", __func__);
 493                 return -EINVAL;
 494         }
 495
 496         omap_dm_timer_write_reg(timer, OMAP_TIMER_TRIGGER_REG, 0);
 497         return 0;
 498 }
 499
 500 static int omap_dm_timer_start(struct omap_dm_timer *timer)
 501 {
 502         u32 l;
 503
 504         if (unlikely(!timer))
 505                 return -EINVAL;
 506
 507         omap_dm_timer_enable(timer);
 508
 509         l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
 510         if (!(l & OMAP_TIMER_CTRL_ST)) {
 511                 l |= OMAP_TIMER_CTRL_ST;
 512                 omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
 513         }
 514
 515         return 0;
 516 }
 517
 518 static int omap_dm_timer_stop(struct omap_dm_timer *timer)
 519 {
 520         unsigned long rate = 0;
 521
 522         if (unlikely(!timer))
 523                 return -EINVAL;
 524
 525         if (!(timer->capability & OMAP_TIMER_NEEDS_RESET))
 526                 rate = clk_get_rate(timer->fclk);
 527
 528         __omap_dm_timer_stop(timer, timer->posted, rate);
 529
 530         omap_dm_timer_disable(timer);
 531         return 0;
 532 }
 533
 534 static int omap_dm_timer_set_load(struct omap_dm_timer *timer,
 535                                   unsigned int load)
 536 {
 537         if (unlikely(!timer))
 538                 return -EINVAL;
 539
 540         omap_dm_timer_enable(timer);
 541         omap_dm_timer_write_reg(timer, OMAP_TIMER_LOAD_REG, load);
 542
 543         omap_dm_timer_disable(timer);
 544         return 0;
 545 }
 546
 547 static int omap_dm_timer_set_match(struct omap_dm_timer *timer, int enable,
 548                                    unsigned int match)
 549 {
 550         u32 l;
 551
 552         if (unlikely(!timer))
 553                 return -EINVAL;
 554
 555         omap_dm_timer_enable(timer);
 556         l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
 557         if (enable)
 558                 l |= OMAP_TIMER_CTRL_CE;
 559         else
 560                 l &= ~OMAP_TIMER_CTRL_CE;
 561         omap_dm_timer_write_reg(timer, OMAP_TIMER_MATCH_REG, match);
 562         omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
 563
 564         omap_dm_timer_disable(timer);
 565         return 0;
 566 }
 567
 568 static int omap_dm_timer_set_pwm(struct omap_dm_timer *timer, int def_on,
 569                                  int toggle, int trigger, int autoreload)
 570 {
 571         u32 l;
 572
 573         if (unlikely(!timer))
 574                 return -EINVAL;
 575
 576         omap_dm_timer_enable(timer);
 577         l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
 578         l &= ~(OMAP_TIMER_CTRL_GPOCFG | OMAP_TIMER_CTRL_SCPWM |
 579                OMAP_TIMER_CTRL_PT | (0x03 << 10) | OMAP_TIMER_CTRL_AR);
 580         if (def_on)
 581                 l |= OMAP_TIMER_CTRL_SCPWM;
 582         if (toggle)
 583                 l |= OMAP_TIMER_CTRL_PT;
 584         l |= trigger << 10;
 585         if (autoreload)
 586                 l |= OMAP_TIMER_CTRL_AR;
 587         omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
 588
 589         omap_dm_timer_disable(timer);
 590         return 0;
 591 }
 592
 593 static int omap_dm_timer_get_pwm_status(struct omap_dm_timer *timer)
 594 {
 595         u32 l;
 596
 597         if (unlikely(!timer))
 598                 return -EINVAL;
 599
 600         omap_dm_timer_enable(timer);
 601         l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
 602         omap_dm_timer_disable(timer);
 603
 604         return l;
 605 }
 606
 607 static int omap_dm_timer_set_prescaler(struct omap_dm_timer *timer,
 608                                         int prescaler)
 609 {
 610         u32 l;
 611
 612         if (unlikely(!timer) || prescaler < -1 || prescaler > 7)
 613                 return -EINVAL;
 614
 615         omap_dm_timer_enable(timer);
 616         l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
 617         l &= ~(OMAP_TIMER_CTRL_PRE | (0x07 << 2));
 618         if (prescaler >= 0) {
 619                 l |= OMAP_TIMER_CTRL_PRE;
 620                 l |= prescaler << 2;
 621         }
 622         omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
 623
 624         omap_dm_timer_disable(timer);
 625         return 0;
 626 }
 627
 628 static int omap_dm_timer_set_int_enable(struct omap_dm_timer *timer,
 629                                         unsigned int value)
 630 {
 631         if (unlikely(!timer))
 632                 return -EINVAL;
 633
 634         omap_dm_timer_enable(timer);
 635         __omap_dm_timer_int_enable(timer, value);
 636
 637         omap_dm_timer_disable(timer);
 638         return 0;
 639 }
 640
 641 /**
 642  * omap_dm_timer_set_int_disable - disable timer interrupts
 643  * @timer:      pointer to timer handle
 644  * @mask:       bit mask of interrupts to be disabled
 645  *
 646  * Disables the specified timer interrupts for a timer.
 647  */
 648 static int omap_dm_timer_set_int_disable(struct omap_dm_timer *timer, u32 mask)
 649 {
 650         u32 l = mask;
 651
 652         if (unlikely(!timer))
 653                 return -EINVAL;
 654
 655         omap_dm_timer_enable(timer);
 656
 657         if (timer->revision == 1)
 658                 l = readl_relaxed(timer->irq_ena) & ~mask;
 659
 660         writel_relaxed(l, timer->irq_dis);
 661         l = omap_dm_timer_read_reg(timer, OMAP_TIMER_WAKEUP_EN_REG) & ~mask;
 662         omap_dm_timer_write_reg(timer, OMAP_TIMER_WAKEUP_EN_REG, l);
 663
 664         omap_dm_timer_disable(timer);
 665         return 0;
 666 }
 667
 668 static unsigned int omap_dm_timer_read_status(struct omap_dm_timer *timer)
 669 {
 670         unsigned int l;
 671
 672         if (unlikely(!timer || !atomic_read(&timer->enabled))) {
 673                 pr_err("%s: timer not available or enabled.\n", __func__);
 674                 return 0;
 675         }
 676
 677         l = readl_relaxed(timer->irq_stat);
 678
 679         return l;
 680 }
 681
 682 static int omap_dm_timer_write_status(struct omap_dm_timer *timer, unsigned int value)
 683 {
 684         if (unlikely(!timer || !atomic_read(&timer->enabled)))
 685                 return -EINVAL;
 686
 687         __omap_dm_timer_write_status(timer, value);
 688
 689         return 0;
 690 }
 691
 692 static unsigned int omap_dm_timer_read_counter(struct omap_dm_timer *timer)
 693 {
 694         if (unlikely(!timer || !atomic_read(&timer->enabled))) {
 695                 pr_err("%s: timer not iavailable or enabled.\n", __func__);
 696                 return 0;
 697         }
 698
 699         return __omap_dm_timer_read_counter(timer, timer->posted);
 700 }
 701
 702 static int omap_dm_timer_write_counter(struct omap_dm_timer *timer, unsigned int value)
 703 {
 704         if (unlikely(!timer || !atomic_read(&timer->enabled))) {
 705                 pr_err("%s: timer not available or enabled.\n", __func__);
 706                 return -EINVAL;
 707         }
 708
 709         omap_dm_timer_write_reg(timer, OMAP_TIMER_COUNTER_REG, value);
 710
 711         /* Save the context */
 712         timer->context.tcrr = value;
 713         return 0;
 714 }
 715
 716 int omap_dm_timers_active(void)
 717 {
 718         struct omap_dm_timer *timer;
 719
 720         list_for_each_entry(timer, &omap_timer_list, node) {
 721                 if (!timer->reserved)
 722                         continue;
 723
 724                 if (omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG) &
 725                     OMAP_TIMER_CTRL_ST) {
 726                         return 1;
 727                 }
 728         }
 729         return 0;
 730 }
 731
 732 static int __maybe_unused omap_dm_timer_runtime_suspend(struct device *dev)
 733 {
 734         struct omap_dm_timer *timer = dev_get_drvdata(dev);
 735
 736         atomic_set(&timer->enabled, 0);
 737
 738         if (timer->capability & OMAP_TIMER_ALWON || !timer->func_base)
 739                 return 0;
 740
 741         omap_timer_save_context(timer);
 742
 743         return 0;
 744 }
 745
 746 static int __maybe_unused omap_dm_timer_runtime_resume(struct device *dev)
 747 {
 748         struct omap_dm_timer *timer = dev_get_drvdata(dev);
 749
 750         if (!(timer->capability & OMAP_TIMER_ALWON) && timer->func_base)
 751                 omap_timer_restore_context(timer);
 752
 753         atomic_set(&timer->enabled, 1);
 754
 755         return 0;
 756 }
 757
 758 static const struct dev_pm_ops omap_dm_timer_pm_ops = {
 759         SET_RUNTIME_PM_OPS(omap_dm_timer_runtime_suspend,
 760                            omap_dm_timer_runtime_resume, NULL)
 761 };
 762
 763 static const struct of_device_id omap_timer_match[];
 764
 765 /**
 766  * omap_dm_timer_probe - probe function called for every registered device
 767  * @pdev:       pointer to current timer platform device
 768  *
 769  * Called by driver framework at the end of device registration for all
 770  * timer devices.
 771  */
 772 static int omap_dm_timer_probe(struct platform_device *pdev)
 773 {
 774         unsigned long flags;
 775         struct omap_dm_timer *timer;
 776         struct device *dev = &pdev->dev;
 777         const struct dmtimer_platform_data *pdata;
 778         int ret;
 779
 780         pdata = of_device_get_match_data(dev);
 781         if (!pdata)
 782                 pdata = dev_get_platdata(dev);
 783         else
 784                 dev->platform_data = (void *)pdata;
 785
 786         if (!pdata) {
 787                 dev_err(dev, "%s: no platform data.\n", __func__);
 788                 return -ENODEV;
 789         }
 790
 791         timer = devm_kzalloc(dev, sizeof(*timer), GFP_KERNEL);
 792         if (!timer)
 793                 return  -ENOMEM;
 794
 795         timer->irq = platform_get_irq(pdev, 0);
 796         if (timer->irq < 0)
 797                 return timer->irq;
 798
 799         timer->fclk = ERR_PTR(-ENODEV);
 800         timer->io_base = devm_platform_ioremap_resource(pdev, 0);
 801         if (IS_ERR(timer->io_base))
 802                 return PTR_ERR(timer->io_base);
 803
 804         platform_set_drvdata(pdev, timer);
 805
 806         if (dev->of_node) {
 807                 if (of_find_property(dev->of_node, "ti,timer-alwon", NULL))
 808                         timer->capability |= OMAP_TIMER_ALWON;
 809                 if (of_find_property(dev->of_node, "ti,timer-dsp", NULL))
 810                         timer->capability |= OMAP_TIMER_HAS_DSP_IRQ;
 811                 if (of_find_property(dev->of_node, "ti,timer-pwm", NULL))
 812                         timer->capability |= OMAP_TIMER_HAS_PWM;
 813                 if (of_find_property(dev->of_node, "ti,timer-secure", NULL))
 814                         timer->capability |= OMAP_TIMER_SECURE;
 815         } else {
 816                 timer->id = pdev->id;
 817                 timer->capability = pdata->timer_capability;
 818                 timer->reserved = omap_dm_timer_reserved_systimer(timer->id);
 819         }
 820
 821         if (!(timer->capability & OMAP_TIMER_ALWON)) {
 822                 timer->nb.notifier_call = omap_timer_context_notifier;
 823                 cpu_pm_register_notifier(&timer->nb);
 824         }
 825
 826         if (pdata)
 827                 timer->errata = pdata->timer_errata;
 828
 829         timer->pdev = pdev;
 830
 831         pm_runtime_enable(dev);
 832
 833         if (!timer->reserved) {
 834                 ret = pm_runtime_get_sync(dev);
 835                 if (ret < 0) {
 836                         dev_err(dev, "%s: pm_runtime_get_sync failed!\n",
 837                                 __func__);
 838                         goto err_get_sync;
 839                 }
 840                 __omap_dm_timer_init_regs(timer);
 841                 pm_runtime_put(dev);
 842         }
 843
 844         /* add the timer element to the list */
 845         spin_lock_irqsave(&dm_timer_lock, flags);
 846         list_add_tail(&timer->node, &omap_timer_list);
 847         spin_unlock_irqrestore(&dm_timer_lock, flags);
 848
 849         dev_dbg(dev, "Device Probed.\n");
 850
 851         return 0;
 852
 853 err_get_sync:
 854         pm_runtime_put_noidle(dev);
 855         pm_runtime_disable(dev);
 856         return ret;
 857 }
 858
 859 /**
 860  * omap_dm_timer_remove - cleanup a registered timer device
 861  * @pdev:       pointer to current timer platform device
 862  *
 863  * Called by driver framework whenever a timer device is unregistered.
 864  * In addition to freeing platform resources it also deletes the timer
 865  * entry from the local list.
 866  */
 867 static int omap_dm_timer_remove(struct platform_device *pdev)
 868 {
 869         struct omap_dm_timer *timer;
 870         unsigned long flags;
 871         int ret = -EINVAL;
 872
 873         spin_lock_irqsave(&dm_timer_lock, flags);
 874         list_for_each_entry(timer, &omap_timer_list, node)
 875                 if (!strcmp(dev_name(&timer->pdev->dev),
 876                             dev_name(&pdev->dev))) {
 877                         if (!(timer->capability & OMAP_TIMER_ALWON))
 878                                 cpu_pm_unregister_notifier(&timer->nb);
 879                         list_del(&timer->node);
 880                         ret = 0;
 881                         break;
 882                 }
 883         spin_unlock_irqrestore(&dm_timer_lock, flags);
 884
 885         pm_runtime_disable(&pdev->dev);
 886
 887         return ret;
 888 }
 889
 890 static const struct omap_dm_timer_ops dmtimer_ops = {
 891         .request_by_node = omap_dm_timer_request_by_node,
 892         .request_specific = omap_dm_timer_request_specific,
 893         .request = omap_dm_timer_request,
 894         .set_source = omap_dm_timer_set_source,
 895         .get_irq = omap_dm_timer_get_irq,
 896         .set_int_enable = omap_dm_timer_set_int_enable,
 897         .set_int_disable = omap_dm_timer_set_int_disable,
 898         .free = omap_dm_timer_free,
 899         .enable = omap_dm_timer_enable,
 900         .disable = omap_dm_timer_disable,
 901         .get_fclk = omap_dm_timer_get_fclk,
 902         .start = omap_dm_timer_start,
 903         .stop = omap_dm_timer_stop,
 904         .set_load = omap_dm_timer_set_load,
 905         .set_match = omap_dm_timer_set_match,
 906         .set_pwm = omap_dm_timer_set_pwm,
 907         .get_pwm_status = omap_dm_timer_get_pwm_status,
 908         .set_prescaler = omap_dm_timer_set_prescaler,
 909         .read_counter = omap_dm_timer_read_counter,
 910         .write_counter = omap_dm_timer_write_counter,
 911         .read_status = omap_dm_timer_read_status,
 912         .write_status = omap_dm_timer_write_status,
 913 };
 914
 915 static const struct dmtimer_platform_data omap3plus_pdata = {
 916         .timer_errata = OMAP_TIMER_ERRATA_I103_I767,
 917         .timer_ops = &dmtimer_ops,
 918 };
 919
 920 static const struct of_device_id omap_timer_match[] = {
 921         {
 922                 .compatible = "ti,omap2420-timer",
 923         },
 924         {
 925                 .compatible = "ti,omap3430-timer",
 926                 .data = &omap3plus_pdata,
 927         },
 928         {
 929                 .compatible = "ti,omap4430-timer",
 930                 .data = &omap3plus_pdata,
 931         },
 932         {
 933                 .compatible = "ti,omap5430-timer",
 934                 .data = &omap3plus_pdata,
 935         },
 936         {
 937                 .compatible = "ti,am335x-timer",
 938                 .data = &omap3plus_pdata,
 939         },
 940         {
 941                 .compatible = "ti,am335x-timer-1ms",
 942                 .data = &omap3plus_pdata,
 943         },
 944         {
 945                 .compatible = "ti,dm816-timer",
 946                 .data = &omap3plus_pdata,
 947         },
 948         {},
 949 };
 950 MODULE_DEVICE_TABLE(of, omap_timer_match);
 951
 952 static struct platform_driver omap_dm_timer_driver = {
 953         .probe  = omap_dm_timer_probe,
 954         .remove = omap_dm_timer_remove,
 955         .driver = {
 956                 .name   = "omap_timer",
 957                 .of_match_table = of_match_ptr(omap_timer_match),
 958                 .pm = &omap_dm_timer_pm_ops,
 959         },
 960 };
 961
 962 module_platform_driver(omap_dm_timer_driver);
 963
 964 MODULE_DESCRIPTION("OMAP Dual-Mode Timer Driver");
 965 MODULE_LICENSE("GPL");
 966 MODULE_AUTHOR("Texas Instruments Inc");