drivers/clocksource/timer-sun5i.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Allwinner SoCs hstimer driver.
   4  *
   5  * Copyright (C) 2013 Maxime Ripard
   6  *
   7  * Maxime Ripard <maxime.ripard@free-electrons.com>
   8  */
   9
  10 #include <linux/clk.h>
  11 #include <linux/clockchips.h>
  12 #include <linux/clocksource.h>
  13 #include <linux/delay.h>
  14 #include <linux/interrupt.h>
  15 #include <linux/irq.h>
  16 #include <linux/irqreturn.h>
  17 #include <linux/reset.h>
  18 #include <linux/slab.h>
  19 #include <linux/of.h>
  20 #include <linux/of_address.h>
  21 #include <linux/of_irq.h>
  22
  23 #define TIMER_IRQ_EN_REG                0x00
  24 #define TIMER_IRQ_EN(val)                       BIT(val)
  25 #define TIMER_IRQ_ST_REG                0x04
  26 #define TIMER_CTL_REG(val)              (0x20 * (val) + 0x10)
  27 #define TIMER_CTL_ENABLE                        BIT(0)
  28 #define TIMER_CTL_RELOAD                        BIT(1)
  29 #define TIMER_CTL_CLK_PRES(val)                 (((val) & 0x7) << 4)
  30 #define TIMER_CTL_ONESHOT                       BIT(7)
  31 #define TIMER_INTVAL_LO_REG(val)        (0x20 * (val) + 0x14)
  32 #define TIMER_INTVAL_HI_REG(val)        (0x20 * (val) + 0x18)
  33 #define TIMER_CNTVAL_LO_REG(val)        (0x20 * (val) + 0x1c)
  34 #define TIMER_CNTVAL_HI_REG(val)        (0x20 * (val) + 0x20)
  35
  36 #define TIMER_SYNC_TICKS        3
  37
  38 struct sun5i_timer {
  39         void __iomem            *base;
  40         struct clk              *clk;
  41         struct notifier_block   clk_rate_cb;
  42         u32                     ticks_per_jiffy;
  43         struct clocksource      clksrc;
  44         struct clock_event_device       clkevt;
  45 };
  46
  47 #define nb_to_sun5i_timer(x) \
  48         container_of(x, struct sun5i_timer, clk_rate_cb)
  49 #define clksrc_to_sun5i_timer(x) \
  50         container_of(x, struct sun5i_timer, clksrc)
  51 #define clkevt_to_sun5i_timer(x) \
  52         container_of(x, struct sun5i_timer, clkevt)
  53
  54 /*
  55  * When we disable a timer, we need to wait at least for 2 cycles of
  56  * the timer source clock. We will use for that the clocksource timer
  57  * that is already setup and runs at the same frequency than the other
  58  * timers, and we never will be disabled.
  59  */
  60 static void sun5i_clkevt_sync(struct sun5i_timer *ce)
  61 {
  62         u32 old = readl(ce->base + TIMER_CNTVAL_LO_REG(1));
  63
  64         while ((old - readl(ce->base + TIMER_CNTVAL_LO_REG(1))) < TIMER_SYNC_TICKS)
  65                 cpu_relax();
  66 }
  67
  68 static void sun5i_clkevt_time_stop(struct sun5i_timer *ce, u8 timer)
  69 {
  70         u32 val = readl(ce->base + TIMER_CTL_REG(timer));
  71         writel(val & ~TIMER_CTL_ENABLE, ce->base + TIMER_CTL_REG(timer));
  72
  73         sun5i_clkevt_sync(ce);
  74 }
  75
  76 static void sun5i_clkevt_time_setup(struct sun5i_timer *ce, u8 timer, u32 delay)
  77 {
  78         writel(delay, ce->base + TIMER_INTVAL_LO_REG(timer));
  79 }
  80
  81 static void sun5i_clkevt_time_start(struct sun5i_timer *ce, u8 timer, bool periodic)
  82 {
  83         u32 val = readl(ce->base + TIMER_CTL_REG(timer));
  84
  85         if (periodic)
  86                 val &= ~TIMER_CTL_ONESHOT;
  87         else
  88                 val |= TIMER_CTL_ONESHOT;
  89
  90         writel(val | TIMER_CTL_ENABLE | TIMER_CTL_RELOAD,
  91                ce->base + TIMER_CTL_REG(timer));
  92 }
  93
  94 static int sun5i_clkevt_shutdown(struct clock_event_device *clkevt)
  95 {
  96         struct sun5i_timer *ce = clkevt_to_sun5i_timer(clkevt);
  97
  98         sun5i_clkevt_time_stop(ce, 0);
  99         return 0;
 100 }
 101
 102 static int sun5i_clkevt_set_oneshot(struct clock_event_device *clkevt)
 103 {
 104         struct sun5i_timer *ce = clkevt_to_sun5i_timer(clkevt);
 105
 106         sun5i_clkevt_time_stop(ce, 0);
 107         sun5i_clkevt_time_start(ce, 0, false);
 108         return 0;
 109 }
 110
 111 static int sun5i_clkevt_set_periodic(struct clock_event_device *clkevt)
 112 {
 113         struct sun5i_timer *ce = clkevt_to_sun5i_timer(clkevt);
 114
 115         sun5i_clkevt_time_stop(ce, 0);
 116         sun5i_clkevt_time_setup(ce, 0, ce->ticks_per_jiffy);
 117         sun5i_clkevt_time_start(ce, 0, true);
 118         return 0;
 119 }
 120
 121 static int sun5i_clkevt_next_event(unsigned long evt,
 122                                    struct clock_event_device *clkevt)
 123 {
 124         struct sun5i_timer *ce = clkevt_to_sun5i_timer(clkevt);
 125
 126         sun5i_clkevt_time_stop(ce, 0);
 127         sun5i_clkevt_time_setup(ce, 0, evt - TIMER_SYNC_TICKS);
 128         sun5i_clkevt_time_start(ce, 0, false);
 129
 130         return 0;
 131 }
 132
 133 static irqreturn_t sun5i_timer_interrupt(int irq, void *dev_id)
 134 {
 135         struct sun5i_timer *ce = dev_id;
 136
 137         writel(0x1, ce->base + TIMER_IRQ_ST_REG);
 138         ce->clkevt.event_handler(&ce->clkevt);
 139
 140         return IRQ_HANDLED;
 141 }
 142
 143 static u64 sun5i_clksrc_read(struct clocksource *clksrc)
 144 {
 145         struct sun5i_timer *cs = clksrc_to_sun5i_timer(clksrc);
 146
 147         return ~readl(cs->base + TIMER_CNTVAL_LO_REG(1));
 148 }
 149
 150 static int sun5i_rate_cb(struct notifier_block *nb,
 151                          unsigned long event, void *data)
 152 {
 153         struct clk_notifier_data *ndata = data;
 154         struct sun5i_timer *cs = nb_to_sun5i_timer(nb);
 155
 156         switch (event) {
 157         case PRE_RATE_CHANGE:
 158                 clocksource_unregister(&cs->clksrc);
 159                 break;
 160
 161         case POST_RATE_CHANGE:
 162                 clocksource_register_hz(&cs->clksrc, ndata->new_rate);
 163                 clockevents_update_freq(&cs->clkevt, ndata->new_rate);
 164                 cs->ticks_per_jiffy = DIV_ROUND_UP(ndata->new_rate, HZ);
 165                 break;
 166
 167         default:
 168                 break;
 169         }
 170
 171         return NOTIFY_DONE;
 172 }
 173
 174 static int __init sun5i_setup_clocksource(struct device_node *node,
 175                                           struct sun5i_timer *cs,
 176                                           unsigned long rate)
 177 {
 178         void __iomem *base = cs->base;
 179         int ret;
 180
 181         writel(~0, base + TIMER_INTVAL_LO_REG(1));
 182         writel(TIMER_CTL_ENABLE | TIMER_CTL_RELOAD,
 183                base + TIMER_CTL_REG(1));
 184
 185         cs->clksrc.name = node->name;
 186         cs->clksrc.rating = 340;
 187         cs->clksrc.read = sun5i_clksrc_read;
 188         cs->clksrc.mask = CLOCKSOURCE_MASK(32);
 189         cs->clksrc.flags = CLOCK_SOURCE_IS_CONTINUOUS;
 190
 191         ret = clocksource_register_hz(&cs->clksrc, rate);
 192         if (ret) {
 193                 pr_err("Couldn't register clock source.\n");
 194                 return ret;
 195         }
 196
 197         return 0;
 198 }
 199
 200 static int __init sun5i_setup_clockevent(struct device_node *node,
 201                                          struct sun5i_timer *ce,
 202                                          unsigned long rate, int irq)
 203 {
 204         void __iomem *base = ce->base;
 205         int ret;
 206         u32 val;
 207
 208         ce->clkevt.name = node->name;
 209         ce->clkevt.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT;
 210         ce->clkevt.set_next_event = sun5i_clkevt_next_event;
 211         ce->clkevt.set_state_shutdown = sun5i_clkevt_shutdown;
 212         ce->clkevt.set_state_periodic = sun5i_clkevt_set_periodic;
 213         ce->clkevt.set_state_oneshot = sun5i_clkevt_set_oneshot;
 214         ce->clkevt.tick_resume = sun5i_clkevt_shutdown;
 215         ce->clkevt.rating = 340;
 216         ce->clkevt.irq = irq;
 217         ce->clkevt.cpumask = cpu_possible_mask;
 218
 219         /* Enable timer0 interrupt */
 220         val = readl(base + TIMER_IRQ_EN_REG);
 221         writel(val | TIMER_IRQ_EN(0), base + TIMER_IRQ_EN_REG);
 222
 223         clockevents_config_and_register(&ce->clkevt, rate,
 224                                         TIMER_SYNC_TICKS, 0xffffffff);
 225
 226         ret = request_irq(irq, sun5i_timer_interrupt, IRQF_TIMER | IRQF_IRQPOLL,
 227                           "sun5i_timer0", ce);
 228         if (ret) {
 229                 pr_err("Unable to register interrupt\n");
 230                 return ret;
 231         }
 232
 233         return 0;
 234 }
 235
 236 static int __init sun5i_timer_init(struct device_node *node)
 237 {
 238         struct sun5i_timer *st;
 239         struct reset_control *rstc;
 240         void __iomem *timer_base;
 241         struct clk *clk;
 242         unsigned long rate;
 243         int irq, ret;
 244
 245         st = kzalloc(sizeof(*st), GFP_KERNEL);
 246         if (!st)
 247                 return -ENOMEM;
 248
 249         timer_base = of_io_request_and_map(node, 0, of_node_full_name(node));
 250         if (IS_ERR(timer_base)) {
 251                 pr_err("Can't map registers\n");
 252                 return PTR_ERR(timer_base);
 253         }
 254
 255         irq = irq_of_parse_and_map(node, 0);
 256         if (irq <= 0) {
 257                 pr_err("Can't parse IRQ\n");
 258                 return -EINVAL;
 259         }
 260
 261         clk = of_clk_get(node, 0);
 262         if (IS_ERR(clk)) {
 263                 pr_err("Can't get timer clock\n");
 264                 return PTR_ERR(clk);
 265         }
 266
 267         ret = clk_prepare_enable(clk);
 268         if (ret) {
 269                 pr_err("Couldn't enable parent clock\n");
 270                 goto err_free;
 271         }
 272
 273         rate = clk_get_rate(clk);
 274         if (!rate) {
 275                 pr_err("Couldn't get parent clock rate\n");
 276                 ret = -EINVAL;
 277                 goto err_disable_clk;
 278         }
 279
 280         st->base = timer_base;
 281         st->ticks_per_jiffy = DIV_ROUND_UP(rate, HZ);
 282         st->clk = clk;
 283         st->clk_rate_cb.notifier_call = sun5i_rate_cb;
 284         st->clk_rate_cb.next = NULL;
 285
 286         ret = clk_notifier_register(clk, &st->clk_rate_cb);
 287         if (ret) {
 288                 pr_err("Unable to register clock notifier.\n");
 289                 goto err_disable_clk;
 290         }
 291
 292         rstc = of_reset_control_get(node, NULL);
 293         if (!IS_ERR(rstc))
 294                 reset_control_deassert(rstc);
 295
 296         ret = sun5i_setup_clocksource(node, st, rate);
 297         if (ret)
 298                 goto err_remove_notifier;
 299
 300         return sun5i_setup_clockevent(node, st, rate, irq);
 301
 302 err_remove_notifier:
 303         clk_notifier_unregister(clk, &st->clk_rate_cb);
 304 err_disable_clk:
 305         clk_disable_unprepare(clk);
 306 err_free:
 307         kfree(st);
 308         return ret;
 309 }
 310 TIMER_OF_DECLARE(sun5i_a13, "allwinner,sun5i-a13-hstimer",
 311                            sun5i_timer_init);
 312 TIMER_OF_DECLARE(sun7i_a20, "allwinner,sun7i-a20-hstimer",
 313                            sun5i_timer_init);