1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright 2021 StarFive, Inc <samin.guo@starfivetech.com>
5 * THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING
6 * CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER
7 * FOR THEM TO SAVE TIME. AS A RESULT, STARFIVE SHALL NOT BE HELD LIABLE
8 * FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY
9 * CLAIMS ARISING FROM THE CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE
10 * BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION
11 * WITH THEIR PRODUCTS.
13 #ifndef STARFIVE_TIMER_H
14 #define STARFIVE_TIMER_H
16 #define NR_TIMERS TIMERS_MAX
17 #define PER_TIMER_LEN 0x40
18 #define TIMER_BASE(x) ((TIMER_##x)*PER_TIMER_LEN)
21 * JH7100 timwer TIMER_INT_STATUS:
22 * ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
23 * | Bits | 08~31 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
24 * ----------------------------------------------------------
25 * | timer(n)_int | res | 6 | 5 | 4 | Wdt | 3 | 2 | 1 | 0 |
26 * ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
28 * Software can read this register to know which interrupt is occurred.
30 #define STF_TIMER_INT_STATUS 0x00
31 #define STF_TIMER_CTL 0x04
32 #define STF_TIMER_LOAD 0x08
33 #define STF_TIMER_ENABLE 0x10
34 #define STF_TIMER_RELOAD 0x14
35 #define STF_TIMER_VALUE 0x18
36 #define STF_TIMER_INT_CLR 0x20
37 #define STF_TIMER_INT_MASK 0x24
38 #define INT_STATUS_CLR_AVA BIT(1)
53 INTMASK_ENABLE_DIS = 0,
68 INT_CLR_AVAILABLE = 0,
69 INT_CLR_NOT_AVAILABLE = 1
72 struct starfive_timer {
80 u32 wdt_lock; /* 0x3c+i*0x40 watchdog use ONLY */
81 u32 timer_base[NR_TIMERS];
84 struct starfive_clkevt {
85 struct clock_event_device evt;
99 void __iomem *intmask;
101 #endif /* STARFIVE_TIMER_H */