1 // SPDX-License-Identifier: GPL-2.0
3 * Starfive Timer driver
5 * Copyright 2021 StarFive, Inc. All rights reserved.
9 #include <linux/clocksource.h>
10 #include <linux/clockchips.h>
11 #include <linux/err.h>
12 #include <linux/kernel.h>
13 #include <linux/interrupt.h>
14 #include <linux/irq.h>
16 #include <linux/iopoll.h>
18 #include <linux/of_address.h>
19 #include <linux/of_clk.h>
20 #include <linux/of_irq.h>
21 #include <linux/sched_clock.h>
22 #include <linux/module.h>
23 #include <linux/reset.h>
24 #include "timer-starfive.h"
26 #define CLOCK_SOURCE_RATE 200
29 #define TIMEOUT_US 10000
30 #define CLOCKEVENT_RATING 300
31 #define MAX_TICKS 0xffffffff
34 struct starfive_timer __initdata jh7110_starfive_timer = {
35 .ctrl = STF_TIMER_CTL,
36 .load = STF_TIMER_LOAD,
37 .enable = STF_TIMER_ENABLE,
38 .reload = STF_TIMER_RELOAD,
39 .value = STF_TIMER_VALUE,
40 .intclr = STF_TIMER_INT_CLR,
41 .intmask = STF_TIMER_INT_MASK,
42 .timer_base = {TIMER_BASE(0), TIMER_BASE(1), TIMER_BASE(2),
43 TIMER_BASE(3), TIMER_BASE(4), TIMER_BASE(5),
44 TIMER_BASE(6), TIMER_BASE(7)},
47 struct starfive_timer_misc_count sfcmisc = {
49 .flg_init_clk = false,
52 static inline struct starfive_clkevt *
53 to_starfive_clkevt(struct clock_event_device *evt)
55 return container_of(evt, struct starfive_clkevt, evt);
58 static inline struct starfive_clkevt *
59 to_starfive_clksrc(struct clocksource *cs)
61 return container_of(cs, struct starfive_clkevt, cs);
64 static inline void timer_set_mod(struct starfive_clkevt *clkevt, int mod)
66 writel(mod, clkevt->ctrl);
70 * After disable timer, then enable, the timer will start
71 * from the reload count value(0x08[31:0]).
73 static inline void timer_int_enable(struct starfive_clkevt *clkevt)
75 writel(INTMASK_ENABLE_DIS, clkevt->intmask);
78 static inline void timer_int_disable(struct starfive_clkevt *clkevt)
80 writel(INTMASK_ENABLE, clkevt->intmask);
83 static inline void timer_int_clear(struct starfive_clkevt *clkevt)
85 /* waiting interrupt can be to clearing */
89 value = readl(clkevt->intclr);
90 ret = readl_poll_timeout_atomic(clkevt->intclr, value,
91 !(value & INT_STATUS_CLR_AVA), DELAY_US, TIMEOUT_US);
93 writel(1, clkevt->intclr);
97 * The initial value to be loaded into the
98 * counter and is also used as the reload value.
100 static inline void timer_set_val(struct starfive_clkevt *clkevt, u32 val)
102 writel(val, clkevt->load);
105 static inline u32 timer_get_val(struct starfive_clkevt *clkevt)
107 return readl(clkevt->value);
110 static inline u32 timer_get_load_val(struct starfive_clkevt *clkevt)
112 return readl(clkevt->load);
116 * Write RELOAD register to reload preset value to counter.
117 * (Write 0 and write 1 are both ok)
120 timer_set_reload(struct starfive_clkevt *clkevt)
122 writel(1, clkevt->reload);
125 static inline void timer_enable(struct starfive_clkevt *clkevt)
127 writel(TIMER_ENA, clkevt->enable);
130 static inline void timer_disable(struct starfive_clkevt *clkevt)
132 writel(TIMER_ENA_DIS, clkevt->enable);
135 static void timer_shutdown(struct starfive_clkevt *clkevt)
137 timer_int_disable(clkevt);
138 timer_disable(clkevt);
141 #ifdef CONFIG_PM_SLEEP
143 static void starfive_timer_suspend(struct clocksource *cs)
145 struct starfive_clkevt *clkevt;
148 clkevt = to_starfive_clksrc(cs);
150 clkevt->reload_val = timer_get_load_val(clkevt);
151 timer_disable(clkevt);
152 timer_int_disable(clkevt);
154 clkevt->misc->clk_count--;
156 if (clkevt->misc->clk_count < 1)
157 pclk = of_clk_get_by_name(clkevt->device_node, "apb_clk");
159 if (!clkevt->misc->flg_init_clk) {
160 const char *name = NULL;
162 of_property_read_string_index(clkevt->device_node,
163 "clock-names", clkevt->index, &name);
164 clkevt->clk = of_clk_get_by_name(clkevt->device_node, name);
165 clk_prepare_enable(clkevt->clk);
166 clk_disable_unprepare(clkevt->clk);
168 if (clkevt->misc->clk_count < 1) {
169 clk_prepare_enable(pclk);
170 clk_disable_unprepare(pclk);
173 clk_disable_unprepare(clkevt->clk);
175 if (clkevt->misc->clk_count < 1)
176 clk_disable_unprepare(pclk);
180 static void starfive_timer_resume(struct clocksource *cs)
182 struct starfive_clkevt *clkevt;
184 clkevt = to_starfive_clksrc(cs);
186 clkevt->misc->flg_init_clk = true;
188 if (clkevt->misc->clk_count < 1) {
191 pclk = of_clk_get_by_name(clkevt->device_node, "apb_clk");
192 clk_prepare_enable(pclk);
194 clk_prepare_enable(clkevt->clk);
195 clkevt->misc->clk_count++;
197 timer_set_val(clkevt, clkevt->reload_val);
198 timer_set_reload(clkevt);
199 timer_int_enable(clkevt);
200 timer_enable(clkevt);
203 #endif /*CONIFG PM SLEEP*/
205 static int starfive_timer_shutdown(struct clock_event_device *evt)
207 struct starfive_clkevt *clkevt;
209 clkevt = to_starfive_clkevt(evt);
210 timer_shutdown(clkevt);
216 starfive_get_clock_rate(struct starfive_clkevt *clkevt, struct device_node *np)
222 clkevt->rate = clk_get_rate(clkevt->clk);
223 if (clkevt->rate > 0) {
224 pr_debug("clk_get_rate clkevt->rate: %lld\n",
230 /* Next we try to get clock-frequency from dts.*/
231 ret = of_property_read_u32(np, "clock-frequency", &rate);
233 pr_debug("Timer: try get clock-frequency:%d MHz\n", rate);
234 clkevt->rate = (u64)rate;
237 pr_err("Timer: get rate failed, need clock-frequency define in dts.\n");
242 static u64 starfive_clocksource_mmio_readl_down(struct clocksource *c)
244 return ~(u64)readl_relaxed(to_starfive_clksrc(c)->value) & c->mask;
247 static int starfive_clocksource_init(struct starfive_clkevt *clkevt,
248 const char *name, struct device_node *np)
251 if (VALID_BITS > 64 || VALID_BITS < 16)
254 clkevt->cs.name = name;
255 clkevt->cs.rating = CLOCK_SOURCE_RATE;
256 clkevt->cs.read = starfive_clocksource_mmio_readl_down;
257 clkevt->cs.mask = CLOCKSOURCE_MASK(VALID_BITS);
258 clkevt->cs.flags = CLOCK_SOURCE_IS_CONTINUOUS;
259 clkevt->cs.suspend = starfive_timer_suspend;
260 clkevt->cs.resume = starfive_timer_resume;
262 timer_set_mod(clkevt, MOD_CONTIN);
263 timer_set_val(clkevt, MAX_TICKS); /* val = rate --> 1s */
264 timer_int_disable(clkevt);
265 timer_int_clear(clkevt);
266 timer_int_enable(clkevt);
267 timer_enable(clkevt);
269 clocksource_register_hz(&clkevt->cs, clkevt->rate);
275 * IRQ handler for the timer
277 static irqreturn_t starfive_timer_interrupt(int irq, void *priv)
279 struct clock_event_device *evt = (struct clock_event_device *)priv;
280 struct starfive_clkevt *clkevt = to_starfive_clkevt(evt);
282 timer_int_clear(clkevt);
283 if (evt->event_handler)
284 evt->event_handler(evt);
289 static int starfive_timer_set_periodic(struct clock_event_device *evt)
291 struct starfive_clkevt *clkevt;
293 clkevt = to_starfive_clkevt(evt);
295 timer_disable(clkevt);
296 timer_set_mod(clkevt, MOD_CONTIN);
297 timer_set_val(clkevt, clkevt->periodic);
298 timer_int_disable(clkevt);
299 timer_int_clear(clkevt);
300 timer_int_enable(clkevt);
301 timer_enable(clkevt);
306 static int starfive_timer_set_oneshot(struct clock_event_device *evt)
308 struct starfive_clkevt *clkevt;
310 clkevt = to_starfive_clkevt(evt);
312 timer_disable(clkevt);
313 timer_set_mod(clkevt, MOD_SINGLE);
314 timer_set_val(clkevt, MAX_TICKS);
315 timer_int_disable(clkevt);
316 timer_int_clear(clkevt);
317 timer_int_enable(clkevt);
318 timer_enable(clkevt);
323 static int starfive_timer_set_next_event(unsigned long next,
324 struct clock_event_device *evt)
326 struct starfive_clkevt *clkevt;
328 clkevt = to_starfive_clkevt(evt);
330 timer_disable(clkevt);
331 timer_set_mod(clkevt, MOD_SINGLE);
332 timer_set_val(clkevt, next);
333 timer_enable(clkevt);
338 static void starfive_set_clockevent(struct clock_event_device *evt)
340 evt->features = CLOCK_EVT_FEAT_PERIODIC |
341 CLOCK_EVT_FEAT_ONESHOT |
342 CLOCK_EVT_FEAT_DYNIRQ;
343 evt->set_state_shutdown = starfive_timer_shutdown;
344 evt->set_state_periodic = starfive_timer_set_periodic;
345 evt->set_state_oneshot = starfive_timer_set_oneshot;
346 evt->set_state_oneshot_stopped = starfive_timer_shutdown;
347 evt->set_next_event = starfive_timer_set_next_event;
348 evt->rating = CLOCKEVENT_RATING;
351 static int starfive_clockevents_register(struct starfive_clkevt *clkevt, unsigned int irq,
352 struct device_node *np, const char *name)
356 ret = starfive_get_clock_rate(clkevt, np);
360 clkevt->periodic = DIV_ROUND_CLOSEST(clkevt->rate, HZ);
362 starfive_set_clockevent(&clkevt->evt);
363 clkevt->evt.name = name;
364 clkevt->evt.irq = irq;
365 clkevt->evt.cpumask = cpu_possible_mask;
367 ret = request_irq(irq, starfive_timer_interrupt,
368 IRQF_TIMER | IRQF_IRQPOLL, name, &clkevt->evt);
370 pr_err("%s: request_irq failed\n", name);
372 clockevents_config_and_register(&clkevt->evt, clkevt->rate,
373 MIN_TICKS, MAX_TICKS);
378 static void __init starfive_clkevt_init(struct starfive_timer *timer,
379 struct starfive_clkevt *clkevt,
380 void __iomem *base, int index)
382 void __iomem *timer_base;
384 timer_base = base + timer->timer_base[index];
385 clkevt->base = timer_base;
386 clkevt->ctrl = timer_base + timer->ctrl;
387 clkevt->load = timer_base + timer->load;
388 clkevt->enable = timer_base + timer->enable;
389 clkevt->reload = timer_base + timer->reload;
390 clkevt->value = timer_base + timer->value;
391 clkevt->intclr = timer_base + timer->intclr;
392 clkevt->intmask = timer_base + timer->intmask;
395 static int __init do_starfive_timer_of_init(struct device_node *np,
396 struct starfive_timer *timer)
398 int index, count, irq, ret = -EINVAL;
399 const char *name = NULL;
402 struct reset_control *prst;
403 struct reset_control *rst;
404 struct starfive_clkevt *clkevt[4];
407 base = of_iomap(np, 0);
411 if (!of_device_is_available(np)) {
416 pclk = of_clk_get_by_name(np, "apb_clk");
418 if (clk_prepare_enable(pclk))
419 pr_warn("pclk for %pOFn is present,"
420 "but could not be activated\n", np);
422 prst = of_reset_control_get(np, "apb_rst");
424 reset_control_assert(prst);
425 reset_control_deassert(prst);
428 count = of_irq_count(np);
429 if (count > NR_TIMERS || count <= 0) {
434 for (index = 0; index < count; index++) {
435 /* one of timer is wdog-timer, skip...*/
436 of_property_read_string_index(np, "clock-names", index, &name);
437 if (strncmp(name, "timer", strlen("timer")))
440 clkevt[index] = kzalloc(sizeof(*clkevt[index]), GFP_KERNEL);
441 if (!clkevt[index]) {
445 clkevt[index]->device_node = np;
446 clkevt[index]->index = index;
447 clkevt[index]->misc = &sfcmisc;
449 starfive_clkevt_init(timer, clkevt[index], base, index);
451 /* Ensure timers are disabled */
452 timer_disable(clkevt[index]);
454 clk = of_clk_get_by_name(np, name);
456 clkevt[index]->clk = clk;
458 if (clk_prepare_enable(clk)) {
459 pr_warn("clk for %pOFn is present,"
460 "but could not be activated\n", np);
464 clkevt[index]->misc->clk_count++;
466 rst = of_reset_control_get(np, name);
468 reset_control_assert(rst);
469 reset_control_deassert(rst);
472 irq = irq_of_parse_and_map(np, index);
478 snprintf(clkevt[index]->name, sizeof(clkevt[index]->name), "%s.ch%d",
479 np->full_name, index);
481 ret = starfive_clockevents_register(clkevt[index], irq, np, clkevt[index]->name);
483 pr_err("%s: init clockevents failed.\n", clkevt[index]->name);
486 clkevt[index]->irq = irq;
488 ret = starfive_clocksource_init(clkevt[index], clkevt[index]->name, np);
499 free_irq(clkevt[index]->irq, &clkevt[index]->evt);
502 reset_control_assert(rst);
503 reset_control_put(rst);
505 if (!clkevt[index]->clk) {
506 clk_disable_unprepare(clkevt[index]->clk);
507 clk_put(clkevt[index]->clk);
509 kfree(clkevt[index]);
514 clk_disable_unprepare(pclk);
522 static int __init starfive_timer_of_init(struct device_node *np)
524 return do_starfive_timer_of_init(np, &jh7110_starfive_timer);
526 TIMER_OF_DECLARE(starfive_timer, "starfive,jh7110-timers", starfive_timer_of_init);
528 MODULE_AUTHOR("xingyu.wu <xingyu.wu@starfivetech.com>");
529 MODULE_AUTHOR("samin.guo <samin.guo@starfivetech.com>");
530 MODULE_DESCRIPTION("StarFive Timer Device Driver");
531 MODULE_LICENSE("GPL v2");