1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * linux/drivers/clocksource/timer-sp.c
5 * Copyright (C) 1999 - 2003 ARM Limited
6 * Copyright (C) 2000 Deep Blue Solutions Ltd
9 #include <linux/clocksource.h>
10 #include <linux/clockchips.h>
11 #include <linux/err.h>
12 #include <linux/interrupt.h>
13 #include <linux/irq.h>
16 #include <linux/of_address.h>
17 #include <linux/of_clk.h>
18 #include <linux/of_irq.h>
19 #include <linux/sched_clock.h>
21 #include <clocksource/timer-sp804.h>
25 static long __init sp804_get_clock_rate(struct clk *clk)
30 err = clk_prepare(clk);
32 pr_err("sp804: clock failed to prepare: %d\n", err);
37 err = clk_enable(clk);
39 pr_err("sp804: clock failed to enable: %d\n", err);
45 rate = clk_get_rate(clk);
47 pr_err("sp804: clock failed to get rate: %ld\n", rate);
56 static void __iomem *sched_clock_base;
58 static u64 notrace sp804_read(void)
60 return ~readl_relaxed(sched_clock_base + TIMER_VALUE);
63 void __init sp804_timer_disable(void __iomem *base)
65 writel(0, base + TIMER_CTRL);
68 int __init __sp804_clocksource_and_sched_clock_init(void __iomem *base,
76 clk = clk_get_sys("sp804", name);
78 pr_err("sp804: clock not found: %d\n",
84 rate = sp804_get_clock_rate(clk);
88 /* setup timer 0 as free-running clocksource */
89 writel(0, base + TIMER_CTRL);
90 writel(0xffffffff, base + TIMER_LOAD);
91 writel(0xffffffff, base + TIMER_VALUE);
92 writel(TIMER_CTRL_32BIT | TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC,
95 clocksource_mmio_init(base + TIMER_VALUE, name,
96 rate, 200, 32, clocksource_mmio_readl_down);
98 if (use_sched_clock) {
99 sched_clock_base = base;
100 sched_clock_register(sp804_read, 32, rate);
107 static void __iomem *clkevt_base;
108 static unsigned long clkevt_reload;
111 * IRQ handler for the timer
113 static irqreturn_t sp804_timer_interrupt(int irq, void *dev_id)
115 struct clock_event_device *evt = dev_id;
117 /* clear the interrupt */
118 writel(1, clkevt_base + TIMER_INTCLR);
120 evt->event_handler(evt);
125 static inline void timer_shutdown(struct clock_event_device *evt)
127 writel(0, clkevt_base + TIMER_CTRL);
130 static int sp804_shutdown(struct clock_event_device *evt)
136 static int sp804_set_periodic(struct clock_event_device *evt)
138 unsigned long ctrl = TIMER_CTRL_32BIT | TIMER_CTRL_IE |
139 TIMER_CTRL_PERIODIC | TIMER_CTRL_ENABLE;
142 writel(clkevt_reload, clkevt_base + TIMER_LOAD);
143 writel(ctrl, clkevt_base + TIMER_CTRL);
147 static int sp804_set_next_event(unsigned long next,
148 struct clock_event_device *evt)
150 unsigned long ctrl = TIMER_CTRL_32BIT | TIMER_CTRL_IE |
151 TIMER_CTRL_ONESHOT | TIMER_CTRL_ENABLE;
153 writel(next, clkevt_base + TIMER_LOAD);
154 writel(ctrl, clkevt_base + TIMER_CTRL);
159 static struct clock_event_device sp804_clockevent = {
160 .features = CLOCK_EVT_FEAT_PERIODIC |
161 CLOCK_EVT_FEAT_ONESHOT |
162 CLOCK_EVT_FEAT_DYNIRQ,
163 .set_state_shutdown = sp804_shutdown,
164 .set_state_periodic = sp804_set_periodic,
165 .set_state_oneshot = sp804_shutdown,
166 .tick_resume = sp804_shutdown,
167 .set_next_event = sp804_set_next_event,
171 static struct irqaction sp804_timer_irq = {
173 .flags = IRQF_TIMER | IRQF_IRQPOLL,
174 .handler = sp804_timer_interrupt,
175 .dev_id = &sp804_clockevent,
178 int __init __sp804_clockevents_init(void __iomem *base, unsigned int irq, struct clk *clk, const char *name)
180 struct clock_event_device *evt = &sp804_clockevent;
184 clk = clk_get_sys("sp804", name);
186 pr_err("sp804: %s clock not found: %d\n", name,
191 rate = sp804_get_clock_rate(clk);
196 clkevt_reload = DIV_ROUND_CLOSEST(rate, HZ);
199 evt->cpumask = cpu_possible_mask;
201 writel(0, base + TIMER_CTRL);
203 setup_irq(irq, &sp804_timer_irq);
204 clockevents_config_and_register(evt, rate, 0xf, 0xffffffff);
209 static int __init sp804_of_init(struct device_node *np)
211 static bool initialized = false;
213 int irq, ret = -EINVAL;
215 struct clk *clk1, *clk2;
216 const char *name = of_get_property(np, "compatible", NULL);
218 base = of_iomap(np, 0);
222 /* Ensure timers are disabled */
223 writel(0, base + TIMER_CTRL);
224 writel(0, base + TIMER_2_BASE + TIMER_CTRL);
226 if (initialized || !of_device_is_available(np)) {
231 clk1 = of_clk_get(np, 0);
235 /* Get the 2nd clock if the timer has 3 timer clocks */
236 if (of_clk_get_parent_count(np) == 3) {
237 clk2 = of_clk_get(np, 1);
239 pr_err("sp804: %pOFn clock not found: %d\n", np,
246 irq = irq_of_parse_and_map(np, 0);
250 of_property_read_u32(np, "arm,sp804-has-irq", &irq_num);
253 ret = __sp804_clockevents_init(base + TIMER_2_BASE, irq, clk2, name);
257 ret = __sp804_clocksource_and_sched_clock_init(base, name, clk1, 1);
262 ret = __sp804_clockevents_init(base, irq, clk1 , name);
266 ret =__sp804_clocksource_and_sched_clock_init(base + TIMER_2_BASE,
278 TIMER_OF_DECLARE(sp804, "arm,sp804", sp804_of_init);
280 static int __init integrator_cp_of_init(struct device_node *np)
282 static int init_count = 0;
284 int irq, ret = -EINVAL;
285 const char *name = of_get_property(np, "compatible", NULL);
288 base = of_iomap(np, 0);
290 pr_err("Failed to iomap\n");
294 clk = of_clk_get(np, 0);
296 pr_err("Failed to get clock\n");
300 /* Ensure timer is disabled */
301 writel(0, base + TIMER_CTRL);
303 if (init_count == 2 || !of_device_is_available(np))
307 ret = __sp804_clocksource_and_sched_clock_init(base, name, clk, 0);
311 irq = irq_of_parse_and_map(np, 0);
315 ret = __sp804_clockevents_init(base, irq, clk, name);
326 TIMER_OF_DECLARE(intcp, "arm,integrator-cp-timer", integrator_cp_of_init);