drivers/clocksource/timer-riscv.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (C) 2012 Regents of the University of California
   4  * Copyright (C) 2017 SiFive
   5  *
   6  * All RISC-V systems have a timer attached to every hart.  These timers can
   7  * either be read from the "time" and "timeh" CSRs, and can use the SBI to
   8  * setup events, or directly accessed using MMIO registers.
   9  */
  10
  11 #define pr_fmt(fmt) "riscv-timer: " fmt
  12
  13 #include <linux/acpi.h>
  14 #include <linux/clocksource.h>
  15 #include <linux/clockchips.h>
  16 #include <linux/cpu.h>
  17 #include <linux/delay.h>
  18 #include <linux/irq.h>
  19 #include <linux/irqdomain.h>
  20 #include <linux/module.h>
  21 #include <linux/sched_clock.h>
  22 #include <linux/io-64-nonatomic-lo-hi.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/of_irq.h>
  25 #include <clocksource/timer-riscv.h>
  26 #include <asm/smp.h>
  27 #include <asm/hwcap.h>
  28 #include <asm/sbi.h>
  29 #include <asm/timex.h>
  30
  31 static DEFINE_STATIC_KEY_FALSE(riscv_sstc_available);
  32 static bool riscv_timer_cannot_wake_cpu;
  33
  34 static int riscv_clock_next_event(unsigned long delta,
  35                 struct clock_event_device *ce)
  36 {
  37         u64 next_tval = get_cycles64() + delta;
  38
  39         csr_set(CSR_IE, IE_TIE);
  40         if (static_branch_likely(&riscv_sstc_available)) {
  41 #if defined(CONFIG_32BIT)
  42                 csr_write(CSR_STIMECMP, next_tval & 0xFFFFFFFF);
  43                 csr_write(CSR_STIMECMPH, next_tval >> 32);
  44 #else
  45                 csr_write(CSR_STIMECMP, next_tval);
  46 #endif
  47         } else
  48                 sbi_set_timer(next_tval);
  49
  50         return 0;
  51 }
  52
  53 static unsigned int riscv_clock_event_irq;
  54 static DEFINE_PER_CPU(struct clock_event_device, riscv_clock_event) = {
  55         .name                   = "riscv_timer_clockevent",
  56         .features               = CLOCK_EVT_FEAT_ONESHOT,
  57         .rating                 = 100,
  58         .set_next_event         = riscv_clock_next_event,
  59 };
  60
  61 /*
  62  * It is guaranteed that all the timers across all the harts are synchronized
  63  * within one tick of each other, so while this could technically go
  64  * backwards when hopping between CPUs, practically it won't happen.
  65  */
  66 static unsigned long long riscv_clocksource_rdtime(struct clocksource *cs)
  67 {
  68         return get_cycles64();
  69 }
  70
  71 static u64 notrace riscv_sched_clock(void)
  72 {
  73         return get_cycles64();
  74 }
  75
  76 static struct clocksource riscv_clocksource = {
  77         .name           = "riscv_clocksource",
  78         .rating         = 400,
  79         .mask           = CLOCKSOURCE_MASK(64),
  80         .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
  81         .read           = riscv_clocksource_rdtime,
  82 #if IS_ENABLED(CONFIG_GENERIC_GETTIMEOFDAY)
  83         .vdso_clock_mode = VDSO_CLOCKMODE_ARCHTIMER,
  84 #else
  85         .vdso_clock_mode = VDSO_CLOCKMODE_NONE,
  86 #endif
  87 };
  88
  89 static int riscv_timer_starting_cpu(unsigned int cpu)
  90 {
  91         struct clock_event_device *ce = per_cpu_ptr(&riscv_clock_event, cpu);
  92
  93         ce->cpumask = cpumask_of(cpu);
  94         ce->irq = riscv_clock_event_irq;
  95         if (riscv_timer_cannot_wake_cpu)
  96                 ce->features |= CLOCK_EVT_FEAT_C3STOP;
  97         clockevents_config_and_register(ce, riscv_timebase, 100, 0x7fffffff);
  98
  99         enable_percpu_irq(riscv_clock_event_irq,
 100                           irq_get_trigger_type(riscv_clock_event_irq));
 101         return 0;
 102 }
 103
 104 static int riscv_timer_dying_cpu(unsigned int cpu)
 105 {
 106         disable_percpu_irq(riscv_clock_event_irq);
 107         return 0;
 108 }
 109
 110 void riscv_cs_get_mult_shift(u32 *mult, u32 *shift)
 111 {
 112         *mult = riscv_clocksource.mult;
 113         *shift = riscv_clocksource.shift;
 114 }
 115 EXPORT_SYMBOL_GPL(riscv_cs_get_mult_shift);
 116
 117 /* called directly from the low-level interrupt handler */
 118 static irqreturn_t riscv_timer_interrupt(int irq, void *dev_id)
 119 {
 120         struct clock_event_device *evdev = this_cpu_ptr(&riscv_clock_event);
 121
 122         csr_clear(CSR_IE, IE_TIE);
 123         evdev->event_handler(evdev);
 124
 125         return IRQ_HANDLED;
 126 }
 127
 128 static int __init riscv_timer_init_common(void)
 129 {
 130         int error;
 131         struct irq_domain *domain;
 132         struct fwnode_handle *intc_fwnode = riscv_get_intc_hwnode();
 133
 134         domain = irq_find_matching_fwnode(intc_fwnode, DOMAIN_BUS_ANY);
 135         if (!domain) {
 136                 pr_err("Failed to find irq_domain for INTC node [%pfwP]\n",
 137                        intc_fwnode);
 138                 return -ENODEV;
 139         }
 140
 141         riscv_clock_event_irq = irq_create_mapping(domain, RV_IRQ_TIMER);
 142         if (!riscv_clock_event_irq) {
 143                 pr_err("Failed to map timer interrupt for node [%pfwP]\n", intc_fwnode);
 144                 return -ENODEV;
 145         }
 146
 147         error = clocksource_register_hz(&riscv_clocksource, riscv_timebase);
 148         if (error) {
 149                 pr_err("RISCV timer registration failed [%d]\n", error);
 150                 return error;
 151         }
 152
 153         sched_clock_register(riscv_sched_clock, 64, riscv_timebase);
 154
 155         error = request_percpu_irq(riscv_clock_event_irq,
 156                                     riscv_timer_interrupt,
 157                                     "riscv-timer", &riscv_clock_event);
 158         if (error) {
 159                 pr_err("registering percpu irq failed [%d]\n", error);
 160                 return error;
 161         }
 162
 163         if (riscv_isa_extension_available(NULL, SSTC)) {
 164                 pr_info("Timer interrupt in S-mode is available via sstc extension\n");
 165                 static_branch_enable(&riscv_sstc_available);
 166         }
 167
 168         error = cpuhp_setup_state(CPUHP_AP_RISCV_TIMER_STARTING,
 169                          "clockevents/riscv/timer:starting",
 170                          riscv_timer_starting_cpu, riscv_timer_dying_cpu);
 171         if (error)
 172                 pr_err("cpu hp setup state failed for RISCV timer [%d]\n",
 173                        error);
 174
 175         return error;
 176 }
 177
 178 static int __init riscv_timer_init_dt(struct device_node *n)
 179 {
 180         int cpuid, error;
 181         unsigned long hartid;
 182         struct device_node *child;
 183
 184         error = riscv_of_processor_hartid(n, &hartid);
 185         if (error < 0) {
 186                 pr_warn("Invalid hartid for node [%pOF] error = [%lu]\n",
 187                         n, hartid);
 188                 return error;
 189         }
 190
 191         cpuid = riscv_hartid_to_cpuid(hartid);
 192         if (cpuid < 0) {
 193                 pr_warn("Invalid cpuid for hartid [%lu]\n", hartid);
 194                 return cpuid;
 195         }
 196
 197         if (cpuid != smp_processor_id())
 198                 return 0;
 199
 200         child = of_find_compatible_node(NULL, NULL, "riscv,timer");
 201         if (child) {
 202                 riscv_timer_cannot_wake_cpu = of_property_read_bool(child,
 203                                         "riscv,timer-cannot-wake-cpu");
 204                 of_node_put(child);
 205         }
 206
 207         return riscv_timer_init_common();
 208 }
 209
 210 TIMER_OF_DECLARE(riscv_timer, "riscv", riscv_timer_init_dt);
 211
 212 #ifdef CONFIG_ACPI
 213 static int __init riscv_timer_acpi_init(struct acpi_table_header *table)
 214 {
 215         return riscv_timer_init_common();
 216 }
 217
 218 TIMER_ACPI_DECLARE(aclint_mtimer, ACPI_SIG_RHCT, riscv_timer_acpi_init);
 219
 220 #endif