1 // SPDX-License-Identifier: GPL-2.0+
3 // Copyright 2016 Freescale Semiconductor, Inc.
7 #include <linux/clockchips.h>
8 #include <linux/clocksource.h>
9 #include <linux/delay.h>
10 #include <linux/interrupt.h>
11 #include <linux/of_address.h>
12 #include <linux/of_irq.h>
13 #include <linux/sched_clock.h>
16 #define TPM_PARAM_WIDTH_SHIFT 16
17 #define TPM_PARAM_WIDTH_MASK (0xff << 16)
19 #define TPM_SC_CMOD_INC_PER_CNT (0x1 << 3)
20 #define TPM_SC_CMOD_DIV_DEFAULT 0x3
21 #define TPM_SC_CMOD_DIV_MAX 0x7
22 #define TPM_SC_TOF_MASK (0x1 << 7)
25 #define TPM_STATUS 0x1c
26 #define TPM_STATUS_CH0F BIT(0)
28 #define TPM_C0SC_CHIE BIT(6)
29 #define TPM_C0SC_MODE_SHIFT 2
30 #define TPM_C0SC_MODE_MASK 0x3c
31 #define TPM_C0SC_MODE_SW_COMPARE 0x4
32 #define TPM_C0SC_CHF_MASK (0x1 << 7)
35 static int counter_width;
37 static void __iomem *timer_base;
38 static struct clock_event_device clockevent_tpm;
40 static inline void tpm_timer_disable(void)
45 val = readl(timer_base + TPM_C0SC);
46 val &= ~(TPM_C0SC_MODE_MASK | TPM_C0SC_CHIE);
47 writel(val, timer_base + TPM_C0SC);
50 static inline void tpm_timer_enable(void)
54 /* channel enabled in sw compare mode */
55 val = readl(timer_base + TPM_C0SC);
56 val |= (TPM_C0SC_MODE_SW_COMPARE << TPM_C0SC_MODE_SHIFT) |
58 writel(val, timer_base + TPM_C0SC);
61 static inline void tpm_irq_acknowledge(void)
63 writel(TPM_STATUS_CH0F, timer_base + TPM_STATUS);
66 static struct delay_timer tpm_delay_timer;
68 static inline unsigned long tpm_read_counter(void)
70 return readl(timer_base + TPM_CNT);
73 static unsigned long tpm_read_current_timer(void)
75 return tpm_read_counter();
78 static u64 notrace tpm_read_sched_clock(void)
80 return tpm_read_counter();
83 static int __init tpm_clocksource_init(unsigned long rate)
85 tpm_delay_timer.read_current_timer = &tpm_read_current_timer;
86 tpm_delay_timer.freq = rate;
87 register_current_timer_delay(&tpm_delay_timer);
89 sched_clock_register(tpm_read_sched_clock, counter_width, rate);
91 return clocksource_mmio_init(timer_base + TPM_CNT, "imx-tpm",
92 rate, rating, counter_width,
93 clocksource_mmio_readl_up);
96 static int tpm_set_next_event(unsigned long delta,
97 struct clock_event_device *evt)
99 unsigned long next, now;
101 next = tpm_read_counter();
103 writel(next, timer_base + TPM_C0V);
104 now = tpm_read_counter();
107 * NOTE: We observed in a very small probability, the bus fabric
108 * contention between GPU and A7 may results a few cycles delay
109 * of writing CNT registers which may cause the min_delta event got
110 * missed, so we need add a ETIME check here in case it happened.
112 return (int)(next - now) <= 0 ? -ETIME : 0;
115 static int tpm_set_state_oneshot(struct clock_event_device *evt)
122 static int tpm_set_state_shutdown(struct clock_event_device *evt)
129 static irqreturn_t tpm_timer_interrupt(int irq, void *dev_id)
131 struct clock_event_device *evt = dev_id;
133 tpm_irq_acknowledge();
135 evt->event_handler(evt);
140 static struct clock_event_device clockevent_tpm = {
141 .name = "i.MX7ULP TPM Timer",
142 .features = CLOCK_EVT_FEAT_ONESHOT,
143 .set_state_oneshot = tpm_set_state_oneshot,
144 .set_next_event = tpm_set_next_event,
145 .set_state_shutdown = tpm_set_state_shutdown,
148 static int __init tpm_clockevent_init(unsigned long rate, int irq)
152 ret = request_irq(irq, tpm_timer_interrupt, IRQF_TIMER | IRQF_IRQPOLL,
153 "i.MX7ULP TPM Timer", &clockevent_tpm);
155 clockevent_tpm.rating = rating;
156 clockevent_tpm.cpumask = cpumask_of(0);
157 clockevent_tpm.irq = irq;
158 clockevents_config_and_register(&clockevent_tpm, rate, 300,
159 GENMASK(counter_width - 1, 1));
164 static int __init tpm_timer_init(struct device_node *np)
166 struct clk *ipg, *per;
170 timer_base = of_iomap(np, 0);
172 pr_err("tpm: failed to get base address\n");
176 irq = irq_of_parse_and_map(np, 0);
178 pr_err("tpm: failed to get irq\n");
183 ipg = of_clk_get_by_name(np, "ipg");
184 per = of_clk_get_by_name(np, "per");
185 if (IS_ERR(ipg) || IS_ERR(per)) {
186 pr_err("tpm: failed to get ipg or per clk\n");
191 /* enable clk before accessing registers */
192 ret = clk_prepare_enable(ipg);
194 pr_err("tpm: ipg clock enable failed (%d)\n", ret);
198 ret = clk_prepare_enable(per);
200 pr_err("tpm: per clock enable failed (%d)\n", ret);
201 goto err_per_clk_enable;
204 counter_width = (readl(timer_base + TPM_PARAM) & TPM_PARAM_WIDTH_MASK)
205 >> TPM_PARAM_WIDTH_SHIFT;
206 /* use rating 200 for 32-bit counter and 150 for 16-bit counter */
207 rating = counter_width == 0x20 ? 200 : 150;
210 * Initialize tpm module to a known state
211 * 1) Counter disabled
212 * 2) TPM counter operates in up counting mode
213 * 3) Timer Overflow Interrupt disabled
214 * 4) Channel0 disabled
215 * 5) DMA transfers disabled
217 /* make sure counter is disabled */
218 writel(0, timer_base + TPM_SC);
220 writel(TPM_SC_TOF_MASK, timer_base + TPM_SC);
221 writel(0, timer_base + TPM_CNT);
223 writel(TPM_C0SC_CHF_MASK, timer_base + TPM_C0SC);
227 * div 8 for 32-bit counter and div 128 for 16-bit counter
229 writel(TPM_SC_CMOD_INC_PER_CNT |
230 (counter_width == 0x20 ?
231 TPM_SC_CMOD_DIV_DEFAULT : TPM_SC_CMOD_DIV_MAX),
232 timer_base + TPM_SC);
234 /* set MOD register to maximum for free running mode */
235 writel(GENMASK(counter_width - 1, 0), timer_base + TPM_MOD);
237 rate = clk_get_rate(per) >> 3;
238 ret = tpm_clocksource_init(rate);
240 goto err_per_clk_enable;
242 ret = tpm_clockevent_init(rate, irq);
244 goto err_per_clk_enable;
249 clk_disable_unprepare(ipg);
257 TIMER_OF_DECLARE(imx7ulp, "fsl,imx7ulp-tpm", tpm_timer_init);