drivers/clocksource/timer-cadence-ttc.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * This file contains driver for the Cadence Triple Timer Counter Rev 06
   4  *
   5  *  Copyright (C) 2011-2013 Xilinx
   6  *
   7  * based on arch/mips/kernel/time.c timer driver
   8  */
   9
  10 #include <linux/clk.h>
  11 #include <linux/interrupt.h>
  12 #include <linux/clockchips.h>
  13 #include <linux/clocksource.h>
  14 #include <linux/of_address.h>
  15 #include <linux/of_irq.h>
  16 #include <linux/slab.h>
  17 #include <linux/sched_clock.h>
  18 #include <linux/module.h>
  19 #include <linux/of_platform.h>
  20
  21 /*
  22  * This driver configures the 2 16/32-bit count-up timers as follows:
  23  *
  24  * T1: Timer 1, clocksource for generic timekeeping
  25  * T2: Timer 2, clockevent source for hrtimers
  26  * T3: Timer 3, <unused>
  27  *
  28  * The input frequency to the timer module for emulation is 2.5MHz which is
  29  * common to all the timer channels (T1, T2, and T3). With a pre-scaler of 32,
  30  * the timers are clocked at 78.125KHz (12.8 us resolution).
  31
  32  * The input frequency to the timer module in silicon is configurable and
  33  * obtained from device tree. The pre-scaler of 32 is used.
  34  */
  35
  36 /*
  37  * Timer Register Offset Definitions of Timer 1, Increment base address by 4
  38  * and use same offsets for Timer 2
  39  */
  40 #define TTC_CLK_CNTRL_OFFSET            0x00 /* Clock Control Reg, RW */
  41 #define TTC_CNT_CNTRL_OFFSET            0x0C /* Counter Control Reg, RW */
  42 #define TTC_COUNT_VAL_OFFSET            0x18 /* Counter Value Reg, RO */
  43 #define TTC_INTR_VAL_OFFSET             0x24 /* Interval Count Reg, RW */
  44 #define TTC_ISR_OFFSET          0x54 /* Interrupt Status Reg, RO */
  45 #define TTC_IER_OFFSET          0x60 /* Interrupt Enable Reg, RW */
  46
  47 #define TTC_CNT_CNTRL_DISABLE_MASK      0x1
  48
  49 #define TTC_CLK_CNTRL_CSRC_MASK         (1 << 5)        /* clock source */
  50 #define TTC_CLK_CNTRL_PSV_MASK          0x1e
  51 #define TTC_CLK_CNTRL_PSV_SHIFT         1
  52
  53 /*
  54  * Setup the timers to use pre-scaling, using a fixed value for now that will
  55  * work across most input frequency, but it may need to be more dynamic
  56  */
  57 #define PRESCALE_EXPONENT       11      /* 2 ^ PRESCALE_EXPONENT = PRESCALE */
  58 #define PRESCALE                2048    /* The exponent must match this */
  59 #define CLK_CNTRL_PRESCALE      ((PRESCALE_EXPONENT - 1) << 1)
  60 #define CLK_CNTRL_PRESCALE_EN   1
  61 #define CNT_CNTRL_RESET         (1 << 4)
  62
  63 #define MAX_F_ERR 50
  64
  65 /**
  66  * struct ttc_timer - This definition defines local timer structure
  67  *
  68  * @base_addr:  Base address of timer
  69  * @freq:       Timer input clock frequency
  70  * @clk:        Associated clock source
  71  * @clk_rate_change_nb  Notifier block for clock rate changes
  72  */
  73 struct ttc_timer {
  74         void __iomem *base_addr;
  75         unsigned long freq;
  76         struct clk *clk;
  77         struct notifier_block clk_rate_change_nb;
  78 };
  79
  80 #define to_ttc_timer(x) \
  81                 container_of(x, struct ttc_timer, clk_rate_change_nb)
  82
  83 struct ttc_timer_clocksource {
  84         u32                     scale_clk_ctrl_reg_old;
  85         u32                     scale_clk_ctrl_reg_new;
  86         struct ttc_timer        ttc;
  87         struct clocksource      cs;
  88 };
  89
  90 #define to_ttc_timer_clksrc(x) \
  91                 container_of(x, struct ttc_timer_clocksource, cs)
  92
  93 struct ttc_timer_clockevent {
  94         struct ttc_timer                ttc;
  95         struct clock_event_device       ce;
  96 };
  97
  98 #define to_ttc_timer_clkevent(x) \
  99                 container_of(x, struct ttc_timer_clockevent, ce)
 100
 101 static void __iomem *ttc_sched_clock_val_reg;
 102
 103 /**
 104  * ttc_set_interval - Set the timer interval value
 105  *
 106  * @timer:      Pointer to the timer instance
 107  * @cycles:     Timer interval ticks
 108  **/
 109 static void ttc_set_interval(struct ttc_timer *timer,
 110                                         unsigned long cycles)
 111 {
 112         u32 ctrl_reg;
 113
 114         /* Disable the counter, set the counter value  and re-enable counter */
 115         ctrl_reg = readl_relaxed(timer->base_addr + TTC_CNT_CNTRL_OFFSET);
 116         ctrl_reg |= TTC_CNT_CNTRL_DISABLE_MASK;
 117         writel_relaxed(ctrl_reg, timer->base_addr + TTC_CNT_CNTRL_OFFSET);
 118
 119         writel_relaxed(cycles, timer->base_addr + TTC_INTR_VAL_OFFSET);
 120
 121         /*
 122          * Reset the counter (0x10) so that it starts from 0, one-shot
 123          * mode makes this needed for timing to be right.
 124          */
 125         ctrl_reg |= CNT_CNTRL_RESET;
 126         ctrl_reg &= ~TTC_CNT_CNTRL_DISABLE_MASK;
 127         writel_relaxed(ctrl_reg, timer->base_addr + TTC_CNT_CNTRL_OFFSET);
 128 }
 129
 130 /**
 131  * ttc_clock_event_interrupt - Clock event timer interrupt handler
 132  *
 133  * @irq:        IRQ number of the Timer
 134  * @dev_id:     void pointer to the ttc_timer instance
 135  *
 136  * returns: Always IRQ_HANDLED - success
 137  **/
 138 static irqreturn_t ttc_clock_event_interrupt(int irq, void *dev_id)
 139 {
 140         struct ttc_timer_clockevent *ttce = dev_id;
 141         struct ttc_timer *timer = &ttce->ttc;
 142
 143         /* Acknowledge the interrupt and call event handler */
 144         readl_relaxed(timer->base_addr + TTC_ISR_OFFSET);
 145
 146         ttce->ce.event_handler(&ttce->ce);
 147
 148         return IRQ_HANDLED;
 149 }
 150
 151 /**
 152  * __ttc_clocksource_read - Reads the timer counter register
 153  *
 154  * returns: Current timer counter register value
 155  **/
 156 static u64 __ttc_clocksource_read(struct clocksource *cs)
 157 {
 158         struct ttc_timer *timer = &to_ttc_timer_clksrc(cs)->ttc;
 159
 160         return (u64)readl_relaxed(timer->base_addr +
 161                                 TTC_COUNT_VAL_OFFSET);
 162 }
 163
 164 static u64 notrace ttc_sched_clock_read(void)
 165 {
 166         return readl_relaxed(ttc_sched_clock_val_reg);
 167 }
 168
 169 /**
 170  * ttc_set_next_event - Sets the time interval for next event
 171  *
 172  * @cycles:     Timer interval ticks
 173  * @evt:        Address of clock event instance
 174  *
 175  * returns: Always 0 - success
 176  **/
 177 static int ttc_set_next_event(unsigned long cycles,
 178                                         struct clock_event_device *evt)
 179 {
 180         struct ttc_timer_clockevent *ttce = to_ttc_timer_clkevent(evt);
 181         struct ttc_timer *timer = &ttce->ttc;
 182
 183         ttc_set_interval(timer, cycles);
 184         return 0;
 185 }
 186
 187 /**
 188  * ttc_set_{shutdown|oneshot|periodic} - Sets the state of timer
 189  *
 190  * @evt:        Address of clock event instance
 191  **/
 192 static int ttc_shutdown(struct clock_event_device *evt)
 193 {
 194         struct ttc_timer_clockevent *ttce = to_ttc_timer_clkevent(evt);
 195         struct ttc_timer *timer = &ttce->ttc;
 196         u32 ctrl_reg;
 197
 198         ctrl_reg = readl_relaxed(timer->base_addr + TTC_CNT_CNTRL_OFFSET);
 199         ctrl_reg |= TTC_CNT_CNTRL_DISABLE_MASK;
 200         writel_relaxed(ctrl_reg, timer->base_addr + TTC_CNT_CNTRL_OFFSET);
 201         return 0;
 202 }
 203
 204 static int ttc_set_periodic(struct clock_event_device *evt)
 205 {
 206         struct ttc_timer_clockevent *ttce = to_ttc_timer_clkevent(evt);
 207         struct ttc_timer *timer = &ttce->ttc;
 208
 209         ttc_set_interval(timer,
 210                          DIV_ROUND_CLOSEST(ttce->ttc.freq, PRESCALE * HZ));
 211         return 0;
 212 }
 213
 214 static int ttc_resume(struct clock_event_device *evt)
 215 {
 216         struct ttc_timer_clockevent *ttce = to_ttc_timer_clkevent(evt);
 217         struct ttc_timer *timer = &ttce->ttc;
 218         u32 ctrl_reg;
 219
 220         ctrl_reg = readl_relaxed(timer->base_addr + TTC_CNT_CNTRL_OFFSET);
 221         ctrl_reg &= ~TTC_CNT_CNTRL_DISABLE_MASK;
 222         writel_relaxed(ctrl_reg, timer->base_addr + TTC_CNT_CNTRL_OFFSET);
 223         return 0;
 224 }
 225
 226 static int ttc_rate_change_clocksource_cb(struct notifier_block *nb,
 227                 unsigned long event, void *data)
 228 {
 229         struct clk_notifier_data *ndata = data;
 230         struct ttc_timer *ttc = to_ttc_timer(nb);
 231         struct ttc_timer_clocksource *ttccs = container_of(ttc,
 232                         struct ttc_timer_clocksource, ttc);
 233
 234         switch (event) {
 235         case PRE_RATE_CHANGE:
 236         {
 237                 u32 psv;
 238                 unsigned long factor, rate_low, rate_high;
 239
 240                 if (ndata->new_rate > ndata->old_rate) {
 241                         factor = DIV_ROUND_CLOSEST(ndata->new_rate,
 242                                         ndata->old_rate);
 243                         rate_low = ndata->old_rate;
 244                         rate_high = ndata->new_rate;
 245                 } else {
 246                         factor = DIV_ROUND_CLOSEST(ndata->old_rate,
 247                                         ndata->new_rate);
 248                         rate_low = ndata->new_rate;
 249                         rate_high = ndata->old_rate;
 250                 }
 251
 252                 if (!is_power_of_2(factor))
 253                                 return NOTIFY_BAD;
 254
 255                 if (abs(rate_high - (factor * rate_low)) > MAX_F_ERR)
 256                         return NOTIFY_BAD;
 257
 258                 factor = __ilog2_u32(factor);
 259
 260                 /*
 261                  * store timer clock ctrl register so we can restore it in case
 262                  * of an abort.
 263                  */
 264                 ttccs->scale_clk_ctrl_reg_old =
 265                         readl_relaxed(ttccs->ttc.base_addr +
 266                         TTC_CLK_CNTRL_OFFSET);
 267
 268                 psv = (ttccs->scale_clk_ctrl_reg_old &
 269                                 TTC_CLK_CNTRL_PSV_MASK) >>
 270                                 TTC_CLK_CNTRL_PSV_SHIFT;
 271                 if (ndata->new_rate < ndata->old_rate)
 272                         psv -= factor;
 273                 else
 274                         psv += factor;
 275
 276                 /* prescaler within legal range? */
 277                 if (psv & ~(TTC_CLK_CNTRL_PSV_MASK >> TTC_CLK_CNTRL_PSV_SHIFT))
 278                         return NOTIFY_BAD;
 279
 280                 ttccs->scale_clk_ctrl_reg_new = ttccs->scale_clk_ctrl_reg_old &
 281                         ~TTC_CLK_CNTRL_PSV_MASK;
 282                 ttccs->scale_clk_ctrl_reg_new |= psv << TTC_CLK_CNTRL_PSV_SHIFT;
 283
 284
 285                 /* scale down: adjust divider in post-change notification */
 286                 if (ndata->new_rate < ndata->old_rate)
 287                         return NOTIFY_DONE;
 288
 289                 /* scale up: adjust divider now - before frequency change */
 290                 writel_relaxed(ttccs->scale_clk_ctrl_reg_new,
 291                                ttccs->ttc.base_addr + TTC_CLK_CNTRL_OFFSET);
 292                 break;
 293         }
 294         case POST_RATE_CHANGE:
 295                 /* scale up: pre-change notification did the adjustment */
 296                 if (ndata->new_rate > ndata->old_rate)
 297                         return NOTIFY_OK;
 298
 299                 /* scale down: adjust divider now - after frequency change */
 300                 writel_relaxed(ttccs->scale_clk_ctrl_reg_new,
 301                                ttccs->ttc.base_addr + TTC_CLK_CNTRL_OFFSET);
 302                 break;
 303
 304         case ABORT_RATE_CHANGE:
 305                 /* we have to undo the adjustment in case we scale up */
 306                 if (ndata->new_rate < ndata->old_rate)
 307                         return NOTIFY_OK;
 308
 309                 /* restore original register value */
 310                 writel_relaxed(ttccs->scale_clk_ctrl_reg_old,
 311                                ttccs->ttc.base_addr + TTC_CLK_CNTRL_OFFSET);
 312                 fallthrough;
 313         default:
 314                 return NOTIFY_DONE;
 315         }
 316
 317         return NOTIFY_DONE;
 318 }
 319
 320 static int __init ttc_setup_clocksource(struct clk *clk, void __iomem *base,
 321                                          u32 timer_width)
 322 {
 323         struct ttc_timer_clocksource *ttccs;
 324         int err;
 325
 326         ttccs = kzalloc(sizeof(*ttccs), GFP_KERNEL);
 327         if (!ttccs)
 328                 return -ENOMEM;
 329
 330         ttccs->ttc.clk = clk;
 331
 332         err = clk_prepare_enable(ttccs->ttc.clk);
 333         if (err) {
 334                 kfree(ttccs);
 335                 return err;
 336         }
 337
 338         ttccs->ttc.freq = clk_get_rate(ttccs->ttc.clk);
 339
 340         ttccs->ttc.clk_rate_change_nb.notifier_call =
 341                 ttc_rate_change_clocksource_cb;
 342         ttccs->ttc.clk_rate_change_nb.next = NULL;
 343
 344         err = clk_notifier_register(ttccs->ttc.clk,
 345                                     &ttccs->ttc.clk_rate_change_nb);
 346         if (err)
 347                 pr_warn("Unable to register clock notifier.\n");
 348
 349         ttccs->ttc.base_addr = base;
 350         ttccs->cs.name = "ttc_clocksource";
 351         ttccs->cs.rating = 200;
 352         ttccs->cs.read = __ttc_clocksource_read;
 353         ttccs->cs.mask = CLOCKSOURCE_MASK(timer_width);
 354         ttccs->cs.flags = CLOCK_SOURCE_IS_CONTINUOUS;
 355
 356         /*
 357          * Setup the clock source counter to be an incrementing counter
 358          * with no interrupt and it rolls over at 0xFFFF. Pre-scale
 359          * it by 32 also. Let it start running now.
 360          */
 361         writel_relaxed(0x0,  ttccs->ttc.base_addr + TTC_IER_OFFSET);
 362         writel_relaxed(CLK_CNTRL_PRESCALE | CLK_CNTRL_PRESCALE_EN,
 363                      ttccs->ttc.base_addr + TTC_CLK_CNTRL_OFFSET);
 364         writel_relaxed(CNT_CNTRL_RESET,
 365                      ttccs->ttc.base_addr + TTC_CNT_CNTRL_OFFSET);
 366
 367         err = clocksource_register_hz(&ttccs->cs, ttccs->ttc.freq / PRESCALE);
 368         if (err) {
 369                 kfree(ttccs);
 370                 return err;
 371         }
 372
 373         ttc_sched_clock_val_reg = base + TTC_COUNT_VAL_OFFSET;
 374         sched_clock_register(ttc_sched_clock_read, timer_width,
 375                              ttccs->ttc.freq / PRESCALE);
 376
 377         return 0;
 378 }
 379
 380 static int ttc_rate_change_clockevent_cb(struct notifier_block *nb,
 381                 unsigned long event, void *data)
 382 {
 383         struct clk_notifier_data *ndata = data;
 384         struct ttc_timer *ttc = to_ttc_timer(nb);
 385         struct ttc_timer_clockevent *ttcce = container_of(ttc,
 386                         struct ttc_timer_clockevent, ttc);
 387
 388         switch (event) {
 389         case POST_RATE_CHANGE:
 390                 /* update cached frequency */
 391                 ttc->freq = ndata->new_rate;
 392
 393                 clockevents_update_freq(&ttcce->ce, ndata->new_rate / PRESCALE);
 394
 395                 fallthrough;
 396         case PRE_RATE_CHANGE:
 397         case ABORT_RATE_CHANGE:
 398         default:
 399                 return NOTIFY_DONE;
 400         }
 401 }
 402
 403 static int __init ttc_setup_clockevent(struct clk *clk,
 404                                        void __iomem *base, u32 irq)
 405 {
 406         struct ttc_timer_clockevent *ttcce;
 407         int err;
 408
 409         ttcce = kzalloc(sizeof(*ttcce), GFP_KERNEL);
 410         if (!ttcce)
 411                 return -ENOMEM;
 412
 413         ttcce->ttc.clk = clk;
 414
 415         err = clk_prepare_enable(ttcce->ttc.clk);
 416         if (err)
 417                 goto out_kfree;
 418
 419         ttcce->ttc.clk_rate_change_nb.notifier_call =
 420                 ttc_rate_change_clockevent_cb;
 421         ttcce->ttc.clk_rate_change_nb.next = NULL;
 422
 423         err = clk_notifier_register(ttcce->ttc.clk,
 424                                     &ttcce->ttc.clk_rate_change_nb);
 425         if (err) {
 426                 pr_warn("Unable to register clock notifier.\n");
 427                 goto out_kfree;
 428         }
 429
 430         ttcce->ttc.freq = clk_get_rate(ttcce->ttc.clk);
 431
 432         ttcce->ttc.base_addr = base;
 433         ttcce->ce.name = "ttc_clockevent";
 434         ttcce->ce.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT;
 435         ttcce->ce.set_next_event = ttc_set_next_event;
 436         ttcce->ce.set_state_shutdown = ttc_shutdown;
 437         ttcce->ce.set_state_periodic = ttc_set_periodic;
 438         ttcce->ce.set_state_oneshot = ttc_shutdown;
 439         ttcce->ce.tick_resume = ttc_resume;
 440         ttcce->ce.rating = 200;
 441         ttcce->ce.irq = irq;
 442         ttcce->ce.cpumask = cpu_possible_mask;
 443
 444         /*
 445          * Setup the clock event timer to be an interval timer which
 446          * is prescaled by 32 using the interval interrupt. Leave it
 447          * disabled for now.
 448          */
 449         writel_relaxed(0x23, ttcce->ttc.base_addr + TTC_CNT_CNTRL_OFFSET);
 450         writel_relaxed(CLK_CNTRL_PRESCALE | CLK_CNTRL_PRESCALE_EN,
 451                      ttcce->ttc.base_addr + TTC_CLK_CNTRL_OFFSET);
 452         writel_relaxed(0x1,  ttcce->ttc.base_addr + TTC_IER_OFFSET);
 453
 454         err = request_irq(irq, ttc_clock_event_interrupt,
 455                           IRQF_TIMER, ttcce->ce.name, ttcce);
 456         if (err)
 457                 goto out_kfree;
 458
 459         clockevents_config_and_register(&ttcce->ce,
 460                         ttcce->ttc.freq / PRESCALE, 1, 0xfffe);
 461
 462         return 0;
 463
 464 out_kfree:
 465         kfree(ttcce);
 466         return err;
 467 }
 468
 469 static int __init ttc_timer_probe(struct platform_device *pdev)
 470 {
 471         unsigned int irq;
 472         void __iomem *timer_baseaddr;
 473         struct clk *clk_cs, *clk_ce;
 474         static int initialized;
 475         int clksel, ret;
 476         u32 timer_width = 16;
 477         struct device_node *timer = pdev->dev.of_node;
 478
 479         if (initialized)
 480                 return 0;
 481
 482         initialized = 1;
 483
 484         /*
 485          * Get the 1st Triple Timer Counter (TTC) block from the device tree
 486          * and use it. Note that the event timer uses the interrupt and it's the
 487          * 2nd TTC hence the irq_of_parse_and_map(,1)
 488          */
 489         timer_baseaddr = of_iomap(timer, 0);
 490         if (!timer_baseaddr) {
 491                 pr_err("ERROR: invalid timer base address\n");
 492                 return -ENXIO;
 493         }
 494
 495         irq = irq_of_parse_and_map(timer, 1);
 496         if (irq <= 0) {
 497                 pr_err("ERROR: invalid interrupt number\n");
 498                 return -EINVAL;
 499         }
 500
 501         of_property_read_u32(timer, "timer-width", &timer_width);
 502
 503         clksel = readl_relaxed(timer_baseaddr + TTC_CLK_CNTRL_OFFSET);
 504         clksel = !!(clksel & TTC_CLK_CNTRL_CSRC_MASK);
 505         clk_cs = of_clk_get(timer, clksel);
 506         if (IS_ERR(clk_cs)) {
 507                 pr_err("ERROR: timer input clock not found\n");
 508                 return PTR_ERR(clk_cs);
 509         }
 510
 511         clksel = readl_relaxed(timer_baseaddr + 4 + TTC_CLK_CNTRL_OFFSET);
 512         clksel = !!(clksel & TTC_CLK_CNTRL_CSRC_MASK);
 513         clk_ce = of_clk_get(timer, clksel);
 514         if (IS_ERR(clk_ce)) {
 515                 pr_err("ERROR: timer input clock not found\n");
 516                 return PTR_ERR(clk_ce);
 517         }
 518
 519         ret = ttc_setup_clocksource(clk_cs, timer_baseaddr, timer_width);
 520         if (ret)
 521                 return ret;
 522
 523         ret = ttc_setup_clockevent(clk_ce, timer_baseaddr + 4, irq);
 524         if (ret)
 525                 return ret;
 526
 527         pr_info("%pOFn #0 at %p, irq=%d\n", timer, timer_baseaddr, irq);
 528
 529         return 0;
 530 }
 531
 532 static const struct of_device_id ttc_timer_of_match[] = {
 533         {.compatible = "cdns,ttc"},
 534         {},
 535 };
 536
 537 MODULE_DEVICE_TABLE(of, ttc_timer_of_match);
 538
 539 static struct platform_driver ttc_timer_driver = {
 540         .driver = {
 541                 .name   = "cdns_ttc_timer",
 542                 .of_match_table = ttc_timer_of_match,
 543         },
 544 };
 545 builtin_platform_driver_probe(ttc_timer_driver, ttc_timer_probe);