drivers/clocksource/sh_tmu.c

   1 /*
   2  * SuperH Timer Support - TMU
   3  *
   4  *  Copyright (C) 2009 Magnus Damm
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  18  */
  19
  20 #include <linux/init.h>
  21 #include <linux/platform_device.h>
  22 #include <linux/spinlock.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/ioport.h>
  25 #include <linux/delay.h>
  26 #include <linux/io.h>
  27 #include <linux/clk.h>
  28 #include <linux/irq.h>
  29 #include <linux/err.h>
  30 #include <linux/clocksource.h>
  31 #include <linux/clockchips.h>
  32 #include <linux/sh_timer.h>
  33 #include <linux/slab.h>
  34 #include <linux/module.h>
  35 #include <linux/pm_domain.h>
  36 #include <linux/pm_runtime.h>
  37
  38 struct sh_tmu_device;
  39
  40 struct sh_tmu_channel {
  41         struct sh_tmu_device *tmu;
  42
  43         void __iomem *base;
  44         int irq;
  45
  46         unsigned long rate;
  47         unsigned long periodic;
  48         struct clock_event_device ced;
  49         struct clocksource cs;
  50         bool cs_enabled;
  51         unsigned int enable_count;
  52 };
  53
  54 struct sh_tmu_device {
  55         struct platform_device *pdev;
  56
  57         void __iomem *mapbase;
  58         struct clk *clk;
  59
  60         struct sh_tmu_channel channel;
  61 };
  62
  63 static DEFINE_RAW_SPINLOCK(sh_tmu_lock);
  64
  65 #define TSTR -1 /* shared register */
  66 #define TCOR  0 /* channel register */
  67 #define TCNT 1 /* channel register */
  68 #define TCR 2 /* channel register */
  69
  70 static inline unsigned long sh_tmu_read(struct sh_tmu_channel *ch, int reg_nr)
  71 {
  72         unsigned long offs;
  73
  74         if (reg_nr == TSTR)
  75                 return ioread8(ch->tmu->mapbase);
  76
  77         offs = reg_nr << 2;
  78
  79         if (reg_nr == TCR)
  80                 return ioread16(ch->base + offs);
  81         else
  82                 return ioread32(ch->base + offs);
  83 }
  84
  85 static inline void sh_tmu_write(struct sh_tmu_channel *ch, int reg_nr,
  86                                 unsigned long value)
  87 {
  88         unsigned long offs;
  89
  90         if (reg_nr == TSTR) {
  91                 iowrite8(value, ch->tmu->mapbase);
  92                 return;
  93         }
  94
  95         offs = reg_nr << 2;
  96
  97         if (reg_nr == TCR)
  98                 iowrite16(value, ch->base + offs);
  99         else
 100                 iowrite32(value, ch->base + offs);
 101 }
 102
 103 static void sh_tmu_start_stop_ch(struct sh_tmu_channel *ch, int start)
 104 {
 105         struct sh_timer_config *cfg = ch->tmu->pdev->dev.platform_data;
 106         unsigned long flags, value;
 107
 108         /* start stop register shared by multiple timer channels */
 109         raw_spin_lock_irqsave(&sh_tmu_lock, flags);
 110         value = sh_tmu_read(ch, TSTR);
 111
 112         if (start)
 113                 value |= 1 << cfg->timer_bit;
 114         else
 115                 value &= ~(1 << cfg->timer_bit);
 116
 117         sh_tmu_write(ch, TSTR, value);
 118         raw_spin_unlock_irqrestore(&sh_tmu_lock, flags);
 119 }
 120
 121 static int __sh_tmu_enable(struct sh_tmu_channel *ch)
 122 {
 123         int ret;
 124
 125         /* enable clock */
 126         ret = clk_enable(ch->tmu->clk);
 127         if (ret) {
 128                 dev_err(&ch->tmu->pdev->dev, "cannot enable clock\n");
 129                 return ret;
 130         }
 131
 132         /* make sure channel is disabled */
 133         sh_tmu_start_stop_ch(ch, 0);
 134
 135         /* maximum timeout */
 136         sh_tmu_write(ch, TCOR, 0xffffffff);
 137         sh_tmu_write(ch, TCNT, 0xffffffff);
 138
 139         /* configure channel to parent clock / 4, irq off */
 140         ch->rate = clk_get_rate(ch->tmu->clk) / 4;
 141         sh_tmu_write(ch, TCR, 0x0000);
 142
 143         /* enable channel */
 144         sh_tmu_start_stop_ch(ch, 1);
 145
 146         return 0;
 147 }
 148
 149 static int sh_tmu_enable(struct sh_tmu_channel *ch)
 150 {
 151         if (ch->enable_count++ > 0)
 152                 return 0;
 153
 154         pm_runtime_get_sync(&ch->tmu->pdev->dev);
 155         dev_pm_syscore_device(&ch->tmu->pdev->dev, true);
 156
 157         return __sh_tmu_enable(ch);
 158 }
 159
 160 static void __sh_tmu_disable(struct sh_tmu_channel *ch)
 161 {
 162         /* disable channel */
 163         sh_tmu_start_stop_ch(ch, 0);
 164
 165         /* disable interrupts in TMU block */
 166         sh_tmu_write(ch, TCR, 0x0000);
 167
 168         /* stop clock */
 169         clk_disable(ch->tmu->clk);
 170 }
 171
 172 static void sh_tmu_disable(struct sh_tmu_channel *ch)
 173 {
 174         if (WARN_ON(ch->enable_count == 0))
 175                 return;
 176
 177         if (--ch->enable_count > 0)
 178                 return;
 179
 180         __sh_tmu_disable(ch);
 181
 182         dev_pm_syscore_device(&ch->tmu->pdev->dev, false);
 183         pm_runtime_put(&ch->tmu->pdev->dev);
 184 }
 185
 186 static void sh_tmu_set_next(struct sh_tmu_channel *ch, unsigned long delta,
 187                             int periodic)
 188 {
 189         /* stop timer */
 190         sh_tmu_start_stop_ch(ch, 0);
 191
 192         /* acknowledge interrupt */
 193         sh_tmu_read(ch, TCR);
 194
 195         /* enable interrupt */
 196         sh_tmu_write(ch, TCR, 0x0020);
 197
 198         /* reload delta value in case of periodic timer */
 199         if (periodic)
 200                 sh_tmu_write(ch, TCOR, delta);
 201         else
 202                 sh_tmu_write(ch, TCOR, 0xffffffff);
 203
 204         sh_tmu_write(ch, TCNT, delta);
 205
 206         /* start timer */
 207         sh_tmu_start_stop_ch(ch, 1);
 208 }
 209
 210 static irqreturn_t sh_tmu_interrupt(int irq, void *dev_id)
 211 {
 212         struct sh_tmu_channel *ch = dev_id;
 213
 214         /* disable or acknowledge interrupt */
 215         if (ch->ced.mode == CLOCK_EVT_MODE_ONESHOT)
 216                 sh_tmu_write(ch, TCR, 0x0000);
 217         else
 218                 sh_tmu_write(ch, TCR, 0x0020);
 219
 220         /* notify clockevent layer */
 221         ch->ced.event_handler(&ch->ced);
 222         return IRQ_HANDLED;
 223 }
 224
 225 static struct sh_tmu_channel *cs_to_sh_tmu(struct clocksource *cs)
 226 {
 227         return container_of(cs, struct sh_tmu_channel, cs);
 228 }
 229
 230 static cycle_t sh_tmu_clocksource_read(struct clocksource *cs)
 231 {
 232         struct sh_tmu_channel *ch = cs_to_sh_tmu(cs);
 233
 234         return sh_tmu_read(ch, TCNT) ^ 0xffffffff;
 235 }
 236
 237 static int sh_tmu_clocksource_enable(struct clocksource *cs)
 238 {
 239         struct sh_tmu_channel *ch = cs_to_sh_tmu(cs);
 240         int ret;
 241
 242         if (WARN_ON(ch->cs_enabled))
 243                 return 0;
 244
 245         ret = sh_tmu_enable(ch);
 246         if (!ret) {
 247                 __clocksource_updatefreq_hz(cs, ch->rate);
 248                 ch->cs_enabled = true;
 249         }
 250
 251         return ret;
 252 }
 253
 254 static void sh_tmu_clocksource_disable(struct clocksource *cs)
 255 {
 256         struct sh_tmu_channel *ch = cs_to_sh_tmu(cs);
 257
 258         if (WARN_ON(!ch->cs_enabled))
 259                 return;
 260
 261         sh_tmu_disable(ch);
 262         ch->cs_enabled = false;
 263 }
 264
 265 static void sh_tmu_clocksource_suspend(struct clocksource *cs)
 266 {
 267         struct sh_tmu_channel *ch = cs_to_sh_tmu(cs);
 268
 269         if (!ch->cs_enabled)
 270                 return;
 271
 272         if (--ch->enable_count == 0) {
 273                 __sh_tmu_disable(ch);
 274                 pm_genpd_syscore_poweroff(&ch->tmu->pdev->dev);
 275         }
 276 }
 277
 278 static void sh_tmu_clocksource_resume(struct clocksource *cs)
 279 {
 280         struct sh_tmu_channel *ch = cs_to_sh_tmu(cs);
 281
 282         if (!ch->cs_enabled)
 283                 return;
 284
 285         if (ch->enable_count++ == 0) {
 286                 pm_genpd_syscore_poweron(&ch->tmu->pdev->dev);
 287                 __sh_tmu_enable(ch);
 288         }
 289 }
 290
 291 static int sh_tmu_register_clocksource(struct sh_tmu_channel *ch,
 292                                        const char *name, unsigned long rating)
 293 {
 294         struct clocksource *cs = &ch->cs;
 295
 296         cs->name = name;
 297         cs->rating = rating;
 298         cs->read = sh_tmu_clocksource_read;
 299         cs->enable = sh_tmu_clocksource_enable;
 300         cs->disable = sh_tmu_clocksource_disable;
 301         cs->suspend = sh_tmu_clocksource_suspend;
 302         cs->resume = sh_tmu_clocksource_resume;
 303         cs->mask = CLOCKSOURCE_MASK(32);
 304         cs->flags = CLOCK_SOURCE_IS_CONTINUOUS;
 305
 306         dev_info(&ch->tmu->pdev->dev, "used as clock source\n");
 307
 308         /* Register with dummy 1 Hz value, gets updated in ->enable() */
 309         clocksource_register_hz(cs, 1);
 310         return 0;
 311 }
 312
 313 static struct sh_tmu_channel *ced_to_sh_tmu(struct clock_event_device *ced)
 314 {
 315         return container_of(ced, struct sh_tmu_channel, ced);
 316 }
 317
 318 static void sh_tmu_clock_event_start(struct sh_tmu_channel *ch, int periodic)
 319 {
 320         struct clock_event_device *ced = &ch->ced;
 321
 322         sh_tmu_enable(ch);
 323
 324         clockevents_config(ced, ch->rate);
 325
 326         if (periodic) {
 327                 ch->periodic = (ch->rate + HZ/2) / HZ;
 328                 sh_tmu_set_next(ch, ch->periodic, 1);
 329         }
 330 }
 331
 332 static void sh_tmu_clock_event_mode(enum clock_event_mode mode,
 333                                     struct clock_event_device *ced)
 334 {
 335         struct sh_tmu_channel *ch = ced_to_sh_tmu(ced);
 336         int disabled = 0;
 337
 338         /* deal with old setting first */
 339         switch (ced->mode) {
 340         case CLOCK_EVT_MODE_PERIODIC:
 341         case CLOCK_EVT_MODE_ONESHOT:
 342                 sh_tmu_disable(ch);
 343                 disabled = 1;
 344                 break;
 345         default:
 346                 break;
 347         }
 348
 349         switch (mode) {
 350         case CLOCK_EVT_MODE_PERIODIC:
 351                 dev_info(&ch->tmu->pdev->dev,
 352                          "used for periodic clock events\n");
 353                 sh_tmu_clock_event_start(ch, 1);
 354                 break;
 355         case CLOCK_EVT_MODE_ONESHOT:
 356                 dev_info(&ch->tmu->pdev->dev,
 357                          "used for oneshot clock events\n");
 358                 sh_tmu_clock_event_start(ch, 0);
 359                 break;
 360         case CLOCK_EVT_MODE_UNUSED:
 361                 if (!disabled)
 362                         sh_tmu_disable(ch);
 363                 break;
 364         case CLOCK_EVT_MODE_SHUTDOWN:
 365         default:
 366                 break;
 367         }
 368 }
 369
 370 static int sh_tmu_clock_event_next(unsigned long delta,
 371                                    struct clock_event_device *ced)
 372 {
 373         struct sh_tmu_channel *ch = ced_to_sh_tmu(ced);
 374
 375         BUG_ON(ced->mode != CLOCK_EVT_MODE_ONESHOT);
 376
 377         /* program new delta value */
 378         sh_tmu_set_next(ch, delta, 0);
 379         return 0;
 380 }
 381
 382 static void sh_tmu_clock_event_suspend(struct clock_event_device *ced)
 383 {
 384         pm_genpd_syscore_poweroff(&ced_to_sh_tmu(ced)->tmu->pdev->dev);
 385 }
 386
 387 static void sh_tmu_clock_event_resume(struct clock_event_device *ced)
 388 {
 389         pm_genpd_syscore_poweron(&ced_to_sh_tmu(ced)->tmu->pdev->dev);
 390 }
 391
 392 static void sh_tmu_register_clockevent(struct sh_tmu_channel *ch,
 393                                        const char *name, unsigned long rating)
 394 {
 395         struct clock_event_device *ced = &ch->ced;
 396         int ret;
 397
 398         memset(ced, 0, sizeof(*ced));
 399
 400         ced->name = name;
 401         ced->features = CLOCK_EVT_FEAT_PERIODIC;
 402         ced->features |= CLOCK_EVT_FEAT_ONESHOT;
 403         ced->rating = rating;
 404         ced->cpumask = cpumask_of(0);
 405         ced->set_next_event = sh_tmu_clock_event_next;
 406         ced->set_mode = sh_tmu_clock_event_mode;
 407         ced->suspend = sh_tmu_clock_event_suspend;
 408         ced->resume = sh_tmu_clock_event_resume;
 409
 410         dev_info(&ch->tmu->pdev->dev, "used for clock events\n");
 411
 412         clockevents_config_and_register(ced, 1, 0x300, 0xffffffff);
 413
 414         ret = request_irq(ch->irq, sh_tmu_interrupt,
 415                           IRQF_TIMER | IRQF_IRQPOLL | IRQF_NOBALANCING,
 416                           dev_name(&ch->tmu->pdev->dev), ch);
 417         if (ret) {
 418                 dev_err(&ch->tmu->pdev->dev, "failed to request irq %d\n",
 419                         ch->irq);
 420                 return;
 421         }
 422 }
 423
 424 static int sh_tmu_register(struct sh_tmu_channel *ch, const char *name,
 425                     unsigned long clockevent_rating,
 426                     unsigned long clocksource_rating)
 427 {
 428         if (clockevent_rating)
 429                 sh_tmu_register_clockevent(ch, name, clockevent_rating);
 430         else if (clocksource_rating)
 431                 sh_tmu_register_clocksource(ch, name, clocksource_rating);
 432
 433         return 0;
 434 }
 435
 436 static int sh_tmu_channel_setup(struct sh_tmu_channel *ch,
 437                                 struct sh_tmu_device *tmu)
 438 {
 439         struct sh_timer_config *cfg = tmu->pdev->dev.platform_data;
 440
 441         memset(ch, 0, sizeof(*ch));
 442         ch->tmu = tmu;
 443
 444         ch->irq = platform_get_irq(tmu->pdev, 0);
 445         if (ch->irq < 0) {
 446                 dev_err(&tmu->pdev->dev, "failed to get irq\n");
 447                 return ch->irq;
 448         }
 449
 450         ch->cs_enabled = false;
 451         ch->enable_count = 0;
 452
 453         return sh_tmu_register(ch, dev_name(&tmu->pdev->dev),
 454                                cfg->clockevent_rating,
 455                                cfg->clocksource_rating);
 456 }
 457
 458 static int sh_tmu_setup(struct sh_tmu_device *tmu, struct platform_device *pdev)
 459 {
 460         struct sh_timer_config *cfg = pdev->dev.platform_data;
 461         struct resource *res;
 462         int ret;
 463         ret = -ENXIO;
 464
 465         memset(tmu, 0, sizeof(*tmu));
 466         tmu->pdev = pdev;
 467
 468         if (!cfg) {
 469                 dev_err(&tmu->pdev->dev, "missing platform data\n");
 470                 goto err0;
 471         }
 472
 473         platform_set_drvdata(pdev, tmu);
 474
 475         res = platform_get_resource(tmu->pdev, IORESOURCE_MEM, 0);
 476         if (!res) {
 477                 dev_err(&tmu->pdev->dev, "failed to get I/O memory\n");
 478                 goto err0;
 479         }
 480
 481         /*
 482          * Map memory, let channel.base point to our channel and mapbase to the
 483          * start/stop shared register.
 484          */
 485         tmu->channel.base = ioremap_nocache(res->start, resource_size(res));
 486         if (tmu->channel.base == NULL) {
 487                 dev_err(&tmu->pdev->dev, "failed to remap I/O memory\n");
 488                 goto err0;
 489         }
 490
 491         tmu->mapbase = tmu->channel.base - cfg->channel_offset;
 492
 493         /* get hold of clock */
 494         tmu->clk = clk_get(&tmu->pdev->dev, "tmu_fck");
 495         if (IS_ERR(tmu->clk)) {
 496                 dev_err(&tmu->pdev->dev, "cannot get clock\n");
 497                 ret = PTR_ERR(tmu->clk);
 498                 goto err1;
 499         }
 500
 501         ret = clk_prepare(tmu->clk);
 502         if (ret < 0)
 503                 goto err2;
 504
 505         ret = sh_tmu_channel_setup(&tmu->channel, tmu);
 506         if (ret < 0)
 507                 goto err3;
 508
 509         return 0;
 510
 511  err3:
 512         clk_unprepare(tmu->clk);
 513  err2:
 514         clk_put(tmu->clk);
 515  err1:
 516         iounmap(tmu->channel.base);
 517  err0:
 518         return ret;
 519 }
 520
 521 static int sh_tmu_probe(struct platform_device *pdev)
 522 {
 523         struct sh_tmu_device *tmu = platform_get_drvdata(pdev);
 524         struct sh_timer_config *cfg = pdev->dev.platform_data;
 525         int ret;
 526
 527         if (!is_early_platform_device(pdev)) {
 528                 pm_runtime_set_active(&pdev->dev);
 529                 pm_runtime_enable(&pdev->dev);
 530         }
 531
 532         if (tmu) {
 533                 dev_info(&pdev->dev, "kept as earlytimer\n");
 534                 goto out;
 535         }
 536
 537         tmu = kmalloc(sizeof(*tmu), GFP_KERNEL);
 538         if (tmu == NULL) {
 539                 dev_err(&pdev->dev, "failed to allocate driver data\n");
 540                 return -ENOMEM;
 541         }
 542
 543         ret = sh_tmu_setup(tmu, pdev);
 544         if (ret) {
 545                 kfree(tmu);
 546                 pm_runtime_idle(&pdev->dev);
 547                 return ret;
 548         }
 549         if (is_early_platform_device(pdev))
 550                 return 0;
 551
 552  out:
 553         if (cfg->clockevent_rating || cfg->clocksource_rating)
 554                 pm_runtime_irq_safe(&pdev->dev);
 555         else
 556                 pm_runtime_idle(&pdev->dev);
 557
 558         return 0;
 559 }
 560
 561 static int sh_tmu_remove(struct platform_device *pdev)
 562 {
 563         return -EBUSY; /* cannot unregister clockevent and clocksource */
 564 }
 565
 566 static struct platform_driver sh_tmu_device_driver = {
 567         .probe          = sh_tmu_probe,
 568         .remove         = sh_tmu_remove,
 569         .driver         = {
 570                 .name   = "sh_tmu",
 571         }
 572 };
 573
 574 static int __init sh_tmu_init(void)
 575 {
 576         return platform_driver_register(&sh_tmu_device_driver);
 577 }
 578
 579 static void __exit sh_tmu_exit(void)
 580 {
 581         platform_driver_unregister(&sh_tmu_device_driver);
 582 }
 583
 584 early_platform_init("earlytimer", &sh_tmu_device_driver);
 585 subsys_initcall(sh_tmu_init);
 586 module_exit(sh_tmu_exit);
 587
 588 MODULE_AUTHOR("Magnus Damm");
 589 MODULE_DESCRIPTION("SuperH TMU Timer Driver");
 590 MODULE_LICENSE("GPL v2");