2 * SuperH Timer Support - TMU
4 * Copyright (C) 2009 Magnus Damm
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 #include <linux/init.h>
21 #include <linux/platform_device.h>
22 #include <linux/spinlock.h>
23 #include <linux/interrupt.h>
24 #include <linux/ioport.h>
25 #include <linux/delay.h>
27 #include <linux/clk.h>
28 #include <linux/irq.h>
29 #include <linux/err.h>
30 #include <linux/clocksource.h>
31 #include <linux/clockchips.h>
32 #include <linux/sh_timer.h>
33 #include <linux/slab.h>
34 #include <linux/module.h>
35 #include <linux/pm_domain.h>
36 #include <linux/pm_runtime.h>
40 struct sh_tmu_channel {
41 struct sh_tmu_device *tmu;
46 unsigned long periodic;
47 struct clock_event_device ced;
48 struct clocksource cs;
50 unsigned int enable_count;
53 struct sh_tmu_device {
54 struct platform_device *pdev;
56 void __iomem *mapbase;
59 struct sh_tmu_channel channel;
62 static DEFINE_RAW_SPINLOCK(sh_tmu_lock);
64 #define TSTR -1 /* shared register */
65 #define TCOR 0 /* channel register */
66 #define TCNT 1 /* channel register */
67 #define TCR 2 /* channel register */
69 static inline unsigned long sh_tmu_read(struct sh_tmu_channel *ch, int reg_nr)
71 struct sh_timer_config *cfg = ch->tmu->pdev->dev.platform_data;
72 void __iomem *base = ch->tmu->mapbase;
76 return ioread8(base - cfg->channel_offset);
81 return ioread16(base + offs);
83 return ioread32(base + offs);
86 static inline void sh_tmu_write(struct sh_tmu_channel *ch, int reg_nr,
89 struct sh_timer_config *cfg = ch->tmu->pdev->dev.platform_data;
90 void __iomem *base = ch->tmu->mapbase;
94 iowrite8(value, base - cfg->channel_offset);
101 iowrite16(value, base + offs);
103 iowrite32(value, base + offs);
106 static void sh_tmu_start_stop_ch(struct sh_tmu_channel *ch, int start)
108 struct sh_timer_config *cfg = ch->tmu->pdev->dev.platform_data;
109 unsigned long flags, value;
111 /* start stop register shared by multiple timer channels */
112 raw_spin_lock_irqsave(&sh_tmu_lock, flags);
113 value = sh_tmu_read(ch, TSTR);
116 value |= 1 << cfg->timer_bit;
118 value &= ~(1 << cfg->timer_bit);
120 sh_tmu_write(ch, TSTR, value);
121 raw_spin_unlock_irqrestore(&sh_tmu_lock, flags);
124 static int __sh_tmu_enable(struct sh_tmu_channel *ch)
129 ret = clk_enable(ch->tmu->clk);
131 dev_err(&ch->tmu->pdev->dev, "cannot enable clock\n");
135 /* make sure channel is disabled */
136 sh_tmu_start_stop_ch(ch, 0);
138 /* maximum timeout */
139 sh_tmu_write(ch, TCOR, 0xffffffff);
140 sh_tmu_write(ch, TCNT, 0xffffffff);
142 /* configure channel to parent clock / 4, irq off */
143 ch->rate = clk_get_rate(ch->tmu->clk) / 4;
144 sh_tmu_write(ch, TCR, 0x0000);
147 sh_tmu_start_stop_ch(ch, 1);
152 static int sh_tmu_enable(struct sh_tmu_channel *ch)
154 if (ch->enable_count++ > 0)
157 pm_runtime_get_sync(&ch->tmu->pdev->dev);
158 dev_pm_syscore_device(&ch->tmu->pdev->dev, true);
160 return __sh_tmu_enable(ch);
163 static void __sh_tmu_disable(struct sh_tmu_channel *ch)
165 /* disable channel */
166 sh_tmu_start_stop_ch(ch, 0);
168 /* disable interrupts in TMU block */
169 sh_tmu_write(ch, TCR, 0x0000);
172 clk_disable(ch->tmu->clk);
175 static void sh_tmu_disable(struct sh_tmu_channel *ch)
177 if (WARN_ON(ch->enable_count == 0))
180 if (--ch->enable_count > 0)
183 __sh_tmu_disable(ch);
185 dev_pm_syscore_device(&ch->tmu->pdev->dev, false);
186 pm_runtime_put(&ch->tmu->pdev->dev);
189 static void sh_tmu_set_next(struct sh_tmu_channel *ch, unsigned long delta,
193 sh_tmu_start_stop_ch(ch, 0);
195 /* acknowledge interrupt */
196 sh_tmu_read(ch, TCR);
198 /* enable interrupt */
199 sh_tmu_write(ch, TCR, 0x0020);
201 /* reload delta value in case of periodic timer */
203 sh_tmu_write(ch, TCOR, delta);
205 sh_tmu_write(ch, TCOR, 0xffffffff);
207 sh_tmu_write(ch, TCNT, delta);
210 sh_tmu_start_stop_ch(ch, 1);
213 static irqreturn_t sh_tmu_interrupt(int irq, void *dev_id)
215 struct sh_tmu_channel *ch = dev_id;
217 /* disable or acknowledge interrupt */
218 if (ch->ced.mode == CLOCK_EVT_MODE_ONESHOT)
219 sh_tmu_write(ch, TCR, 0x0000);
221 sh_tmu_write(ch, TCR, 0x0020);
223 /* notify clockevent layer */
224 ch->ced.event_handler(&ch->ced);
228 static struct sh_tmu_channel *cs_to_sh_tmu(struct clocksource *cs)
230 return container_of(cs, struct sh_tmu_channel, cs);
233 static cycle_t sh_tmu_clocksource_read(struct clocksource *cs)
235 struct sh_tmu_channel *ch = cs_to_sh_tmu(cs);
237 return sh_tmu_read(ch, TCNT) ^ 0xffffffff;
240 static int sh_tmu_clocksource_enable(struct clocksource *cs)
242 struct sh_tmu_channel *ch = cs_to_sh_tmu(cs);
245 if (WARN_ON(ch->cs_enabled))
248 ret = sh_tmu_enable(ch);
250 __clocksource_updatefreq_hz(cs, ch->rate);
251 ch->cs_enabled = true;
257 static void sh_tmu_clocksource_disable(struct clocksource *cs)
259 struct sh_tmu_channel *ch = cs_to_sh_tmu(cs);
261 if (WARN_ON(!ch->cs_enabled))
265 ch->cs_enabled = false;
268 static void sh_tmu_clocksource_suspend(struct clocksource *cs)
270 struct sh_tmu_channel *ch = cs_to_sh_tmu(cs);
275 if (--ch->enable_count == 0) {
276 __sh_tmu_disable(ch);
277 pm_genpd_syscore_poweroff(&ch->tmu->pdev->dev);
281 static void sh_tmu_clocksource_resume(struct clocksource *cs)
283 struct sh_tmu_channel *ch = cs_to_sh_tmu(cs);
288 if (ch->enable_count++ == 0) {
289 pm_genpd_syscore_poweron(&ch->tmu->pdev->dev);
294 static int sh_tmu_register_clocksource(struct sh_tmu_channel *ch,
295 char *name, unsigned long rating)
297 struct clocksource *cs = &ch->cs;
301 cs->read = sh_tmu_clocksource_read;
302 cs->enable = sh_tmu_clocksource_enable;
303 cs->disable = sh_tmu_clocksource_disable;
304 cs->suspend = sh_tmu_clocksource_suspend;
305 cs->resume = sh_tmu_clocksource_resume;
306 cs->mask = CLOCKSOURCE_MASK(32);
307 cs->flags = CLOCK_SOURCE_IS_CONTINUOUS;
309 dev_info(&ch->tmu->pdev->dev, "used as clock source\n");
311 /* Register with dummy 1 Hz value, gets updated in ->enable() */
312 clocksource_register_hz(cs, 1);
316 static struct sh_tmu_channel *ced_to_sh_tmu(struct clock_event_device *ced)
318 return container_of(ced, struct sh_tmu_channel, ced);
321 static void sh_tmu_clock_event_start(struct sh_tmu_channel *ch, int periodic)
323 struct clock_event_device *ced = &ch->ced;
327 clockevents_config(ced, ch->rate);
330 ch->periodic = (ch->rate + HZ/2) / HZ;
331 sh_tmu_set_next(ch, ch->periodic, 1);
335 static void sh_tmu_clock_event_mode(enum clock_event_mode mode,
336 struct clock_event_device *ced)
338 struct sh_tmu_channel *ch = ced_to_sh_tmu(ced);
341 /* deal with old setting first */
343 case CLOCK_EVT_MODE_PERIODIC:
344 case CLOCK_EVT_MODE_ONESHOT:
353 case CLOCK_EVT_MODE_PERIODIC:
354 dev_info(&ch->tmu->pdev->dev,
355 "used for periodic clock events\n");
356 sh_tmu_clock_event_start(ch, 1);
358 case CLOCK_EVT_MODE_ONESHOT:
359 dev_info(&ch->tmu->pdev->dev,
360 "used for oneshot clock events\n");
361 sh_tmu_clock_event_start(ch, 0);
363 case CLOCK_EVT_MODE_UNUSED:
367 case CLOCK_EVT_MODE_SHUTDOWN:
373 static int sh_tmu_clock_event_next(unsigned long delta,
374 struct clock_event_device *ced)
376 struct sh_tmu_channel *ch = ced_to_sh_tmu(ced);
378 BUG_ON(ced->mode != CLOCK_EVT_MODE_ONESHOT);
380 /* program new delta value */
381 sh_tmu_set_next(ch, delta, 0);
385 static void sh_tmu_clock_event_suspend(struct clock_event_device *ced)
387 pm_genpd_syscore_poweroff(&ced_to_sh_tmu(ced)->tmu->pdev->dev);
390 static void sh_tmu_clock_event_resume(struct clock_event_device *ced)
392 pm_genpd_syscore_poweron(&ced_to_sh_tmu(ced)->tmu->pdev->dev);
395 static void sh_tmu_register_clockevent(struct sh_tmu_channel *ch,
396 char *name, unsigned long rating)
398 struct clock_event_device *ced = &ch->ced;
401 memset(ced, 0, sizeof(*ced));
404 ced->features = CLOCK_EVT_FEAT_PERIODIC;
405 ced->features |= CLOCK_EVT_FEAT_ONESHOT;
406 ced->rating = rating;
407 ced->cpumask = cpumask_of(0);
408 ced->set_next_event = sh_tmu_clock_event_next;
409 ced->set_mode = sh_tmu_clock_event_mode;
410 ced->suspend = sh_tmu_clock_event_suspend;
411 ced->resume = sh_tmu_clock_event_resume;
413 dev_info(&ch->tmu->pdev->dev, "used for clock events\n");
415 clockevents_config_and_register(ced, 1, 0x300, 0xffffffff);
417 ret = request_irq(ch->irq, sh_tmu_interrupt,
418 IRQF_TIMER | IRQF_IRQPOLL | IRQF_NOBALANCING,
419 dev_name(&ch->tmu->pdev->dev), ch);
421 dev_err(&ch->tmu->pdev->dev, "failed to request irq %d\n",
427 static int sh_tmu_register(struct sh_tmu_channel *ch, char *name,
428 unsigned long clockevent_rating,
429 unsigned long clocksource_rating)
431 if (clockevent_rating)
432 sh_tmu_register_clockevent(ch, name, clockevent_rating);
433 else if (clocksource_rating)
434 sh_tmu_register_clocksource(ch, name, clocksource_rating);
439 static int sh_tmu_setup(struct sh_tmu_device *tmu, struct platform_device *pdev)
441 struct sh_timer_config *cfg = pdev->dev.platform_data;
442 struct resource *res;
446 memset(tmu, 0, sizeof(*tmu));
450 dev_err(&tmu->pdev->dev, "missing platform data\n");
454 platform_set_drvdata(pdev, tmu);
456 res = platform_get_resource(tmu->pdev, IORESOURCE_MEM, 0);
458 dev_err(&tmu->pdev->dev, "failed to get I/O memory\n");
462 tmu->channel.irq = platform_get_irq(tmu->pdev, 0);
463 if (tmu->channel.irq < 0) {
464 dev_err(&tmu->pdev->dev, "failed to get irq\n");
468 /* map memory, let mapbase point to our channel */
469 tmu->mapbase = ioremap_nocache(res->start, resource_size(res));
470 if (tmu->mapbase == NULL) {
471 dev_err(&tmu->pdev->dev, "failed to remap I/O memory\n");
475 /* get hold of clock */
476 tmu->clk = clk_get(&tmu->pdev->dev, "tmu_fck");
477 if (IS_ERR(tmu->clk)) {
478 dev_err(&tmu->pdev->dev, "cannot get clock\n");
479 ret = PTR_ERR(tmu->clk);
483 ret = clk_prepare(tmu->clk);
487 tmu->channel.cs_enabled = false;
488 tmu->channel.enable_count = 0;
489 tmu->channel.tmu = tmu;
491 ret = sh_tmu_register(&tmu->channel, (char *)dev_name(&tmu->pdev->dev),
492 cfg->clockevent_rating,
493 cfg->clocksource_rating);
500 clk_unprepare(tmu->clk);
504 iounmap(tmu->mapbase);
509 static int sh_tmu_probe(struct platform_device *pdev)
511 struct sh_tmu_device *tmu = platform_get_drvdata(pdev);
512 struct sh_timer_config *cfg = pdev->dev.platform_data;
515 if (!is_early_platform_device(pdev)) {
516 pm_runtime_set_active(&pdev->dev);
517 pm_runtime_enable(&pdev->dev);
521 dev_info(&pdev->dev, "kept as earlytimer\n");
525 tmu = kmalloc(sizeof(*tmu), GFP_KERNEL);
527 dev_err(&pdev->dev, "failed to allocate driver data\n");
531 ret = sh_tmu_setup(tmu, pdev);
534 pm_runtime_idle(&pdev->dev);
537 if (is_early_platform_device(pdev))
541 if (cfg->clockevent_rating || cfg->clocksource_rating)
542 pm_runtime_irq_safe(&pdev->dev);
544 pm_runtime_idle(&pdev->dev);
549 static int sh_tmu_remove(struct platform_device *pdev)
551 return -EBUSY; /* cannot unregister clockevent and clocksource */
554 static struct platform_driver sh_tmu_device_driver = {
555 .probe = sh_tmu_probe,
556 .remove = sh_tmu_remove,
562 static int __init sh_tmu_init(void)
564 return platform_driver_register(&sh_tmu_device_driver);
567 static void __exit sh_tmu_exit(void)
569 platform_driver_unregister(&sh_tmu_device_driver);
572 early_platform_init("earlytimer", &sh_tmu_device_driver);
573 subsys_initcall(sh_tmu_init);
574 module_exit(sh_tmu_exit);
576 MODULE_AUTHOR("Magnus Damm");
577 MODULE_DESCRIPTION("SuperH TMU Timer Driver");
578 MODULE_LICENSE("GPL v2");