drivers/clocksource/sh_tmu.c

   1 /*
   2  * SuperH Timer Support - TMU
   3  *
   4  *  Copyright (C) 2009 Magnus Damm
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  18  */
  19
  20 #include <linux/init.h>
  21 #include <linux/platform_device.h>
  22 #include <linux/spinlock.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/ioport.h>
  25 #include <linux/delay.h>
  26 #include <linux/io.h>
  27 #include <linux/clk.h>
  28 #include <linux/irq.h>
  29 #include <linux/err.h>
  30 #include <linux/clocksource.h>
  31 #include <linux/clockchips.h>
  32 #include <linux/sh_timer.h>
  33 #include <linux/slab.h>
  34 #include <linux/module.h>
  35 #include <linux/pm_domain.h>
  36 #include <linux/pm_runtime.h>
  37
  38 struct sh_tmu_device;
  39
  40 struct sh_tmu_channel {
  41         struct sh_tmu_device *tmu;
  42
  43         int irq;
  44
  45         unsigned long rate;
  46         unsigned long periodic;
  47         struct clock_event_device ced;
  48         struct clocksource cs;
  49         bool cs_enabled;
  50         unsigned int enable_count;
  51 };
  52
  53 struct sh_tmu_device {
  54         struct platform_device *pdev;
  55
  56         void __iomem *mapbase;
  57         struct clk *clk;
  58
  59         struct sh_tmu_channel channel;
  60 };
  61
  62 static DEFINE_RAW_SPINLOCK(sh_tmu_lock);
  63
  64 #define TSTR -1 /* shared register */
  65 #define TCOR  0 /* channel register */
  66 #define TCNT 1 /* channel register */
  67 #define TCR 2 /* channel register */
  68
  69 static inline unsigned long sh_tmu_read(struct sh_tmu_channel *ch, int reg_nr)
  70 {
  71         struct sh_timer_config *cfg = ch->tmu->pdev->dev.platform_data;
  72         void __iomem *base = ch->tmu->mapbase;
  73         unsigned long offs;
  74
  75         if (reg_nr == TSTR)
  76                 return ioread8(base - cfg->channel_offset);
  77
  78         offs = reg_nr << 2;
  79
  80         if (reg_nr == TCR)
  81                 return ioread16(base + offs);
  82         else
  83                 return ioread32(base + offs);
  84 }
  85
  86 static inline void sh_tmu_write(struct sh_tmu_channel *ch, int reg_nr,
  87                                 unsigned long value)
  88 {
  89         struct sh_timer_config *cfg = ch->tmu->pdev->dev.platform_data;
  90         void __iomem *base = ch->tmu->mapbase;
  91         unsigned long offs;
  92
  93         if (reg_nr == TSTR) {
  94                 iowrite8(value, base - cfg->channel_offset);
  95                 return;
  96         }
  97
  98         offs = reg_nr << 2;
  99
 100         if (reg_nr == TCR)
 101                 iowrite16(value, base + offs);
 102         else
 103                 iowrite32(value, base + offs);
 104 }
 105
 106 static void sh_tmu_start_stop_ch(struct sh_tmu_channel *ch, int start)
 107 {
 108         struct sh_timer_config *cfg = ch->tmu->pdev->dev.platform_data;
 109         unsigned long flags, value;
 110
 111         /* start stop register shared by multiple timer channels */
 112         raw_spin_lock_irqsave(&sh_tmu_lock, flags);
 113         value = sh_tmu_read(ch, TSTR);
 114
 115         if (start)
 116                 value |= 1 << cfg->timer_bit;
 117         else
 118                 value &= ~(1 << cfg->timer_bit);
 119
 120         sh_tmu_write(ch, TSTR, value);
 121         raw_spin_unlock_irqrestore(&sh_tmu_lock, flags);
 122 }
 123
 124 static int __sh_tmu_enable(struct sh_tmu_channel *ch)
 125 {
 126         int ret;
 127
 128         /* enable clock */
 129         ret = clk_enable(ch->tmu->clk);
 130         if (ret) {
 131                 dev_err(&ch->tmu->pdev->dev, "cannot enable clock\n");
 132                 return ret;
 133         }
 134
 135         /* make sure channel is disabled */
 136         sh_tmu_start_stop_ch(ch, 0);
 137
 138         /* maximum timeout */
 139         sh_tmu_write(ch, TCOR, 0xffffffff);
 140         sh_tmu_write(ch, TCNT, 0xffffffff);
 141
 142         /* configure channel to parent clock / 4, irq off */
 143         ch->rate = clk_get_rate(ch->tmu->clk) / 4;
 144         sh_tmu_write(ch, TCR, 0x0000);
 145
 146         /* enable channel */
 147         sh_tmu_start_stop_ch(ch, 1);
 148
 149         return 0;
 150 }
 151
 152 static int sh_tmu_enable(struct sh_tmu_channel *ch)
 153 {
 154         if (ch->enable_count++ > 0)
 155                 return 0;
 156
 157         pm_runtime_get_sync(&ch->tmu->pdev->dev);
 158         dev_pm_syscore_device(&ch->tmu->pdev->dev, true);
 159
 160         return __sh_tmu_enable(ch);
 161 }
 162
 163 static void __sh_tmu_disable(struct sh_tmu_channel *ch)
 164 {
 165         /* disable channel */
 166         sh_tmu_start_stop_ch(ch, 0);
 167
 168         /* disable interrupts in TMU block */
 169         sh_tmu_write(ch, TCR, 0x0000);
 170
 171         /* stop clock */
 172         clk_disable(ch->tmu->clk);
 173 }
 174
 175 static void sh_tmu_disable(struct sh_tmu_channel *ch)
 176 {
 177         if (WARN_ON(ch->enable_count == 0))
 178                 return;
 179
 180         if (--ch->enable_count > 0)
 181                 return;
 182
 183         __sh_tmu_disable(ch);
 184
 185         dev_pm_syscore_device(&ch->tmu->pdev->dev, false);
 186         pm_runtime_put(&ch->tmu->pdev->dev);
 187 }
 188
 189 static void sh_tmu_set_next(struct sh_tmu_channel *ch, unsigned long delta,
 190                             int periodic)
 191 {
 192         /* stop timer */
 193         sh_tmu_start_stop_ch(ch, 0);
 194
 195         /* acknowledge interrupt */
 196         sh_tmu_read(ch, TCR);
 197
 198         /* enable interrupt */
 199         sh_tmu_write(ch, TCR, 0x0020);
 200
 201         /* reload delta value in case of periodic timer */
 202         if (periodic)
 203                 sh_tmu_write(ch, TCOR, delta);
 204         else
 205                 sh_tmu_write(ch, TCOR, 0xffffffff);
 206
 207         sh_tmu_write(ch, TCNT, delta);
 208
 209         /* start timer */
 210         sh_tmu_start_stop_ch(ch, 1);
 211 }
 212
 213 static irqreturn_t sh_tmu_interrupt(int irq, void *dev_id)
 214 {
 215         struct sh_tmu_channel *ch = dev_id;
 216
 217         /* disable or acknowledge interrupt */
 218         if (ch->ced.mode == CLOCK_EVT_MODE_ONESHOT)
 219                 sh_tmu_write(ch, TCR, 0x0000);
 220         else
 221                 sh_tmu_write(ch, TCR, 0x0020);
 222
 223         /* notify clockevent layer */
 224         ch->ced.event_handler(&ch->ced);
 225         return IRQ_HANDLED;
 226 }
 227
 228 static struct sh_tmu_channel *cs_to_sh_tmu(struct clocksource *cs)
 229 {
 230         return container_of(cs, struct sh_tmu_channel, cs);
 231 }
 232
 233 static cycle_t sh_tmu_clocksource_read(struct clocksource *cs)
 234 {
 235         struct sh_tmu_channel *ch = cs_to_sh_tmu(cs);
 236
 237         return sh_tmu_read(ch, TCNT) ^ 0xffffffff;
 238 }
 239
 240 static int sh_tmu_clocksource_enable(struct clocksource *cs)
 241 {
 242         struct sh_tmu_channel *ch = cs_to_sh_tmu(cs);
 243         int ret;
 244
 245         if (WARN_ON(ch->cs_enabled))
 246                 return 0;
 247
 248         ret = sh_tmu_enable(ch);
 249         if (!ret) {
 250                 __clocksource_updatefreq_hz(cs, ch->rate);
 251                 ch->cs_enabled = true;
 252         }
 253
 254         return ret;
 255 }
 256
 257 static void sh_tmu_clocksource_disable(struct clocksource *cs)
 258 {
 259         struct sh_tmu_channel *ch = cs_to_sh_tmu(cs);
 260
 261         if (WARN_ON(!ch->cs_enabled))
 262                 return;
 263
 264         sh_tmu_disable(ch);
 265         ch->cs_enabled = false;
 266 }
 267
 268 static void sh_tmu_clocksource_suspend(struct clocksource *cs)
 269 {
 270         struct sh_tmu_channel *ch = cs_to_sh_tmu(cs);
 271
 272         if (!ch->cs_enabled)
 273                 return;
 274
 275         if (--ch->enable_count == 0) {
 276                 __sh_tmu_disable(ch);
 277                 pm_genpd_syscore_poweroff(&ch->tmu->pdev->dev);
 278         }
 279 }
 280
 281 static void sh_tmu_clocksource_resume(struct clocksource *cs)
 282 {
 283         struct sh_tmu_channel *ch = cs_to_sh_tmu(cs);
 284
 285         if (!ch->cs_enabled)
 286                 return;
 287
 288         if (ch->enable_count++ == 0) {
 289                 pm_genpd_syscore_poweron(&ch->tmu->pdev->dev);
 290                 __sh_tmu_enable(ch);
 291         }
 292 }
 293
 294 static int sh_tmu_register_clocksource(struct sh_tmu_channel *ch,
 295                                        char *name, unsigned long rating)
 296 {
 297         struct clocksource *cs = &ch->cs;
 298
 299         cs->name = name;
 300         cs->rating = rating;
 301         cs->read = sh_tmu_clocksource_read;
 302         cs->enable = sh_tmu_clocksource_enable;
 303         cs->disable = sh_tmu_clocksource_disable;
 304         cs->suspend = sh_tmu_clocksource_suspend;
 305         cs->resume = sh_tmu_clocksource_resume;
 306         cs->mask = CLOCKSOURCE_MASK(32);
 307         cs->flags = CLOCK_SOURCE_IS_CONTINUOUS;
 308
 309         dev_info(&ch->tmu->pdev->dev, "used as clock source\n");
 310
 311         /* Register with dummy 1 Hz value, gets updated in ->enable() */
 312         clocksource_register_hz(cs, 1);
 313         return 0;
 314 }
 315
 316 static struct sh_tmu_channel *ced_to_sh_tmu(struct clock_event_device *ced)
 317 {
 318         return container_of(ced, struct sh_tmu_channel, ced);
 319 }
 320
 321 static void sh_tmu_clock_event_start(struct sh_tmu_channel *ch, int periodic)
 322 {
 323         struct clock_event_device *ced = &ch->ced;
 324
 325         sh_tmu_enable(ch);
 326
 327         clockevents_config(ced, ch->rate);
 328
 329         if (periodic) {
 330                 ch->periodic = (ch->rate + HZ/2) / HZ;
 331                 sh_tmu_set_next(ch, ch->periodic, 1);
 332         }
 333 }
 334
 335 static void sh_tmu_clock_event_mode(enum clock_event_mode mode,
 336                                     struct clock_event_device *ced)
 337 {
 338         struct sh_tmu_channel *ch = ced_to_sh_tmu(ced);
 339         int disabled = 0;
 340
 341         /* deal with old setting first */
 342         switch (ced->mode) {
 343         case CLOCK_EVT_MODE_PERIODIC:
 344         case CLOCK_EVT_MODE_ONESHOT:
 345                 sh_tmu_disable(ch);
 346                 disabled = 1;
 347                 break;
 348         default:
 349                 break;
 350         }
 351
 352         switch (mode) {
 353         case CLOCK_EVT_MODE_PERIODIC:
 354                 dev_info(&ch->tmu->pdev->dev,
 355                          "used for periodic clock events\n");
 356                 sh_tmu_clock_event_start(ch, 1);
 357                 break;
 358         case CLOCK_EVT_MODE_ONESHOT:
 359                 dev_info(&ch->tmu->pdev->dev,
 360                          "used for oneshot clock events\n");
 361                 sh_tmu_clock_event_start(ch, 0);
 362                 break;
 363         case CLOCK_EVT_MODE_UNUSED:
 364                 if (!disabled)
 365                         sh_tmu_disable(ch);
 366                 break;
 367         case CLOCK_EVT_MODE_SHUTDOWN:
 368         default:
 369                 break;
 370         }
 371 }
 372
 373 static int sh_tmu_clock_event_next(unsigned long delta,
 374                                    struct clock_event_device *ced)
 375 {
 376         struct sh_tmu_channel *ch = ced_to_sh_tmu(ced);
 377
 378         BUG_ON(ced->mode != CLOCK_EVT_MODE_ONESHOT);
 379
 380         /* program new delta value */
 381         sh_tmu_set_next(ch, delta, 0);
 382         return 0;
 383 }
 384
 385 static void sh_tmu_clock_event_suspend(struct clock_event_device *ced)
 386 {
 387         pm_genpd_syscore_poweroff(&ced_to_sh_tmu(ced)->tmu->pdev->dev);
 388 }
 389
 390 static void sh_tmu_clock_event_resume(struct clock_event_device *ced)
 391 {
 392         pm_genpd_syscore_poweron(&ced_to_sh_tmu(ced)->tmu->pdev->dev);
 393 }
 394
 395 static void sh_tmu_register_clockevent(struct sh_tmu_channel *ch,
 396                                        char *name, unsigned long rating)
 397 {
 398         struct clock_event_device *ced = &ch->ced;
 399         int ret;
 400
 401         memset(ced, 0, sizeof(*ced));
 402
 403         ced->name = name;
 404         ced->features = CLOCK_EVT_FEAT_PERIODIC;
 405         ced->features |= CLOCK_EVT_FEAT_ONESHOT;
 406         ced->rating = rating;
 407         ced->cpumask = cpumask_of(0);
 408         ced->set_next_event = sh_tmu_clock_event_next;
 409         ced->set_mode = sh_tmu_clock_event_mode;
 410         ced->suspend = sh_tmu_clock_event_suspend;
 411         ced->resume = sh_tmu_clock_event_resume;
 412
 413         dev_info(&ch->tmu->pdev->dev, "used for clock events\n");
 414
 415         clockevents_config_and_register(ced, 1, 0x300, 0xffffffff);
 416
 417         ret = request_irq(ch->irq, sh_tmu_interrupt,
 418                           IRQF_TIMER | IRQF_IRQPOLL | IRQF_NOBALANCING,
 419                           dev_name(&ch->tmu->pdev->dev), ch);
 420         if (ret) {
 421                 dev_err(&ch->tmu->pdev->dev, "failed to request irq %d\n",
 422                         ch->irq);
 423                 return;
 424         }
 425 }
 426
 427 static int sh_tmu_register(struct sh_tmu_channel *ch, char *name,
 428                     unsigned long clockevent_rating,
 429                     unsigned long clocksource_rating)
 430 {
 431         if (clockevent_rating)
 432                 sh_tmu_register_clockevent(ch, name, clockevent_rating);
 433         else if (clocksource_rating)
 434                 sh_tmu_register_clocksource(ch, name, clocksource_rating);
 435
 436         return 0;
 437 }
 438
 439 static int sh_tmu_channel_setup(struct sh_tmu_channel *ch,
 440                                 struct sh_tmu_device *tmu)
 441 {
 442         struct sh_timer_config *cfg = tmu->pdev->dev.platform_data;
 443
 444         memset(ch, 0, sizeof(*ch));
 445         ch->tmu = tmu;
 446
 447         ch->irq = platform_get_irq(tmu->pdev, 0);
 448         if (ch->irq < 0) {
 449                 dev_err(&tmu->pdev->dev, "failed to get irq\n");
 450                 return ch->irq;
 451         }
 452
 453         ch->cs_enabled = false;
 454         ch->enable_count = 0;
 455
 456         return sh_tmu_register(ch, (char *)dev_name(&tmu->pdev->dev),
 457                                cfg->clockevent_rating,
 458                                cfg->clocksource_rating);
 459 }
 460
 461 static int sh_tmu_setup(struct sh_tmu_device *tmu, struct platform_device *pdev)
 462 {
 463         struct sh_timer_config *cfg = pdev->dev.platform_data;
 464         struct resource *res;
 465         int ret;
 466         ret = -ENXIO;
 467
 468         memset(tmu, 0, sizeof(*tmu));
 469         tmu->pdev = pdev;
 470
 471         if (!cfg) {
 472                 dev_err(&tmu->pdev->dev, "missing platform data\n");
 473                 goto err0;
 474         }
 475
 476         platform_set_drvdata(pdev, tmu);
 477
 478         res = platform_get_resource(tmu->pdev, IORESOURCE_MEM, 0);
 479         if (!res) {
 480                 dev_err(&tmu->pdev->dev, "failed to get I/O memory\n");
 481                 goto err0;
 482         }
 483
 484         /* map memory, let mapbase point to our channel */
 485         tmu->mapbase = ioremap_nocache(res->start, resource_size(res));
 486         if (tmu->mapbase == NULL) {
 487                 dev_err(&tmu->pdev->dev, "failed to remap I/O memory\n");
 488                 goto err0;
 489         }
 490
 491         /* get hold of clock */
 492         tmu->clk = clk_get(&tmu->pdev->dev, "tmu_fck");
 493         if (IS_ERR(tmu->clk)) {
 494                 dev_err(&tmu->pdev->dev, "cannot get clock\n");
 495                 ret = PTR_ERR(tmu->clk);
 496                 goto err1;
 497         }
 498
 499         ret = clk_prepare(tmu->clk);
 500         if (ret < 0)
 501                 goto err2;
 502
 503         ret = sh_tmu_channel_setup(&tmu->channel, tmu);
 504         if (ret < 0)
 505                 goto err3;
 506
 507         return 0;
 508
 509  err3:
 510         clk_unprepare(tmu->clk);
 511  err2:
 512         clk_put(tmu->clk);
 513  err1:
 514         iounmap(tmu->mapbase);
 515  err0:
 516         return ret;
 517 }
 518
 519 static int sh_tmu_probe(struct platform_device *pdev)
 520 {
 521         struct sh_tmu_device *tmu = platform_get_drvdata(pdev);
 522         struct sh_timer_config *cfg = pdev->dev.platform_data;
 523         int ret;
 524
 525         if (!is_early_platform_device(pdev)) {
 526                 pm_runtime_set_active(&pdev->dev);
 527                 pm_runtime_enable(&pdev->dev);
 528         }
 529
 530         if (tmu) {
 531                 dev_info(&pdev->dev, "kept as earlytimer\n");
 532                 goto out;
 533         }
 534
 535         tmu = kmalloc(sizeof(*tmu), GFP_KERNEL);
 536         if (tmu == NULL) {
 537                 dev_err(&pdev->dev, "failed to allocate driver data\n");
 538                 return -ENOMEM;
 539         }
 540
 541         ret = sh_tmu_setup(tmu, pdev);
 542         if (ret) {
 543                 kfree(tmu);
 544                 pm_runtime_idle(&pdev->dev);
 545                 return ret;
 546         }
 547         if (is_early_platform_device(pdev))
 548                 return 0;
 549
 550  out:
 551         if (cfg->clockevent_rating || cfg->clocksource_rating)
 552                 pm_runtime_irq_safe(&pdev->dev);
 553         else
 554                 pm_runtime_idle(&pdev->dev);
 555
 556         return 0;
 557 }
 558
 559 static int sh_tmu_remove(struct platform_device *pdev)
 560 {
 561         return -EBUSY; /* cannot unregister clockevent and clocksource */
 562 }
 563
 564 static struct platform_driver sh_tmu_device_driver = {
 565         .probe          = sh_tmu_probe,
 566         .remove         = sh_tmu_remove,
 567         .driver         = {
 568                 .name   = "sh_tmu",
 569         }
 570 };
 571
 572 static int __init sh_tmu_init(void)
 573 {
 574         return platform_driver_register(&sh_tmu_device_driver);
 575 }
 576
 577 static void __exit sh_tmu_exit(void)
 578 {
 579         platform_driver_unregister(&sh_tmu_device_driver);
 580 }
 581
 582 early_platform_init("earlytimer", &sh_tmu_device_driver);
 583 subsys_initcall(sh_tmu_init);
 584 module_exit(sh_tmu_exit);
 585
 586 MODULE_AUTHOR("Magnus Damm");
 587 MODULE_DESCRIPTION("SuperH TMU Timer Driver");
 588 MODULE_LICENSE("GPL v2");