drivers/clocksource/sh_tmu.c

   1 /*
   2  * SuperH Timer Support - TMU
   3  *
   4  *  Copyright (C) 2009 Magnus Damm
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  18  */
  19
  20 #include <linux/init.h>
  21 #include <linux/platform_device.h>
  22 #include <linux/spinlock.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/ioport.h>
  25 #include <linux/delay.h>
  26 #include <linux/io.h>
  27 #include <linux/clk.h>
  28 #include <linux/irq.h>
  29 #include <linux/err.h>
  30 #include <linux/clocksource.h>
  31 #include <linux/clockchips.h>
  32 #include <linux/sh_timer.h>
  33 #include <linux/slab.h>
  34 #include <linux/module.h>
  35 #include <linux/pm_domain.h>
  36 #include <linux/pm_runtime.h>
  37
  38 struct sh_tmu_device;
  39
  40 struct sh_tmu_channel {
  41         struct sh_tmu_device *tmu;
  42         unsigned int index;
  43
  44         void __iomem *base;
  45         int irq;
  46
  47         unsigned long rate;
  48         unsigned long periodic;
  49         struct clock_event_device ced;
  50         struct clocksource cs;
  51         bool cs_enabled;
  52         unsigned int enable_count;
  53 };
  54
  55 struct sh_tmu_device {
  56         struct platform_device *pdev;
  57
  58         void __iomem *mapbase;
  59         struct clk *clk;
  60
  61         struct sh_tmu_channel *channels;
  62         unsigned int num_channels;
  63 };
  64
  65 static DEFINE_RAW_SPINLOCK(sh_tmu_lock);
  66
  67 #define TSTR -1 /* shared register */
  68 #define TCOR  0 /* channel register */
  69 #define TCNT 1 /* channel register */
  70 #define TCR 2 /* channel register */
  71
  72 static inline unsigned long sh_tmu_read(struct sh_tmu_channel *ch, int reg_nr)
  73 {
  74         unsigned long offs;
  75
  76         if (reg_nr == TSTR)
  77                 return ioread8(ch->tmu->mapbase);
  78
  79         offs = reg_nr << 2;
  80
  81         if (reg_nr == TCR)
  82                 return ioread16(ch->base + offs);
  83         else
  84                 return ioread32(ch->base + offs);
  85 }
  86
  87 static inline void sh_tmu_write(struct sh_tmu_channel *ch, int reg_nr,
  88                                 unsigned long value)
  89 {
  90         unsigned long offs;
  91
  92         if (reg_nr == TSTR) {
  93                 iowrite8(value, ch->tmu->mapbase);
  94                 return;
  95         }
  96
  97         offs = reg_nr << 2;
  98
  99         if (reg_nr == TCR)
 100                 iowrite16(value, ch->base + offs);
 101         else
 102                 iowrite32(value, ch->base + offs);
 103 }
 104
 105 static void sh_tmu_start_stop_ch(struct sh_tmu_channel *ch, int start)
 106 {
 107         unsigned long flags, value;
 108
 109         /* start stop register shared by multiple timer channels */
 110         raw_spin_lock_irqsave(&sh_tmu_lock, flags);
 111         value = sh_tmu_read(ch, TSTR);
 112
 113         if (start)
 114                 value |= 1 << ch->index;
 115         else
 116                 value &= ~(1 << ch->index);
 117
 118         sh_tmu_write(ch, TSTR, value);
 119         raw_spin_unlock_irqrestore(&sh_tmu_lock, flags);
 120 }
 121
 122 static int __sh_tmu_enable(struct sh_tmu_channel *ch)
 123 {
 124         int ret;
 125
 126         /* enable clock */
 127         ret = clk_enable(ch->tmu->clk);
 128         if (ret) {
 129                 dev_err(&ch->tmu->pdev->dev, "ch%u: cannot enable clock\n",
 130                         ch->index);
 131                 return ret;
 132         }
 133
 134         /* make sure channel is disabled */
 135         sh_tmu_start_stop_ch(ch, 0);
 136
 137         /* maximum timeout */
 138         sh_tmu_write(ch, TCOR, 0xffffffff);
 139         sh_tmu_write(ch, TCNT, 0xffffffff);
 140
 141         /* configure channel to parent clock / 4, irq off */
 142         ch->rate = clk_get_rate(ch->tmu->clk) / 4;
 143         sh_tmu_write(ch, TCR, 0x0000);
 144
 145         /* enable channel */
 146         sh_tmu_start_stop_ch(ch, 1);
 147
 148         return 0;
 149 }
 150
 151 static int sh_tmu_enable(struct sh_tmu_channel *ch)
 152 {
 153         if (ch->enable_count++ > 0)
 154                 return 0;
 155
 156         pm_runtime_get_sync(&ch->tmu->pdev->dev);
 157         dev_pm_syscore_device(&ch->tmu->pdev->dev, true);
 158
 159         return __sh_tmu_enable(ch);
 160 }
 161
 162 static void __sh_tmu_disable(struct sh_tmu_channel *ch)
 163 {
 164         /* disable channel */
 165         sh_tmu_start_stop_ch(ch, 0);
 166
 167         /* disable interrupts in TMU block */
 168         sh_tmu_write(ch, TCR, 0x0000);
 169
 170         /* stop clock */
 171         clk_disable(ch->tmu->clk);
 172 }
 173
 174 static void sh_tmu_disable(struct sh_tmu_channel *ch)
 175 {
 176         if (WARN_ON(ch->enable_count == 0))
 177                 return;
 178
 179         if (--ch->enable_count > 0)
 180                 return;
 181
 182         __sh_tmu_disable(ch);
 183
 184         dev_pm_syscore_device(&ch->tmu->pdev->dev, false);
 185         pm_runtime_put(&ch->tmu->pdev->dev);
 186 }
 187
 188 static void sh_tmu_set_next(struct sh_tmu_channel *ch, unsigned long delta,
 189                             int periodic)
 190 {
 191         /* stop timer */
 192         sh_tmu_start_stop_ch(ch, 0);
 193
 194         /* acknowledge interrupt */
 195         sh_tmu_read(ch, TCR);
 196
 197         /* enable interrupt */
 198         sh_tmu_write(ch, TCR, 0x0020);
 199
 200         /* reload delta value in case of periodic timer */
 201         if (periodic)
 202                 sh_tmu_write(ch, TCOR, delta);
 203         else
 204                 sh_tmu_write(ch, TCOR, 0xffffffff);
 205
 206         sh_tmu_write(ch, TCNT, delta);
 207
 208         /* start timer */
 209         sh_tmu_start_stop_ch(ch, 1);
 210 }
 211
 212 static irqreturn_t sh_tmu_interrupt(int irq, void *dev_id)
 213 {
 214         struct sh_tmu_channel *ch = dev_id;
 215
 216         /* disable or acknowledge interrupt */
 217         if (ch->ced.mode == CLOCK_EVT_MODE_ONESHOT)
 218                 sh_tmu_write(ch, TCR, 0x0000);
 219         else
 220                 sh_tmu_write(ch, TCR, 0x0020);
 221
 222         /* notify clockevent layer */
 223         ch->ced.event_handler(&ch->ced);
 224         return IRQ_HANDLED;
 225 }
 226
 227 static struct sh_tmu_channel *cs_to_sh_tmu(struct clocksource *cs)
 228 {
 229         return container_of(cs, struct sh_tmu_channel, cs);
 230 }
 231
 232 static cycle_t sh_tmu_clocksource_read(struct clocksource *cs)
 233 {
 234         struct sh_tmu_channel *ch = cs_to_sh_tmu(cs);
 235
 236         return sh_tmu_read(ch, TCNT) ^ 0xffffffff;
 237 }
 238
 239 static int sh_tmu_clocksource_enable(struct clocksource *cs)
 240 {
 241         struct sh_tmu_channel *ch = cs_to_sh_tmu(cs);
 242         int ret;
 243
 244         if (WARN_ON(ch->cs_enabled))
 245                 return 0;
 246
 247         ret = sh_tmu_enable(ch);
 248         if (!ret) {
 249                 __clocksource_updatefreq_hz(cs, ch->rate);
 250                 ch->cs_enabled = true;
 251         }
 252
 253         return ret;
 254 }
 255
 256 static void sh_tmu_clocksource_disable(struct clocksource *cs)
 257 {
 258         struct sh_tmu_channel *ch = cs_to_sh_tmu(cs);
 259
 260         if (WARN_ON(!ch->cs_enabled))
 261                 return;
 262
 263         sh_tmu_disable(ch);
 264         ch->cs_enabled = false;
 265 }
 266
 267 static void sh_tmu_clocksource_suspend(struct clocksource *cs)
 268 {
 269         struct sh_tmu_channel *ch = cs_to_sh_tmu(cs);
 270
 271         if (!ch->cs_enabled)
 272                 return;
 273
 274         if (--ch->enable_count == 0) {
 275                 __sh_tmu_disable(ch);
 276                 pm_genpd_syscore_poweroff(&ch->tmu->pdev->dev);
 277         }
 278 }
 279
 280 static void sh_tmu_clocksource_resume(struct clocksource *cs)
 281 {
 282         struct sh_tmu_channel *ch = cs_to_sh_tmu(cs);
 283
 284         if (!ch->cs_enabled)
 285                 return;
 286
 287         if (ch->enable_count++ == 0) {
 288                 pm_genpd_syscore_poweron(&ch->tmu->pdev->dev);
 289                 __sh_tmu_enable(ch);
 290         }
 291 }
 292
 293 static int sh_tmu_register_clocksource(struct sh_tmu_channel *ch,
 294                                        const char *name, unsigned long rating)
 295 {
 296         struct clocksource *cs = &ch->cs;
 297
 298         cs->name = name;
 299         cs->rating = rating;
 300         cs->read = sh_tmu_clocksource_read;
 301         cs->enable = sh_tmu_clocksource_enable;
 302         cs->disable = sh_tmu_clocksource_disable;
 303         cs->suspend = sh_tmu_clocksource_suspend;
 304         cs->resume = sh_tmu_clocksource_resume;
 305         cs->mask = CLOCKSOURCE_MASK(32);
 306         cs->flags = CLOCK_SOURCE_IS_CONTINUOUS;
 307
 308         dev_info(&ch->tmu->pdev->dev, "ch%u: used as clock source\n",
 309                  ch->index);
 310
 311         /* Register with dummy 1 Hz value, gets updated in ->enable() */
 312         clocksource_register_hz(cs, 1);
 313         return 0;
 314 }
 315
 316 static struct sh_tmu_channel *ced_to_sh_tmu(struct clock_event_device *ced)
 317 {
 318         return container_of(ced, struct sh_tmu_channel, ced);
 319 }
 320
 321 static void sh_tmu_clock_event_start(struct sh_tmu_channel *ch, int periodic)
 322 {
 323         struct clock_event_device *ced = &ch->ced;
 324
 325         sh_tmu_enable(ch);
 326
 327         clockevents_config(ced, ch->rate);
 328
 329         if (periodic) {
 330                 ch->periodic = (ch->rate + HZ/2) / HZ;
 331                 sh_tmu_set_next(ch, ch->periodic, 1);
 332         }
 333 }
 334
 335 static void sh_tmu_clock_event_mode(enum clock_event_mode mode,
 336                                     struct clock_event_device *ced)
 337 {
 338         struct sh_tmu_channel *ch = ced_to_sh_tmu(ced);
 339         int disabled = 0;
 340
 341         /* deal with old setting first */
 342         switch (ced->mode) {
 343         case CLOCK_EVT_MODE_PERIODIC:
 344         case CLOCK_EVT_MODE_ONESHOT:
 345                 sh_tmu_disable(ch);
 346                 disabled = 1;
 347                 break;
 348         default:
 349                 break;
 350         }
 351
 352         switch (mode) {
 353         case CLOCK_EVT_MODE_PERIODIC:
 354                 dev_info(&ch->tmu->pdev->dev,
 355                          "ch%u: used for periodic clock events\n", ch->index);
 356                 sh_tmu_clock_event_start(ch, 1);
 357                 break;
 358         case CLOCK_EVT_MODE_ONESHOT:
 359                 dev_info(&ch->tmu->pdev->dev,
 360                          "ch%u: used for oneshot clock events\n", ch->index);
 361                 sh_tmu_clock_event_start(ch, 0);
 362                 break;
 363         case CLOCK_EVT_MODE_UNUSED:
 364                 if (!disabled)
 365                         sh_tmu_disable(ch);
 366                 break;
 367         case CLOCK_EVT_MODE_SHUTDOWN:
 368         default:
 369                 break;
 370         }
 371 }
 372
 373 static int sh_tmu_clock_event_next(unsigned long delta,
 374                                    struct clock_event_device *ced)
 375 {
 376         struct sh_tmu_channel *ch = ced_to_sh_tmu(ced);
 377
 378         BUG_ON(ced->mode != CLOCK_EVT_MODE_ONESHOT);
 379
 380         /* program new delta value */
 381         sh_tmu_set_next(ch, delta, 0);
 382         return 0;
 383 }
 384
 385 static void sh_tmu_clock_event_suspend(struct clock_event_device *ced)
 386 {
 387         pm_genpd_syscore_poweroff(&ced_to_sh_tmu(ced)->tmu->pdev->dev);
 388 }
 389
 390 static void sh_tmu_clock_event_resume(struct clock_event_device *ced)
 391 {
 392         pm_genpd_syscore_poweron(&ced_to_sh_tmu(ced)->tmu->pdev->dev);
 393 }
 394
 395 static void sh_tmu_register_clockevent(struct sh_tmu_channel *ch,
 396                                        const char *name, unsigned long rating)
 397 {
 398         struct clock_event_device *ced = &ch->ced;
 399         int ret;
 400
 401         ced->name = name;
 402         ced->features = CLOCK_EVT_FEAT_PERIODIC;
 403         ced->features |= CLOCK_EVT_FEAT_ONESHOT;
 404         ced->rating = rating;
 405         ced->cpumask = cpumask_of(0);
 406         ced->set_next_event = sh_tmu_clock_event_next;
 407         ced->set_mode = sh_tmu_clock_event_mode;
 408         ced->suspend = sh_tmu_clock_event_suspend;
 409         ced->resume = sh_tmu_clock_event_resume;
 410
 411         dev_info(&ch->tmu->pdev->dev, "ch%u: used for clock events\n",
 412                  ch->index);
 413
 414         clockevents_config_and_register(ced, 1, 0x300, 0xffffffff);
 415
 416         ret = request_irq(ch->irq, sh_tmu_interrupt,
 417                           IRQF_TIMER | IRQF_IRQPOLL | IRQF_NOBALANCING,
 418                           dev_name(&ch->tmu->pdev->dev), ch);
 419         if (ret) {
 420                 dev_err(&ch->tmu->pdev->dev, "ch%u: failed to request irq %d\n",
 421                         ch->index, ch->irq);
 422                 return;
 423         }
 424 }
 425
 426 static int sh_tmu_register(struct sh_tmu_channel *ch, const char *name,
 427                     unsigned long clockevent_rating,
 428                     unsigned long clocksource_rating)
 429 {
 430         if (clockevent_rating)
 431                 sh_tmu_register_clockevent(ch, name, clockevent_rating);
 432         else if (clocksource_rating)
 433                 sh_tmu_register_clocksource(ch, name, clocksource_rating);
 434
 435         return 0;
 436 }
 437
 438 static int sh_tmu_channel_setup(struct sh_tmu_channel *ch,
 439                                 struct sh_tmu_device *tmu)
 440 {
 441         struct sh_timer_config *cfg = tmu->pdev->dev.platform_data;
 442
 443         ch->tmu = tmu;
 444
 445         /*
 446          * The SH3 variant (SH770x, SH7705, SH7710 and SH7720) maps channel
 447          * registers blocks at base + 2 + 12 * index, while all other variants
 448          * map them at base + 4 + 12 * index. We can compute the index by just
 449          * dividing by 12, the 2 bytes or 4 bytes offset being hidden by the
 450          * integer division.
 451          */
 452         ch->index = cfg->channel_offset / 12;
 453
 454         ch->irq = platform_get_irq(tmu->pdev, 0);
 455         if (ch->irq < 0) {
 456                 dev_err(&tmu->pdev->dev, "ch%u: failed to get irq\n",
 457                         ch->index);
 458                 return ch->irq;
 459         }
 460
 461         ch->cs_enabled = false;
 462         ch->enable_count = 0;
 463
 464         return sh_tmu_register(ch, dev_name(&tmu->pdev->dev),
 465                                cfg->clockevent_rating,
 466                                cfg->clocksource_rating);
 467 }
 468
 469 static int sh_tmu_setup(struct sh_tmu_device *tmu, struct platform_device *pdev)
 470 {
 471         struct sh_timer_config *cfg = pdev->dev.platform_data;
 472         struct resource *res;
 473         void __iomem *base;
 474         int ret;
 475         ret = -ENXIO;
 476
 477         tmu->pdev = pdev;
 478
 479         if (!cfg) {
 480                 dev_err(&tmu->pdev->dev, "missing platform data\n");
 481                 goto err0;
 482         }
 483
 484         platform_set_drvdata(pdev, tmu);
 485
 486         res = platform_get_resource(tmu->pdev, IORESOURCE_MEM, 0);
 487         if (!res) {
 488                 dev_err(&tmu->pdev->dev, "failed to get I/O memory\n");
 489                 goto err0;
 490         }
 491
 492         /*
 493          * Map memory, let base point to our channel and mapbase to the
 494          * start/stop shared register.
 495          */
 496         base = ioremap_nocache(res->start, resource_size(res));
 497         if (base == NULL) {
 498                 dev_err(&tmu->pdev->dev, "failed to remap I/O memory\n");
 499                 goto err0;
 500         }
 501
 502         tmu->mapbase = base - cfg->channel_offset;
 503
 504         /* get hold of clock */
 505         tmu->clk = clk_get(&tmu->pdev->dev, "tmu_fck");
 506         if (IS_ERR(tmu->clk)) {
 507                 dev_err(&tmu->pdev->dev, "cannot get clock\n");
 508                 ret = PTR_ERR(tmu->clk);
 509                 goto err1;
 510         }
 511
 512         ret = clk_prepare(tmu->clk);
 513         if (ret < 0)
 514                 goto err2;
 515
 516         tmu->channels = kzalloc(sizeof(*tmu->channels), GFP_KERNEL);
 517         if (tmu->channels == NULL) {
 518                 ret = -ENOMEM;
 519                 goto err3;
 520         }
 521
 522         tmu->num_channels = 1;
 523
 524         tmu->channels[0].base = base;
 525
 526         ret = sh_tmu_channel_setup(&tmu->channels[0], tmu);
 527         if (ret < 0)
 528                 goto err3;
 529
 530         return 0;
 531
 532  err3:
 533         kfree(tmu->channels);
 534         clk_unprepare(tmu->clk);
 535  err2:
 536         clk_put(tmu->clk);
 537  err1:
 538         iounmap(base);
 539  err0:
 540         return ret;
 541 }
 542
 543 static int sh_tmu_probe(struct platform_device *pdev)
 544 {
 545         struct sh_tmu_device *tmu = platform_get_drvdata(pdev);
 546         struct sh_timer_config *cfg = pdev->dev.platform_data;
 547         int ret;
 548
 549         if (!is_early_platform_device(pdev)) {
 550                 pm_runtime_set_active(&pdev->dev);
 551                 pm_runtime_enable(&pdev->dev);
 552         }
 553
 554         if (tmu) {
 555                 dev_info(&pdev->dev, "kept as earlytimer\n");
 556                 goto out;
 557         }
 558
 559         tmu = kzalloc(sizeof(*tmu), GFP_KERNEL);
 560         if (tmu == NULL) {
 561                 dev_err(&pdev->dev, "failed to allocate driver data\n");
 562                 return -ENOMEM;
 563         }
 564
 565         ret = sh_tmu_setup(tmu, pdev);
 566         if (ret) {
 567                 kfree(tmu);
 568                 pm_runtime_idle(&pdev->dev);
 569                 return ret;
 570         }
 571         if (is_early_platform_device(pdev))
 572                 return 0;
 573
 574  out:
 575         if (cfg->clockevent_rating || cfg->clocksource_rating)
 576                 pm_runtime_irq_safe(&pdev->dev);
 577         else
 578                 pm_runtime_idle(&pdev->dev);
 579
 580         return 0;
 581 }
 582
 583 static int sh_tmu_remove(struct platform_device *pdev)
 584 {
 585         return -EBUSY; /* cannot unregister clockevent and clocksource */
 586 }
 587
 588 static struct platform_driver sh_tmu_device_driver = {
 589         .probe          = sh_tmu_probe,
 590         .remove         = sh_tmu_remove,
 591         .driver         = {
 592                 .name   = "sh_tmu",
 593         }
 594 };
 595
 596 static int __init sh_tmu_init(void)
 597 {
 598         return platform_driver_register(&sh_tmu_device_driver);
 599 }
 600
 601 static void __exit sh_tmu_exit(void)
 602 {
 603         platform_driver_unregister(&sh_tmu_device_driver);
 604 }
 605
 606 early_platform_init("earlytimer", &sh_tmu_device_driver);
 607 subsys_initcall(sh_tmu_init);
 608 module_exit(sh_tmu_exit);
 609
 610 MODULE_AUTHOR("Magnus Damm");
 611 MODULE_DESCRIPTION("SuperH TMU Timer Driver");
 612 MODULE_LICENSE("GPL v2");