drivers/clocksource/sh_tmu.c

   1 /*
   2  * SuperH Timer Support - TMU
   3  *
   4  *  Copyright (C) 2009 Magnus Damm
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  18  */
  19
  20 #include <linux/init.h>
  21 #include <linux/platform_device.h>
  22 #include <linux/spinlock.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/ioport.h>
  25 #include <linux/delay.h>
  26 #include <linux/io.h>
  27 #include <linux/clk.h>
  28 #include <linux/irq.h>
  29 #include <linux/err.h>
  30 #include <linux/clocksource.h>
  31 #include <linux/clockchips.h>
  32 #include <linux/sh_timer.h>
  33 #include <linux/slab.h>
  34 #include <linux/module.h>
  35 #include <linux/pm_domain.h>
  36 #include <linux/pm_runtime.h>
  37
  38 struct sh_tmu_device;
  39
  40 struct sh_tmu_channel {
  41         struct sh_tmu_device *tmu;
  42         unsigned int index;
  43
  44         void __iomem *base;
  45         int irq;
  46
  47         unsigned long rate;
  48         unsigned long periodic;
  49         struct clock_event_device ced;
  50         struct clocksource cs;
  51         bool cs_enabled;
  52         unsigned int enable_count;
  53 };
  54
  55 struct sh_tmu_device {
  56         struct platform_device *pdev;
  57
  58         void __iomem *mapbase;
  59         struct clk *clk;
  60
  61         struct sh_tmu_channel channel;
  62 };
  63
  64 static DEFINE_RAW_SPINLOCK(sh_tmu_lock);
  65
  66 #define TSTR -1 /* shared register */
  67 #define TCOR  0 /* channel register */
  68 #define TCNT 1 /* channel register */
  69 #define TCR 2 /* channel register */
  70
  71 static inline unsigned long sh_tmu_read(struct sh_tmu_channel *ch, int reg_nr)
  72 {
  73         unsigned long offs;
  74
  75         if (reg_nr == TSTR)
  76                 return ioread8(ch->tmu->mapbase);
  77
  78         offs = reg_nr << 2;
  79
  80         if (reg_nr == TCR)
  81                 return ioread16(ch->base + offs);
  82         else
  83                 return ioread32(ch->base + offs);
  84 }
  85
  86 static inline void sh_tmu_write(struct sh_tmu_channel *ch, int reg_nr,
  87                                 unsigned long value)
  88 {
  89         unsigned long offs;
  90
  91         if (reg_nr == TSTR) {
  92                 iowrite8(value, ch->tmu->mapbase);
  93                 return;
  94         }
  95
  96         offs = reg_nr << 2;
  97
  98         if (reg_nr == TCR)
  99                 iowrite16(value, ch->base + offs);
 100         else
 101                 iowrite32(value, ch->base + offs);
 102 }
 103
 104 static void sh_tmu_start_stop_ch(struct sh_tmu_channel *ch, int start)
 105 {
 106         unsigned long flags, value;
 107
 108         /* start stop register shared by multiple timer channels */
 109         raw_spin_lock_irqsave(&sh_tmu_lock, flags);
 110         value = sh_tmu_read(ch, TSTR);
 111
 112         if (start)
 113                 value |= 1 << ch->index;
 114         else
 115                 value &= ~(1 << ch->index);
 116
 117         sh_tmu_write(ch, TSTR, value);
 118         raw_spin_unlock_irqrestore(&sh_tmu_lock, flags);
 119 }
 120
 121 static int __sh_tmu_enable(struct sh_tmu_channel *ch)
 122 {
 123         int ret;
 124
 125         /* enable clock */
 126         ret = clk_enable(ch->tmu->clk);
 127         if (ret) {
 128                 dev_err(&ch->tmu->pdev->dev, "ch%u: cannot enable clock\n",
 129                         ch->index);
 130                 return ret;
 131         }
 132
 133         /* make sure channel is disabled */
 134         sh_tmu_start_stop_ch(ch, 0);
 135
 136         /* maximum timeout */
 137         sh_tmu_write(ch, TCOR, 0xffffffff);
 138         sh_tmu_write(ch, TCNT, 0xffffffff);
 139
 140         /* configure channel to parent clock / 4, irq off */
 141         ch->rate = clk_get_rate(ch->tmu->clk) / 4;
 142         sh_tmu_write(ch, TCR, 0x0000);
 143
 144         /* enable channel */
 145         sh_tmu_start_stop_ch(ch, 1);
 146
 147         return 0;
 148 }
 149
 150 static int sh_tmu_enable(struct sh_tmu_channel *ch)
 151 {
 152         if (ch->enable_count++ > 0)
 153                 return 0;
 154
 155         pm_runtime_get_sync(&ch->tmu->pdev->dev);
 156         dev_pm_syscore_device(&ch->tmu->pdev->dev, true);
 157
 158         return __sh_tmu_enable(ch);
 159 }
 160
 161 static void __sh_tmu_disable(struct sh_tmu_channel *ch)
 162 {
 163         /* disable channel */
 164         sh_tmu_start_stop_ch(ch, 0);
 165
 166         /* disable interrupts in TMU block */
 167         sh_tmu_write(ch, TCR, 0x0000);
 168
 169         /* stop clock */
 170         clk_disable(ch->tmu->clk);
 171 }
 172
 173 static void sh_tmu_disable(struct sh_tmu_channel *ch)
 174 {
 175         if (WARN_ON(ch->enable_count == 0))
 176                 return;
 177
 178         if (--ch->enable_count > 0)
 179                 return;
 180
 181         __sh_tmu_disable(ch);
 182
 183         dev_pm_syscore_device(&ch->tmu->pdev->dev, false);
 184         pm_runtime_put(&ch->tmu->pdev->dev);
 185 }
 186
 187 static void sh_tmu_set_next(struct sh_tmu_channel *ch, unsigned long delta,
 188                             int periodic)
 189 {
 190         /* stop timer */
 191         sh_tmu_start_stop_ch(ch, 0);
 192
 193         /* acknowledge interrupt */
 194         sh_tmu_read(ch, TCR);
 195
 196         /* enable interrupt */
 197         sh_tmu_write(ch, TCR, 0x0020);
 198
 199         /* reload delta value in case of periodic timer */
 200         if (periodic)
 201                 sh_tmu_write(ch, TCOR, delta);
 202         else
 203                 sh_tmu_write(ch, TCOR, 0xffffffff);
 204
 205         sh_tmu_write(ch, TCNT, delta);
 206
 207         /* start timer */
 208         sh_tmu_start_stop_ch(ch, 1);
 209 }
 210
 211 static irqreturn_t sh_tmu_interrupt(int irq, void *dev_id)
 212 {
 213         struct sh_tmu_channel *ch = dev_id;
 214
 215         /* disable or acknowledge interrupt */
 216         if (ch->ced.mode == CLOCK_EVT_MODE_ONESHOT)
 217                 sh_tmu_write(ch, TCR, 0x0000);
 218         else
 219                 sh_tmu_write(ch, TCR, 0x0020);
 220
 221         /* notify clockevent layer */
 222         ch->ced.event_handler(&ch->ced);
 223         return IRQ_HANDLED;
 224 }
 225
 226 static struct sh_tmu_channel *cs_to_sh_tmu(struct clocksource *cs)
 227 {
 228         return container_of(cs, struct sh_tmu_channel, cs);
 229 }
 230
 231 static cycle_t sh_tmu_clocksource_read(struct clocksource *cs)
 232 {
 233         struct sh_tmu_channel *ch = cs_to_sh_tmu(cs);
 234
 235         return sh_tmu_read(ch, TCNT) ^ 0xffffffff;
 236 }
 237
 238 static int sh_tmu_clocksource_enable(struct clocksource *cs)
 239 {
 240         struct sh_tmu_channel *ch = cs_to_sh_tmu(cs);
 241         int ret;
 242
 243         if (WARN_ON(ch->cs_enabled))
 244                 return 0;
 245
 246         ret = sh_tmu_enable(ch);
 247         if (!ret) {
 248                 __clocksource_updatefreq_hz(cs, ch->rate);
 249                 ch->cs_enabled = true;
 250         }
 251
 252         return ret;
 253 }
 254
 255 static void sh_tmu_clocksource_disable(struct clocksource *cs)
 256 {
 257         struct sh_tmu_channel *ch = cs_to_sh_tmu(cs);
 258
 259         if (WARN_ON(!ch->cs_enabled))
 260                 return;
 261
 262         sh_tmu_disable(ch);
 263         ch->cs_enabled = false;
 264 }
 265
 266 static void sh_tmu_clocksource_suspend(struct clocksource *cs)
 267 {
 268         struct sh_tmu_channel *ch = cs_to_sh_tmu(cs);
 269
 270         if (!ch->cs_enabled)
 271                 return;
 272
 273         if (--ch->enable_count == 0) {
 274                 __sh_tmu_disable(ch);
 275                 pm_genpd_syscore_poweroff(&ch->tmu->pdev->dev);
 276         }
 277 }
 278
 279 static void sh_tmu_clocksource_resume(struct clocksource *cs)
 280 {
 281         struct sh_tmu_channel *ch = cs_to_sh_tmu(cs);
 282
 283         if (!ch->cs_enabled)
 284                 return;
 285
 286         if (ch->enable_count++ == 0) {
 287                 pm_genpd_syscore_poweron(&ch->tmu->pdev->dev);
 288                 __sh_tmu_enable(ch);
 289         }
 290 }
 291
 292 static int sh_tmu_register_clocksource(struct sh_tmu_channel *ch,
 293                                        const char *name, unsigned long rating)
 294 {
 295         struct clocksource *cs = &ch->cs;
 296
 297         cs->name = name;
 298         cs->rating = rating;
 299         cs->read = sh_tmu_clocksource_read;
 300         cs->enable = sh_tmu_clocksource_enable;
 301         cs->disable = sh_tmu_clocksource_disable;
 302         cs->suspend = sh_tmu_clocksource_suspend;
 303         cs->resume = sh_tmu_clocksource_resume;
 304         cs->mask = CLOCKSOURCE_MASK(32);
 305         cs->flags = CLOCK_SOURCE_IS_CONTINUOUS;
 306
 307         dev_info(&ch->tmu->pdev->dev, "ch%u: used as clock source\n",
 308                  ch->index);
 309
 310         /* Register with dummy 1 Hz value, gets updated in ->enable() */
 311         clocksource_register_hz(cs, 1);
 312         return 0;
 313 }
 314
 315 static struct sh_tmu_channel *ced_to_sh_tmu(struct clock_event_device *ced)
 316 {
 317         return container_of(ced, struct sh_tmu_channel, ced);
 318 }
 319
 320 static void sh_tmu_clock_event_start(struct sh_tmu_channel *ch, int periodic)
 321 {
 322         struct clock_event_device *ced = &ch->ced;
 323
 324         sh_tmu_enable(ch);
 325
 326         clockevents_config(ced, ch->rate);
 327
 328         if (periodic) {
 329                 ch->periodic = (ch->rate + HZ/2) / HZ;
 330                 sh_tmu_set_next(ch, ch->periodic, 1);
 331         }
 332 }
 333
 334 static void sh_tmu_clock_event_mode(enum clock_event_mode mode,
 335                                     struct clock_event_device *ced)
 336 {
 337         struct sh_tmu_channel *ch = ced_to_sh_tmu(ced);
 338         int disabled = 0;
 339
 340         /* deal with old setting first */
 341         switch (ced->mode) {
 342         case CLOCK_EVT_MODE_PERIODIC:
 343         case CLOCK_EVT_MODE_ONESHOT:
 344                 sh_tmu_disable(ch);
 345                 disabled = 1;
 346                 break;
 347         default:
 348                 break;
 349         }
 350
 351         switch (mode) {
 352         case CLOCK_EVT_MODE_PERIODIC:
 353                 dev_info(&ch->tmu->pdev->dev,
 354                          "ch%u: used for periodic clock events\n", ch->index);
 355                 sh_tmu_clock_event_start(ch, 1);
 356                 break;
 357         case CLOCK_EVT_MODE_ONESHOT:
 358                 dev_info(&ch->tmu->pdev->dev,
 359                          "ch%u: used for oneshot clock events\n", ch->index);
 360                 sh_tmu_clock_event_start(ch, 0);
 361                 break;
 362         case CLOCK_EVT_MODE_UNUSED:
 363                 if (!disabled)
 364                         sh_tmu_disable(ch);
 365                 break;
 366         case CLOCK_EVT_MODE_SHUTDOWN:
 367         default:
 368                 break;
 369         }
 370 }
 371
 372 static int sh_tmu_clock_event_next(unsigned long delta,
 373                                    struct clock_event_device *ced)
 374 {
 375         struct sh_tmu_channel *ch = ced_to_sh_tmu(ced);
 376
 377         BUG_ON(ced->mode != CLOCK_EVT_MODE_ONESHOT);
 378
 379         /* program new delta value */
 380         sh_tmu_set_next(ch, delta, 0);
 381         return 0;
 382 }
 383
 384 static void sh_tmu_clock_event_suspend(struct clock_event_device *ced)
 385 {
 386         pm_genpd_syscore_poweroff(&ced_to_sh_tmu(ced)->tmu->pdev->dev);
 387 }
 388
 389 static void sh_tmu_clock_event_resume(struct clock_event_device *ced)
 390 {
 391         pm_genpd_syscore_poweron(&ced_to_sh_tmu(ced)->tmu->pdev->dev);
 392 }
 393
 394 static void sh_tmu_register_clockevent(struct sh_tmu_channel *ch,
 395                                        const char *name, unsigned long rating)
 396 {
 397         struct clock_event_device *ced = &ch->ced;
 398         int ret;
 399
 400         memset(ced, 0, sizeof(*ced));
 401
 402         ced->name = name;
 403         ced->features = CLOCK_EVT_FEAT_PERIODIC;
 404         ced->features |= CLOCK_EVT_FEAT_ONESHOT;
 405         ced->rating = rating;
 406         ced->cpumask = cpumask_of(0);
 407         ced->set_next_event = sh_tmu_clock_event_next;
 408         ced->set_mode = sh_tmu_clock_event_mode;
 409         ced->suspend = sh_tmu_clock_event_suspend;
 410         ced->resume = sh_tmu_clock_event_resume;
 411
 412         dev_info(&ch->tmu->pdev->dev, "ch%u: used for clock events\n",
 413                  ch->index);
 414
 415         clockevents_config_and_register(ced, 1, 0x300, 0xffffffff);
 416
 417         ret = request_irq(ch->irq, sh_tmu_interrupt,
 418                           IRQF_TIMER | IRQF_IRQPOLL | IRQF_NOBALANCING,
 419                           dev_name(&ch->tmu->pdev->dev), ch);
 420         if (ret) {
 421                 dev_err(&ch->tmu->pdev->dev, "ch%u: failed to request irq %d\n",
 422                         ch->index, ch->irq);
 423                 return;
 424         }
 425 }
 426
 427 static int sh_tmu_register(struct sh_tmu_channel *ch, const char *name,
 428                     unsigned long clockevent_rating,
 429                     unsigned long clocksource_rating)
 430 {
 431         if (clockevent_rating)
 432                 sh_tmu_register_clockevent(ch, name, clockevent_rating);
 433         else if (clocksource_rating)
 434                 sh_tmu_register_clocksource(ch, name, clocksource_rating);
 435
 436         return 0;
 437 }
 438
 439 static int sh_tmu_channel_setup(struct sh_tmu_channel *ch,
 440                                 struct sh_tmu_device *tmu)
 441 {
 442         struct sh_timer_config *cfg = tmu->pdev->dev.platform_data;
 443
 444         memset(ch, 0, sizeof(*ch));
 445         ch->tmu = tmu;
 446
 447         /*
 448          * The SH3 variant (SH770x, SH7705, SH7710 and SH7720) maps channel
 449          * registers blocks at base + 2 + 12 * index, while all other variants
 450          * map them at base + 4 + 12 * index. We can compute the index by just
 451          * dividing by 12, the 2 bytes or 4 bytes offset being hidden by the
 452          * integer division.
 453          */
 454         ch->index = cfg->channel_offset / 12;
 455
 456         ch->irq = platform_get_irq(tmu->pdev, 0);
 457         if (ch->irq < 0) {
 458                 dev_err(&tmu->pdev->dev, "ch%u: failed to get irq\n",
 459                         ch->index);
 460                 return ch->irq;
 461         }
 462
 463         ch->cs_enabled = false;
 464         ch->enable_count = 0;
 465
 466         return sh_tmu_register(ch, dev_name(&tmu->pdev->dev),
 467                                cfg->clockevent_rating,
 468                                cfg->clocksource_rating);
 469 }
 470
 471 static int sh_tmu_setup(struct sh_tmu_device *tmu, struct platform_device *pdev)
 472 {
 473         struct sh_timer_config *cfg = pdev->dev.platform_data;
 474         struct resource *res;
 475         int ret;
 476         ret = -ENXIO;
 477
 478         memset(tmu, 0, sizeof(*tmu));
 479         tmu->pdev = pdev;
 480
 481         if (!cfg) {
 482                 dev_err(&tmu->pdev->dev, "missing platform data\n");
 483                 goto err0;
 484         }
 485
 486         platform_set_drvdata(pdev, tmu);
 487
 488         res = platform_get_resource(tmu->pdev, IORESOURCE_MEM, 0);
 489         if (!res) {
 490                 dev_err(&tmu->pdev->dev, "failed to get I/O memory\n");
 491                 goto err0;
 492         }
 493
 494         /*
 495          * Map memory, let channel.base point to our channel and mapbase to the
 496          * start/stop shared register.
 497          */
 498         tmu->channel.base = ioremap_nocache(res->start, resource_size(res));
 499         if (tmu->channel.base == NULL) {
 500                 dev_err(&tmu->pdev->dev, "failed to remap I/O memory\n");
 501                 goto err0;
 502         }
 503
 504         tmu->mapbase = tmu->channel.base - cfg->channel_offset;
 505
 506         /* get hold of clock */
 507         tmu->clk = clk_get(&tmu->pdev->dev, "tmu_fck");
 508         if (IS_ERR(tmu->clk)) {
 509                 dev_err(&tmu->pdev->dev, "cannot get clock\n");
 510                 ret = PTR_ERR(tmu->clk);
 511                 goto err1;
 512         }
 513
 514         ret = clk_prepare(tmu->clk);
 515         if (ret < 0)
 516                 goto err2;
 517
 518         ret = sh_tmu_channel_setup(&tmu->channel, tmu);
 519         if (ret < 0)
 520                 goto err3;
 521
 522         return 0;
 523
 524  err3:
 525         clk_unprepare(tmu->clk);
 526  err2:
 527         clk_put(tmu->clk);
 528  err1:
 529         iounmap(tmu->channel.base);
 530  err0:
 531         return ret;
 532 }
 533
 534 static int sh_tmu_probe(struct platform_device *pdev)
 535 {
 536         struct sh_tmu_device *tmu = platform_get_drvdata(pdev);
 537         struct sh_timer_config *cfg = pdev->dev.platform_data;
 538         int ret;
 539
 540         if (!is_early_platform_device(pdev)) {
 541                 pm_runtime_set_active(&pdev->dev);
 542                 pm_runtime_enable(&pdev->dev);
 543         }
 544
 545         if (tmu) {
 546                 dev_info(&pdev->dev, "kept as earlytimer\n");
 547                 goto out;
 548         }
 549
 550         tmu = kmalloc(sizeof(*tmu), GFP_KERNEL);
 551         if (tmu == NULL) {
 552                 dev_err(&pdev->dev, "failed to allocate driver data\n");
 553                 return -ENOMEM;
 554         }
 555
 556         ret = sh_tmu_setup(tmu, pdev);
 557         if (ret) {
 558                 kfree(tmu);
 559                 pm_runtime_idle(&pdev->dev);
 560                 return ret;
 561         }
 562         if (is_early_platform_device(pdev))
 563                 return 0;
 564
 565  out:
 566         if (cfg->clockevent_rating || cfg->clocksource_rating)
 567                 pm_runtime_irq_safe(&pdev->dev);
 568         else
 569                 pm_runtime_idle(&pdev->dev);
 570
 571         return 0;
 572 }
 573
 574 static int sh_tmu_remove(struct platform_device *pdev)
 575 {
 576         return -EBUSY; /* cannot unregister clockevent and clocksource */
 577 }
 578
 579 static struct platform_driver sh_tmu_device_driver = {
 580         .probe          = sh_tmu_probe,
 581         .remove         = sh_tmu_remove,
 582         .driver         = {
 583                 .name   = "sh_tmu",
 584         }
 585 };
 586
 587 static int __init sh_tmu_init(void)
 588 {
 589         return platform_driver_register(&sh_tmu_device_driver);
 590 }
 591
 592 static void __exit sh_tmu_exit(void)
 593 {
 594         platform_driver_unregister(&sh_tmu_device_driver);
 595 }
 596
 597 early_platform_init("earlytimer", &sh_tmu_device_driver);
 598 subsys_initcall(sh_tmu_init);
 599 module_exit(sh_tmu_exit);
 600
 601 MODULE_AUTHOR("Magnus Damm");
 602 MODULE_DESCRIPTION("SuperH TMU Timer Driver");
 603 MODULE_LICENSE("GPL v2");