drivers/clocksource/sh_tmu.c

   1 /*
   2  * SuperH Timer Support - TMU
   3  *
   4  *  Copyright (C) 2009 Magnus Damm
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 #include <linux/clk.h>
  17 #include <linux/clockchips.h>
  18 #include <linux/clocksource.h>
  19 #include <linux/delay.h>
  20 #include <linux/err.h>
  21 #include <linux/init.h>
  22 #include <linux/interrupt.h>
  23 #include <linux/io.h>
  24 #include <linux/ioport.h>
  25 #include <linux/irq.h>
  26 #include <linux/module.h>
  27 #include <linux/platform_device.h>
  28 #include <linux/pm_domain.h>
  29 #include <linux/pm_runtime.h>
  30 #include <linux/sh_timer.h>
  31 #include <linux/slab.h>
  32 #include <linux/spinlock.h>
  33
  34 enum sh_tmu_model {
  35         SH_TMU,
  36         SH_TMU_SH3,
  37 };
  38
  39 struct sh_tmu_device;
  40
  41 struct sh_tmu_channel {
  42         struct sh_tmu_device *tmu;
  43         unsigned int index;
  44
  45         void __iomem *base;
  46         int irq;
  47
  48         unsigned long rate;
  49         unsigned long periodic;
  50         struct clock_event_device ced;
  51         struct clocksource cs;
  52         bool cs_enabled;
  53         unsigned int enable_count;
  54 };
  55
  56 struct sh_tmu_device {
  57         struct platform_device *pdev;
  58
  59         void __iomem *mapbase;
  60         struct clk *clk;
  61
  62         enum sh_tmu_model model;
  63
  64         struct sh_tmu_channel *channels;
  65         unsigned int num_channels;
  66
  67         bool has_clockevent;
  68         bool has_clocksource;
  69 };
  70
  71 static DEFINE_RAW_SPINLOCK(sh_tmu_lock);
  72
  73 #define TSTR -1 /* shared register */
  74 #define TCOR  0 /* channel register */
  75 #define TCNT 1 /* channel register */
  76 #define TCR 2 /* channel register */
  77
  78 #define TCR_UNF                 (1 << 8)
  79 #define TCR_UNIE                (1 << 5)
  80 #define TCR_TPSC_CLK4           (0 << 0)
  81 #define TCR_TPSC_CLK16          (1 << 0)
  82 #define TCR_TPSC_CLK64          (2 << 0)
  83 #define TCR_TPSC_CLK256         (3 << 0)
  84 #define TCR_TPSC_CLK1024        (4 << 0)
  85 #define TCR_TPSC_MASK           (7 << 0)
  86
  87 static inline unsigned long sh_tmu_read(struct sh_tmu_channel *ch, int reg_nr)
  88 {
  89         unsigned long offs;
  90
  91         if (reg_nr == TSTR) {
  92                 switch (ch->tmu->model) {
  93                 case SH_TMU_SH3:
  94                         return ioread8(ch->tmu->mapbase + 2);
  95                 case SH_TMU:
  96                         return ioread8(ch->tmu->mapbase + 4);
  97                 }
  98         }
  99
 100         offs = reg_nr << 2;
 101
 102         if (reg_nr == TCR)
 103                 return ioread16(ch->base + offs);
 104         else
 105                 return ioread32(ch->base + offs);
 106 }
 107
 108 static inline void sh_tmu_write(struct sh_tmu_channel *ch, int reg_nr,
 109                                 unsigned long value)
 110 {
 111         unsigned long offs;
 112
 113         if (reg_nr == TSTR) {
 114                 switch (ch->tmu->model) {
 115                 case SH_TMU_SH3:
 116                         return iowrite8(value, ch->tmu->mapbase + 2);
 117                 case SH_TMU:
 118                         return iowrite8(value, ch->tmu->mapbase + 4);
 119                 }
 120         }
 121
 122         offs = reg_nr << 2;
 123
 124         if (reg_nr == TCR)
 125                 iowrite16(value, ch->base + offs);
 126         else
 127                 iowrite32(value, ch->base + offs);
 128 }
 129
 130 static void sh_tmu_start_stop_ch(struct sh_tmu_channel *ch, int start)
 131 {
 132         unsigned long flags, value;
 133
 134         /* start stop register shared by multiple timer channels */
 135         raw_spin_lock_irqsave(&sh_tmu_lock, flags);
 136         value = sh_tmu_read(ch, TSTR);
 137
 138         if (start)
 139                 value |= 1 << ch->index;
 140         else
 141                 value &= ~(1 << ch->index);
 142
 143         sh_tmu_write(ch, TSTR, value);
 144         raw_spin_unlock_irqrestore(&sh_tmu_lock, flags);
 145 }
 146
 147 static int __sh_tmu_enable(struct sh_tmu_channel *ch)
 148 {
 149         int ret;
 150
 151         /* enable clock */
 152         ret = clk_enable(ch->tmu->clk);
 153         if (ret) {
 154                 dev_err(&ch->tmu->pdev->dev, "ch%u: cannot enable clock\n",
 155                         ch->index);
 156                 return ret;
 157         }
 158
 159         /* make sure channel is disabled */
 160         sh_tmu_start_stop_ch(ch, 0);
 161
 162         /* maximum timeout */
 163         sh_tmu_write(ch, TCOR, 0xffffffff);
 164         sh_tmu_write(ch, TCNT, 0xffffffff);
 165
 166         /* configure channel to parent clock / 4, irq off */
 167         ch->rate = clk_get_rate(ch->tmu->clk) / 4;
 168         sh_tmu_write(ch, TCR, TCR_TPSC_CLK4);
 169
 170         /* enable channel */
 171         sh_tmu_start_stop_ch(ch, 1);
 172
 173         return 0;
 174 }
 175
 176 static int sh_tmu_enable(struct sh_tmu_channel *ch)
 177 {
 178         if (ch->enable_count++ > 0)
 179                 return 0;
 180
 181         pm_runtime_get_sync(&ch->tmu->pdev->dev);
 182         dev_pm_syscore_device(&ch->tmu->pdev->dev, true);
 183
 184         return __sh_tmu_enable(ch);
 185 }
 186
 187 static void __sh_tmu_disable(struct sh_tmu_channel *ch)
 188 {
 189         /* disable channel */
 190         sh_tmu_start_stop_ch(ch, 0);
 191
 192         /* disable interrupts in TMU block */
 193         sh_tmu_write(ch, TCR, TCR_TPSC_CLK4);
 194
 195         /* stop clock */
 196         clk_disable(ch->tmu->clk);
 197 }
 198
 199 static void sh_tmu_disable(struct sh_tmu_channel *ch)
 200 {
 201         if (WARN_ON(ch->enable_count == 0))
 202                 return;
 203
 204         if (--ch->enable_count > 0)
 205                 return;
 206
 207         __sh_tmu_disable(ch);
 208
 209         dev_pm_syscore_device(&ch->tmu->pdev->dev, false);
 210         pm_runtime_put(&ch->tmu->pdev->dev);
 211 }
 212
 213 static void sh_tmu_set_next(struct sh_tmu_channel *ch, unsigned long delta,
 214                             int periodic)
 215 {
 216         /* stop timer */
 217         sh_tmu_start_stop_ch(ch, 0);
 218
 219         /* acknowledge interrupt */
 220         sh_tmu_read(ch, TCR);
 221
 222         /* enable interrupt */
 223         sh_tmu_write(ch, TCR, TCR_UNIE | TCR_TPSC_CLK4);
 224
 225         /* reload delta value in case of periodic timer */
 226         if (periodic)
 227                 sh_tmu_write(ch, TCOR, delta);
 228         else
 229                 sh_tmu_write(ch, TCOR, 0xffffffff);
 230
 231         sh_tmu_write(ch, TCNT, delta);
 232
 233         /* start timer */
 234         sh_tmu_start_stop_ch(ch, 1);
 235 }
 236
 237 static irqreturn_t sh_tmu_interrupt(int irq, void *dev_id)
 238 {
 239         struct sh_tmu_channel *ch = dev_id;
 240
 241         /* disable or acknowledge interrupt */
 242         if (ch->ced.mode == CLOCK_EVT_MODE_ONESHOT)
 243                 sh_tmu_write(ch, TCR, TCR_TPSC_CLK4);
 244         else
 245                 sh_tmu_write(ch, TCR, TCR_UNIE | TCR_TPSC_CLK4);
 246
 247         /* notify clockevent layer */
 248         ch->ced.event_handler(&ch->ced);
 249         return IRQ_HANDLED;
 250 }
 251
 252 static struct sh_tmu_channel *cs_to_sh_tmu(struct clocksource *cs)
 253 {
 254         return container_of(cs, struct sh_tmu_channel, cs);
 255 }
 256
 257 static cycle_t sh_tmu_clocksource_read(struct clocksource *cs)
 258 {
 259         struct sh_tmu_channel *ch = cs_to_sh_tmu(cs);
 260
 261         return sh_tmu_read(ch, TCNT) ^ 0xffffffff;
 262 }
 263
 264 static int sh_tmu_clocksource_enable(struct clocksource *cs)
 265 {
 266         struct sh_tmu_channel *ch = cs_to_sh_tmu(cs);
 267         int ret;
 268
 269         if (WARN_ON(ch->cs_enabled))
 270                 return 0;
 271
 272         ret = sh_tmu_enable(ch);
 273         if (!ret) {
 274                 __clocksource_updatefreq_hz(cs, ch->rate);
 275                 ch->cs_enabled = true;
 276         }
 277
 278         return ret;
 279 }
 280
 281 static void sh_tmu_clocksource_disable(struct clocksource *cs)
 282 {
 283         struct sh_tmu_channel *ch = cs_to_sh_tmu(cs);
 284
 285         if (WARN_ON(!ch->cs_enabled))
 286                 return;
 287
 288         sh_tmu_disable(ch);
 289         ch->cs_enabled = false;
 290 }
 291
 292 static void sh_tmu_clocksource_suspend(struct clocksource *cs)
 293 {
 294         struct sh_tmu_channel *ch = cs_to_sh_tmu(cs);
 295
 296         if (!ch->cs_enabled)
 297                 return;
 298
 299         if (--ch->enable_count == 0) {
 300                 __sh_tmu_disable(ch);
 301                 pm_genpd_syscore_poweroff(&ch->tmu->pdev->dev);
 302         }
 303 }
 304
 305 static void sh_tmu_clocksource_resume(struct clocksource *cs)
 306 {
 307         struct sh_tmu_channel *ch = cs_to_sh_tmu(cs);
 308
 309         if (!ch->cs_enabled)
 310                 return;
 311
 312         if (ch->enable_count++ == 0) {
 313                 pm_genpd_syscore_poweron(&ch->tmu->pdev->dev);
 314                 __sh_tmu_enable(ch);
 315         }
 316 }
 317
 318 static int sh_tmu_register_clocksource(struct sh_tmu_channel *ch,
 319                                        const char *name)
 320 {
 321         struct clocksource *cs = &ch->cs;
 322
 323         cs->name = name;
 324         cs->rating = 200;
 325         cs->read = sh_tmu_clocksource_read;
 326         cs->enable = sh_tmu_clocksource_enable;
 327         cs->disable = sh_tmu_clocksource_disable;
 328         cs->suspend = sh_tmu_clocksource_suspend;
 329         cs->resume = sh_tmu_clocksource_resume;
 330         cs->mask = CLOCKSOURCE_MASK(32);
 331         cs->flags = CLOCK_SOURCE_IS_CONTINUOUS;
 332
 333         dev_info(&ch->tmu->pdev->dev, "ch%u: used as clock source\n",
 334                  ch->index);
 335
 336         /* Register with dummy 1 Hz value, gets updated in ->enable() */
 337         clocksource_register_hz(cs, 1);
 338         return 0;
 339 }
 340
 341 static struct sh_tmu_channel *ced_to_sh_tmu(struct clock_event_device *ced)
 342 {
 343         return container_of(ced, struct sh_tmu_channel, ced);
 344 }
 345
 346 static void sh_tmu_clock_event_start(struct sh_tmu_channel *ch, int periodic)
 347 {
 348         struct clock_event_device *ced = &ch->ced;
 349
 350         sh_tmu_enable(ch);
 351
 352         clockevents_config(ced, ch->rate);
 353
 354         if (periodic) {
 355                 ch->periodic = (ch->rate + HZ/2) / HZ;
 356                 sh_tmu_set_next(ch, ch->periodic, 1);
 357         }
 358 }
 359
 360 static void sh_tmu_clock_event_mode(enum clock_event_mode mode,
 361                                     struct clock_event_device *ced)
 362 {
 363         struct sh_tmu_channel *ch = ced_to_sh_tmu(ced);
 364         int disabled = 0;
 365
 366         /* deal with old setting first */
 367         switch (ced->mode) {
 368         case CLOCK_EVT_MODE_PERIODIC:
 369         case CLOCK_EVT_MODE_ONESHOT:
 370                 sh_tmu_disable(ch);
 371                 disabled = 1;
 372                 break;
 373         default:
 374                 break;
 375         }
 376
 377         switch (mode) {
 378         case CLOCK_EVT_MODE_PERIODIC:
 379                 dev_info(&ch->tmu->pdev->dev,
 380                          "ch%u: used for periodic clock events\n", ch->index);
 381                 sh_tmu_clock_event_start(ch, 1);
 382                 break;
 383         case CLOCK_EVT_MODE_ONESHOT:
 384                 dev_info(&ch->tmu->pdev->dev,
 385                          "ch%u: used for oneshot clock events\n", ch->index);
 386                 sh_tmu_clock_event_start(ch, 0);
 387                 break;
 388         case CLOCK_EVT_MODE_UNUSED:
 389                 if (!disabled)
 390                         sh_tmu_disable(ch);
 391                 break;
 392         case CLOCK_EVT_MODE_SHUTDOWN:
 393         default:
 394                 break;
 395         }
 396 }
 397
 398 static int sh_tmu_clock_event_next(unsigned long delta,
 399                                    struct clock_event_device *ced)
 400 {
 401         struct sh_tmu_channel *ch = ced_to_sh_tmu(ced);
 402
 403         BUG_ON(ced->mode != CLOCK_EVT_MODE_ONESHOT);
 404
 405         /* program new delta value */
 406         sh_tmu_set_next(ch, delta, 0);
 407         return 0;
 408 }
 409
 410 static void sh_tmu_clock_event_suspend(struct clock_event_device *ced)
 411 {
 412         pm_genpd_syscore_poweroff(&ced_to_sh_tmu(ced)->tmu->pdev->dev);
 413 }
 414
 415 static void sh_tmu_clock_event_resume(struct clock_event_device *ced)
 416 {
 417         pm_genpd_syscore_poweron(&ced_to_sh_tmu(ced)->tmu->pdev->dev);
 418 }
 419
 420 static void sh_tmu_register_clockevent(struct sh_tmu_channel *ch,
 421                                        const char *name)
 422 {
 423         struct clock_event_device *ced = &ch->ced;
 424         int ret;
 425
 426         ced->name = name;
 427         ced->features = CLOCK_EVT_FEAT_PERIODIC;
 428         ced->features |= CLOCK_EVT_FEAT_ONESHOT;
 429         ced->rating = 200;
 430         ced->cpumask = cpumask_of(0);
 431         ced->set_next_event = sh_tmu_clock_event_next;
 432         ced->set_mode = sh_tmu_clock_event_mode;
 433         ced->suspend = sh_tmu_clock_event_suspend;
 434         ced->resume = sh_tmu_clock_event_resume;
 435
 436         dev_info(&ch->tmu->pdev->dev, "ch%u: used for clock events\n",
 437                  ch->index);
 438
 439         clockevents_config_and_register(ced, 1, 0x300, 0xffffffff);
 440
 441         ret = request_irq(ch->irq, sh_tmu_interrupt,
 442                           IRQF_TIMER | IRQF_IRQPOLL | IRQF_NOBALANCING,
 443                           dev_name(&ch->tmu->pdev->dev), ch);
 444         if (ret) {
 445                 dev_err(&ch->tmu->pdev->dev, "ch%u: failed to request irq %d\n",
 446                         ch->index, ch->irq);
 447                 return;
 448         }
 449 }
 450
 451 static int sh_tmu_register(struct sh_tmu_channel *ch, const char *name,
 452                            bool clockevent, bool clocksource)
 453 {
 454         if (clockevent) {
 455                 ch->tmu->has_clockevent = true;
 456                 sh_tmu_register_clockevent(ch, name);
 457         } else if (clocksource) {
 458                 ch->tmu->has_clocksource = true;
 459                 sh_tmu_register_clocksource(ch, name);
 460         }
 461
 462         return 0;
 463 }
 464
 465 static int sh_tmu_channel_setup(struct sh_tmu_channel *ch, unsigned int index,
 466                                 bool clockevent, bool clocksource,
 467                                 struct sh_tmu_device *tmu)
 468 {
 469         /* Skip unused channels. */
 470         if (!clockevent && !clocksource)
 471                 return 0;
 472
 473         ch->tmu = tmu;
 474         ch->index = index;
 475
 476         if (tmu->model == SH_TMU_SH3)
 477                 ch->base = tmu->mapbase + 4 + ch->index * 12;
 478         else
 479                 ch->base = tmu->mapbase + 8 + ch->index * 12;
 480
 481         ch->irq = platform_get_irq(tmu->pdev, index);
 482         if (ch->irq < 0) {
 483                 dev_err(&tmu->pdev->dev, "ch%u: failed to get irq\n",
 484                         ch->index);
 485                 return ch->irq;
 486         }
 487
 488         ch->cs_enabled = false;
 489         ch->enable_count = 0;
 490
 491         return sh_tmu_register(ch, dev_name(&tmu->pdev->dev),
 492                                clockevent, clocksource);
 493 }
 494
 495 static int sh_tmu_map_memory(struct sh_tmu_device *tmu)
 496 {
 497         struct resource *res;
 498
 499         res = platform_get_resource(tmu->pdev, IORESOURCE_MEM, 0);
 500         if (!res) {
 501                 dev_err(&tmu->pdev->dev, "failed to get I/O memory\n");
 502                 return -ENXIO;
 503         }
 504
 505         tmu->mapbase = ioremap_nocache(res->start, resource_size(res));
 506         if (tmu->mapbase == NULL)
 507                 return -ENXIO;
 508
 509         return 0;
 510 }
 511
 512 static int sh_tmu_setup(struct sh_tmu_device *tmu, struct platform_device *pdev)
 513 {
 514         struct sh_timer_config *cfg = pdev->dev.platform_data;
 515         const struct platform_device_id *id = pdev->id_entry;
 516         unsigned int i;
 517         int ret;
 518
 519         if (!cfg) {
 520                 dev_err(&tmu->pdev->dev, "missing platform data\n");
 521                 return -ENXIO;
 522         }
 523
 524         tmu->pdev = pdev;
 525         tmu->model = id->driver_data;
 526
 527         /* Get hold of clock. */
 528         tmu->clk = clk_get(&tmu->pdev->dev, "fck");
 529         if (IS_ERR(tmu->clk)) {
 530                 dev_err(&tmu->pdev->dev, "cannot get clock\n");
 531                 return PTR_ERR(tmu->clk);
 532         }
 533
 534         ret = clk_prepare(tmu->clk);
 535         if (ret < 0)
 536                 goto err_clk_put;
 537
 538         /* Map the memory resource. */
 539         ret = sh_tmu_map_memory(tmu);
 540         if (ret < 0) {
 541                 dev_err(&tmu->pdev->dev, "failed to remap I/O memory\n");
 542                 goto err_clk_unprepare;
 543         }
 544
 545         /* Allocate and setup the channels. */
 546         tmu->num_channels = hweight8(cfg->channels_mask);
 547
 548         tmu->channels = kzalloc(sizeof(*tmu->channels) * tmu->num_channels,
 549                                 GFP_KERNEL);
 550         if (tmu->channels == NULL) {
 551                 ret = -ENOMEM;
 552                 goto err_unmap;
 553         }
 554
 555         /*
 556          * Use the first channel as a clock event device and the second channel
 557          * as a clock source.
 558          */
 559         for (i = 0; i < tmu->num_channels; ++i) {
 560                 ret = sh_tmu_channel_setup(&tmu->channels[i], i,
 561                                            i == 0, i == 1, tmu);
 562                 if (ret < 0)
 563                         goto err_unmap;
 564         }
 565
 566         platform_set_drvdata(pdev, tmu);
 567
 568         return 0;
 569
 570 err_unmap:
 571         kfree(tmu->channels);
 572         iounmap(tmu->mapbase);
 573 err_clk_unprepare:
 574         clk_unprepare(tmu->clk);
 575 err_clk_put:
 576         clk_put(tmu->clk);
 577         return ret;
 578 }
 579
 580 static int sh_tmu_probe(struct platform_device *pdev)
 581 {
 582         struct sh_tmu_device *tmu = platform_get_drvdata(pdev);
 583         int ret;
 584
 585         if (!is_early_platform_device(pdev)) {
 586                 pm_runtime_set_active(&pdev->dev);
 587                 pm_runtime_enable(&pdev->dev);
 588         }
 589
 590         if (tmu) {
 591                 dev_info(&pdev->dev, "kept as earlytimer\n");
 592                 goto out;
 593         }
 594
 595         tmu = kzalloc(sizeof(*tmu), GFP_KERNEL);
 596         if (tmu == NULL)
 597                 return -ENOMEM;
 598
 599         ret = sh_tmu_setup(tmu, pdev);
 600         if (ret) {
 601                 kfree(tmu);
 602                 pm_runtime_idle(&pdev->dev);
 603                 return ret;
 604         }
 605         if (is_early_platform_device(pdev))
 606                 return 0;
 607
 608  out:
 609         if (tmu->has_clockevent || tmu->has_clocksource)
 610                 pm_runtime_irq_safe(&pdev->dev);
 611         else
 612                 pm_runtime_idle(&pdev->dev);
 613
 614         return 0;
 615 }
 616
 617 static int sh_tmu_remove(struct platform_device *pdev)
 618 {
 619         return -EBUSY; /* cannot unregister clockevent and clocksource */
 620 }
 621
 622 static const struct platform_device_id sh_tmu_id_table[] = {
 623         { "sh-tmu", SH_TMU },
 624         { "sh-tmu-sh3", SH_TMU_SH3 },
 625         { }
 626 };
 627 MODULE_DEVICE_TABLE(platform, sh_tmu_id_table);
 628
 629 static struct platform_driver sh_tmu_device_driver = {
 630         .probe          = sh_tmu_probe,
 631         .remove         = sh_tmu_remove,
 632         .driver         = {
 633                 .name   = "sh_tmu",
 634         },
 635         .id_table       = sh_tmu_id_table,
 636 };
 637
 638 static int __init sh_tmu_init(void)
 639 {
 640         return platform_driver_register(&sh_tmu_device_driver);
 641 }
 642
 643 static void __exit sh_tmu_exit(void)
 644 {
 645         platform_driver_unregister(&sh_tmu_device_driver);
 646 }
 647
 648 early_platform_init("earlytimer", &sh_tmu_device_driver);
 649 subsys_initcall(sh_tmu_init);
 650 module_exit(sh_tmu_exit);
 651
 652 MODULE_AUTHOR("Magnus Damm");
 653 MODULE_DESCRIPTION("SuperH TMU Timer Driver");
 654 MODULE_LICENSE("GPL v2");