2 * SuperH Timer Support - TMU
4 * Copyright (C) 2009 Magnus Damm
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 #include <linux/init.h>
21 #include <linux/platform_device.h>
22 #include <linux/spinlock.h>
23 #include <linux/interrupt.h>
24 #include <linux/ioport.h>
25 #include <linux/delay.h>
27 #include <linux/clk.h>
28 #include <linux/pm_runtime.h>
29 #include <linux/irq.h>
30 #include <linux/err.h>
31 #include <linux/clocksource.h>
32 #include <linux/clockchips.h>
33 #include <linux/sh_timer.h>
34 #include <linux/slab.h>
37 void __iomem *mapbase;
39 struct irqaction irqaction;
40 struct platform_device *pdev;
42 unsigned long periodic;
43 struct clock_event_device ced;
44 struct clocksource cs;
47 static DEFINE_SPINLOCK(sh_tmu_lock);
49 #define TSTR -1 /* shared register */
50 #define TCOR 0 /* channel register */
51 #define TCNT 1 /* channel register */
52 #define TCR 2 /* channel register */
54 static inline unsigned long sh_tmu_read(struct sh_tmu_priv *p, int reg_nr)
56 struct sh_timer_config *cfg = p->pdev->dev.platform_data;
57 void __iomem *base = p->mapbase;
61 return ioread8(base - cfg->channel_offset);
66 return ioread16(base + offs);
68 return ioread32(base + offs);
71 static inline void sh_tmu_write(struct sh_tmu_priv *p, int reg_nr,
74 struct sh_timer_config *cfg = p->pdev->dev.platform_data;
75 void __iomem *base = p->mapbase;
79 iowrite8(value, base - cfg->channel_offset);
86 iowrite16(value, base + offs);
88 iowrite32(value, base + offs);
91 static void sh_tmu_start_stop_ch(struct sh_tmu_priv *p, int start)
93 struct sh_timer_config *cfg = p->pdev->dev.platform_data;
94 unsigned long flags, value;
96 /* start stop register shared by multiple timer channels */
97 spin_lock_irqsave(&sh_tmu_lock, flags);
98 value = sh_tmu_read(p, TSTR);
101 value |= 1 << cfg->timer_bit;
103 value &= ~(1 << cfg->timer_bit);
105 sh_tmu_write(p, TSTR, value);
106 spin_unlock_irqrestore(&sh_tmu_lock, flags);
109 static int sh_tmu_enable(struct sh_tmu_priv *p)
113 /* wake up device and enable clock */
114 pm_runtime_get_sync(&p->pdev->dev);
115 ret = clk_enable(p->clk);
117 dev_err(&p->pdev->dev, "cannot enable clock\n");
118 pm_runtime_put_sync(&p->pdev->dev);
122 /* make sure channel is disabled */
123 sh_tmu_start_stop_ch(p, 0);
125 /* maximum timeout */
126 sh_tmu_write(p, TCOR, 0xffffffff);
127 sh_tmu_write(p, TCNT, 0xffffffff);
129 /* configure channel to parent clock / 4, irq off */
130 p->rate = clk_get_rate(p->clk) / 4;
131 sh_tmu_write(p, TCR, 0x0000);
134 sh_tmu_start_stop_ch(p, 1);
139 static void sh_tmu_disable(struct sh_tmu_priv *p)
141 /* disable channel */
142 sh_tmu_start_stop_ch(p, 0);
144 /* disable interrupts in TMU block */
145 sh_tmu_write(p, TCR, 0x0000);
147 /* stop clock and mark device as idle */
149 pm_runtime_put_sync(&p->pdev->dev);
152 static void sh_tmu_set_next(struct sh_tmu_priv *p, unsigned long delta,
156 sh_tmu_start_stop_ch(p, 0);
158 /* acknowledge interrupt */
161 /* enable interrupt */
162 sh_tmu_write(p, TCR, 0x0020);
164 /* reload delta value in case of periodic timer */
166 sh_tmu_write(p, TCOR, delta);
168 sh_tmu_write(p, TCOR, 0xffffffff);
170 sh_tmu_write(p, TCNT, delta);
173 sh_tmu_start_stop_ch(p, 1);
176 static irqreturn_t sh_tmu_interrupt(int irq, void *dev_id)
178 struct sh_tmu_priv *p = dev_id;
180 /* disable or acknowledge interrupt */
181 if (p->ced.mode == CLOCK_EVT_MODE_ONESHOT)
182 sh_tmu_write(p, TCR, 0x0000);
184 sh_tmu_write(p, TCR, 0x0020);
186 /* notify clockevent layer */
187 p->ced.event_handler(&p->ced);
191 static struct sh_tmu_priv *cs_to_sh_tmu(struct clocksource *cs)
193 return container_of(cs, struct sh_tmu_priv, cs);
196 static cycle_t sh_tmu_clocksource_read(struct clocksource *cs)
198 struct sh_tmu_priv *p = cs_to_sh_tmu(cs);
200 return sh_tmu_read(p, TCNT) ^ 0xffffffff;
203 static int sh_tmu_clocksource_enable(struct clocksource *cs)
205 struct sh_tmu_priv *p = cs_to_sh_tmu(cs);
208 ret = sh_tmu_enable(p);
210 __clocksource_updatefreq_hz(cs, p->rate);
214 static void sh_tmu_clocksource_disable(struct clocksource *cs)
216 sh_tmu_disable(cs_to_sh_tmu(cs));
219 static int sh_tmu_register_clocksource(struct sh_tmu_priv *p,
220 char *name, unsigned long rating)
222 struct clocksource *cs = &p->cs;
226 cs->read = sh_tmu_clocksource_read;
227 cs->enable = sh_tmu_clocksource_enable;
228 cs->disable = sh_tmu_clocksource_disable;
229 cs->mask = CLOCKSOURCE_MASK(32);
230 cs->flags = CLOCK_SOURCE_IS_CONTINUOUS;
232 dev_info(&p->pdev->dev, "used as clock source\n");
234 /* Register with dummy 1 Hz value, gets updated in ->enable() */
235 clocksource_register_hz(cs, 1);
239 static struct sh_tmu_priv *ced_to_sh_tmu(struct clock_event_device *ced)
241 return container_of(ced, struct sh_tmu_priv, ced);
244 static void sh_tmu_clock_event_start(struct sh_tmu_priv *p, int periodic)
246 struct clock_event_device *ced = &p->ced;
250 /* TODO: calculate good shift from rate and counter bit width */
253 ced->mult = div_sc(p->rate, NSEC_PER_SEC, ced->shift);
254 ced->max_delta_ns = clockevent_delta2ns(0xffffffff, ced);
255 ced->min_delta_ns = 5000;
258 p->periodic = (p->rate + HZ/2) / HZ;
259 sh_tmu_set_next(p, p->periodic, 1);
263 static void sh_tmu_clock_event_mode(enum clock_event_mode mode,
264 struct clock_event_device *ced)
266 struct sh_tmu_priv *p = ced_to_sh_tmu(ced);
269 /* deal with old setting first */
271 case CLOCK_EVT_MODE_PERIODIC:
272 case CLOCK_EVT_MODE_ONESHOT:
281 case CLOCK_EVT_MODE_PERIODIC:
282 dev_info(&p->pdev->dev, "used for periodic clock events\n");
283 sh_tmu_clock_event_start(p, 1);
285 case CLOCK_EVT_MODE_ONESHOT:
286 dev_info(&p->pdev->dev, "used for oneshot clock events\n");
287 sh_tmu_clock_event_start(p, 0);
289 case CLOCK_EVT_MODE_UNUSED:
293 case CLOCK_EVT_MODE_SHUTDOWN:
299 static int sh_tmu_clock_event_next(unsigned long delta,
300 struct clock_event_device *ced)
302 struct sh_tmu_priv *p = ced_to_sh_tmu(ced);
304 BUG_ON(ced->mode != CLOCK_EVT_MODE_ONESHOT);
306 /* program new delta value */
307 sh_tmu_set_next(p, delta, 0);
311 static void sh_tmu_register_clockevent(struct sh_tmu_priv *p,
312 char *name, unsigned long rating)
314 struct clock_event_device *ced = &p->ced;
317 memset(ced, 0, sizeof(*ced));
320 ced->features = CLOCK_EVT_FEAT_PERIODIC;
321 ced->features |= CLOCK_EVT_FEAT_ONESHOT;
322 ced->rating = rating;
323 ced->cpumask = cpumask_of(0);
324 ced->set_next_event = sh_tmu_clock_event_next;
325 ced->set_mode = sh_tmu_clock_event_mode;
327 dev_info(&p->pdev->dev, "used for clock events\n");
328 clockevents_register_device(ced);
330 ret = setup_irq(p->irqaction.irq, &p->irqaction);
332 dev_err(&p->pdev->dev, "failed to request irq %d\n",
338 static int sh_tmu_register(struct sh_tmu_priv *p, char *name,
339 unsigned long clockevent_rating,
340 unsigned long clocksource_rating)
342 if (clockevent_rating)
343 sh_tmu_register_clockevent(p, name, clockevent_rating);
344 else if (clocksource_rating)
345 sh_tmu_register_clocksource(p, name, clocksource_rating);
350 static int sh_tmu_setup(struct sh_tmu_priv *p, struct platform_device *pdev)
352 struct sh_timer_config *cfg = pdev->dev.platform_data;
353 struct resource *res;
357 memset(p, 0, sizeof(*p));
361 dev_err(&p->pdev->dev, "missing platform data\n");
365 platform_set_drvdata(pdev, p);
367 res = platform_get_resource(p->pdev, IORESOURCE_MEM, 0);
369 dev_err(&p->pdev->dev, "failed to get I/O memory\n");
373 irq = platform_get_irq(p->pdev, 0);
375 dev_err(&p->pdev->dev, "failed to get irq\n");
379 /* map memory, let mapbase point to our channel */
380 p->mapbase = ioremap_nocache(res->start, resource_size(res));
381 if (p->mapbase == NULL) {
382 dev_err(&p->pdev->dev, "failed to remap I/O memory\n");
386 /* setup data for setup_irq() (too early for request_irq()) */
387 p->irqaction.name = dev_name(&p->pdev->dev);
388 p->irqaction.handler = sh_tmu_interrupt;
389 p->irqaction.dev_id = p;
390 p->irqaction.irq = irq;
391 p->irqaction.flags = IRQF_DISABLED | IRQF_TIMER | \
392 IRQF_IRQPOLL | IRQF_NOBALANCING;
394 /* get hold of clock */
395 p->clk = clk_get(&p->pdev->dev, "tmu_fck");
396 if (IS_ERR(p->clk)) {
397 dev_err(&p->pdev->dev, "cannot get clock\n");
398 ret = PTR_ERR(p->clk);
402 return sh_tmu_register(p, (char *)dev_name(&p->pdev->dev),
403 cfg->clockevent_rating,
404 cfg->clocksource_rating);
411 static int __devinit sh_tmu_probe(struct platform_device *pdev)
413 struct sh_tmu_priv *p = platform_get_drvdata(pdev);
417 dev_info(&pdev->dev, "kept as earlytimer\n");
418 pm_runtime_enable(&pdev->dev);
422 p = kmalloc(sizeof(*p), GFP_KERNEL);
424 dev_err(&pdev->dev, "failed to allocate driver data\n");
428 ret = sh_tmu_setup(p, pdev);
431 platform_set_drvdata(pdev, NULL);
434 if (!is_early_platform_device(pdev))
435 pm_runtime_enable(&pdev->dev);
439 static int __devexit sh_tmu_remove(struct platform_device *pdev)
441 return -EBUSY; /* cannot unregister clockevent and clocksource */
444 static struct platform_driver sh_tmu_device_driver = {
445 .probe = sh_tmu_probe,
446 .remove = __devexit_p(sh_tmu_remove),
452 static int __init sh_tmu_init(void)
454 return platform_driver_register(&sh_tmu_device_driver);
457 static void __exit sh_tmu_exit(void)
459 platform_driver_unregister(&sh_tmu_device_driver);
462 early_platform_init("earlytimer", &sh_tmu_device_driver);
463 module_init(sh_tmu_init);
464 module_exit(sh_tmu_exit);
466 MODULE_AUTHOR("Magnus Damm");
467 MODULE_DESCRIPTION("SuperH TMU Timer Driver");
468 MODULE_LICENSE("GPL v2");