2 * SuperH Timer Support - MTU2
4 * Copyright (C) 2009 Magnus Damm
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
16 #include <linux/clk.h>
17 #include <linux/clockchips.h>
18 #include <linux/delay.h>
19 #include <linux/err.h>
20 #include <linux/init.h>
21 #include <linux/interrupt.h>
23 #include <linux/ioport.h>
24 #include <linux/irq.h>
25 #include <linux/module.h>
26 #include <linux/platform_device.h>
27 #include <linux/pm_domain.h>
28 #include <linux/pm_runtime.h>
29 #include <linux/sh_timer.h>
30 #include <linux/slab.h>
31 #include <linux/spinlock.h>
33 struct sh_mtu2_device;
35 struct sh_mtu2_channel {
36 struct sh_mtu2_device *mtu;
41 struct clock_event_device ced;
44 struct sh_mtu2_device {
45 struct platform_device *pdev;
47 void __iomem *mapbase;
50 raw_spinlock_t lock; /* Protect the shared registers */
52 struct sh_mtu2_channel *channels;
53 unsigned int num_channels;
58 #define TSTR -1 /* shared register */
59 #define TCR 0 /* channel register */
60 #define TMDR 1 /* channel register */
61 #define TIOR 2 /* channel register */
62 #define TIER 3 /* channel register */
63 #define TSR 4 /* channel register */
64 #define TCNT 5 /* channel register */
65 #define TGR 6 /* channel register */
67 #define TCR_CCLR_NONE (0 << 5)
68 #define TCR_CCLR_TGRA (1 << 5)
69 #define TCR_CCLR_TGRB (2 << 5)
70 #define TCR_CCLR_SYNC (3 << 5)
71 #define TCR_CCLR_TGRC (5 << 5)
72 #define TCR_CCLR_TGRD (6 << 5)
73 #define TCR_CCLR_MASK (7 << 5)
74 #define TCR_CKEG_RISING (0 << 3)
75 #define TCR_CKEG_FALLING (1 << 3)
76 #define TCR_CKEG_BOTH (2 << 3)
77 #define TCR_CKEG_MASK (3 << 3)
78 /* Values 4 to 7 are channel-dependent */
79 #define TCR_TPSC_P1 (0 << 0)
80 #define TCR_TPSC_P4 (1 << 0)
81 #define TCR_TPSC_P16 (2 << 0)
82 #define TCR_TPSC_P64 (3 << 0)
83 #define TCR_TPSC_CH0_TCLKA (4 << 0)
84 #define TCR_TPSC_CH0_TCLKB (5 << 0)
85 #define TCR_TPSC_CH0_TCLKC (6 << 0)
86 #define TCR_TPSC_CH0_TCLKD (7 << 0)
87 #define TCR_TPSC_CH1_TCLKA (4 << 0)
88 #define TCR_TPSC_CH1_TCLKB (5 << 0)
89 #define TCR_TPSC_CH1_P256 (6 << 0)
90 #define TCR_TPSC_CH1_TCNT2 (7 << 0)
91 #define TCR_TPSC_CH2_TCLKA (4 << 0)
92 #define TCR_TPSC_CH2_TCLKB (5 << 0)
93 #define TCR_TPSC_CH2_TCLKC (6 << 0)
94 #define TCR_TPSC_CH2_P1024 (7 << 0)
95 #define TCR_TPSC_CH34_P256 (4 << 0)
96 #define TCR_TPSC_CH34_P1024 (5 << 0)
97 #define TCR_TPSC_CH34_TCLKA (6 << 0)
98 #define TCR_TPSC_CH34_TCLKB (7 << 0)
99 #define TCR_TPSC_MASK (7 << 0)
101 #define TMDR_BFE (1 << 6)
102 #define TMDR_BFB (1 << 5)
103 #define TMDR_BFA (1 << 4)
104 #define TMDR_MD_NORMAL (0 << 0)
105 #define TMDR_MD_PWM_1 (2 << 0)
106 #define TMDR_MD_PWM_2 (3 << 0)
107 #define TMDR_MD_PHASE_1 (4 << 0)
108 #define TMDR_MD_PHASE_2 (5 << 0)
109 #define TMDR_MD_PHASE_3 (6 << 0)
110 #define TMDR_MD_PHASE_4 (7 << 0)
111 #define TMDR_MD_PWM_SYNC (8 << 0)
112 #define TMDR_MD_PWM_COMP_CREST (13 << 0)
113 #define TMDR_MD_PWM_COMP_TROUGH (14 << 0)
114 #define TMDR_MD_PWM_COMP_BOTH (15 << 0)
115 #define TMDR_MD_MASK (15 << 0)
117 #define TIOC_IOCH(n) ((n) << 4)
118 #define TIOC_IOCL(n) ((n) << 0)
119 #define TIOR_OC_RETAIN (0 << 0)
120 #define TIOR_OC_0_CLEAR (1 << 0)
121 #define TIOR_OC_0_SET (2 << 0)
122 #define TIOR_OC_0_TOGGLE (3 << 0)
123 #define TIOR_OC_1_CLEAR (5 << 0)
124 #define TIOR_OC_1_SET (6 << 0)
125 #define TIOR_OC_1_TOGGLE (7 << 0)
126 #define TIOR_IC_RISING (8 << 0)
127 #define TIOR_IC_FALLING (9 << 0)
128 #define TIOR_IC_BOTH (10 << 0)
129 #define TIOR_IC_TCNT (12 << 0)
130 #define TIOR_MASK (15 << 0)
132 #define TIER_TTGE (1 << 7)
133 #define TIER_TTGE2 (1 << 6)
134 #define TIER_TCIEU (1 << 5)
135 #define TIER_TCIEV (1 << 4)
136 #define TIER_TGIED (1 << 3)
137 #define TIER_TGIEC (1 << 2)
138 #define TIER_TGIEB (1 << 1)
139 #define TIER_TGIEA (1 << 0)
141 #define TSR_TCFD (1 << 7)
142 #define TSR_TCFU (1 << 5)
143 #define TSR_TCFV (1 << 4)
144 #define TSR_TGFD (1 << 3)
145 #define TSR_TGFC (1 << 2)
146 #define TSR_TGFB (1 << 1)
147 #define TSR_TGFA (1 << 0)
149 static unsigned long mtu2_reg_offs[] = {
159 static inline unsigned long sh_mtu2_read(struct sh_mtu2_channel *ch, int reg_nr)
164 return ioread8(ch->mtu->mapbase + 0x280);
166 offs = mtu2_reg_offs[reg_nr];
168 if ((reg_nr == TCNT) || (reg_nr == TGR))
169 return ioread16(ch->base + offs);
171 return ioread8(ch->base + offs);
174 static inline void sh_mtu2_write(struct sh_mtu2_channel *ch, int reg_nr,
180 return iowrite8(value, ch->mtu->mapbase + 0x280);
182 offs = mtu2_reg_offs[reg_nr];
184 if ((reg_nr == TCNT) || (reg_nr == TGR))
185 iowrite16(value, ch->base + offs);
187 iowrite8(value, ch->base + offs);
190 static void sh_mtu2_start_stop_ch(struct sh_mtu2_channel *ch, int start)
192 unsigned long flags, value;
194 /* start stop register shared by multiple timer channels */
195 raw_spin_lock_irqsave(&ch->mtu->lock, flags);
196 value = sh_mtu2_read(ch, TSTR);
199 value |= 1 << ch->index;
201 value &= ~(1 << ch->index);
203 sh_mtu2_write(ch, TSTR, value);
204 raw_spin_unlock_irqrestore(&ch->mtu->lock, flags);
207 static int sh_mtu2_enable(struct sh_mtu2_channel *ch)
209 unsigned long periodic;
213 pm_runtime_get_sync(&ch->mtu->pdev->dev);
214 dev_pm_syscore_device(&ch->mtu->pdev->dev, true);
217 ret = clk_enable(ch->mtu->clk);
219 dev_err(&ch->mtu->pdev->dev, "ch%u: cannot enable clock\n",
224 /* make sure channel is disabled */
225 sh_mtu2_start_stop_ch(ch, 0);
227 rate = clk_get_rate(ch->mtu->clk) / 64;
228 periodic = (rate + HZ/2) / HZ;
231 * "Periodic Counter Operation"
232 * Clear on TGRA compare match, divide clock by 64.
234 sh_mtu2_write(ch, TCR, TCR_CCLR_TGRA | TCR_TPSC_P64);
235 sh_mtu2_write(ch, TIOR, TIOC_IOCH(TIOR_OC_0_CLEAR) |
236 TIOC_IOCL(TIOR_OC_0_CLEAR));
237 sh_mtu2_write(ch, TGR, periodic);
238 sh_mtu2_write(ch, TCNT, 0);
239 sh_mtu2_write(ch, TMDR, TMDR_MD_NORMAL);
240 sh_mtu2_write(ch, TIER, TIER_TGIEA);
243 sh_mtu2_start_stop_ch(ch, 1);
248 static void sh_mtu2_disable(struct sh_mtu2_channel *ch)
250 /* disable channel */
251 sh_mtu2_start_stop_ch(ch, 0);
254 clk_disable(ch->mtu->clk);
256 dev_pm_syscore_device(&ch->mtu->pdev->dev, false);
257 pm_runtime_put(&ch->mtu->pdev->dev);
260 static irqreturn_t sh_mtu2_interrupt(int irq, void *dev_id)
262 struct sh_mtu2_channel *ch = dev_id;
264 /* acknowledge interrupt */
265 sh_mtu2_read(ch, TSR);
266 sh_mtu2_write(ch, TSR, ~TSR_TGFA);
268 /* notify clockevent layer */
269 ch->ced.event_handler(&ch->ced);
273 static struct sh_mtu2_channel *ced_to_sh_mtu2(struct clock_event_device *ced)
275 return container_of(ced, struct sh_mtu2_channel, ced);
278 static void sh_mtu2_clock_event_mode(enum clock_event_mode mode,
279 struct clock_event_device *ced)
281 struct sh_mtu2_channel *ch = ced_to_sh_mtu2(ced);
284 /* deal with old setting first */
286 case CLOCK_EVT_MODE_PERIODIC:
295 case CLOCK_EVT_MODE_PERIODIC:
296 dev_info(&ch->mtu->pdev->dev,
297 "ch%u: used for periodic clock events\n", ch->index);
300 case CLOCK_EVT_MODE_UNUSED:
304 case CLOCK_EVT_MODE_SHUTDOWN:
310 static void sh_mtu2_clock_event_suspend(struct clock_event_device *ced)
312 pm_genpd_syscore_poweroff(&ced_to_sh_mtu2(ced)->mtu->pdev->dev);
315 static void sh_mtu2_clock_event_resume(struct clock_event_device *ced)
317 pm_genpd_syscore_poweron(&ced_to_sh_mtu2(ced)->mtu->pdev->dev);
320 static void sh_mtu2_register_clockevent(struct sh_mtu2_channel *ch,
323 struct clock_event_device *ced = &ch->ced;
326 ced->features = CLOCK_EVT_FEAT_PERIODIC;
328 ced->cpumask = cpu_possible_mask;
329 ced->set_mode = sh_mtu2_clock_event_mode;
330 ced->suspend = sh_mtu2_clock_event_suspend;
331 ced->resume = sh_mtu2_clock_event_resume;
333 dev_info(&ch->mtu->pdev->dev, "ch%u: used for clock events\n",
335 clockevents_register_device(ced);
338 static int sh_mtu2_register(struct sh_mtu2_channel *ch, const char *name)
340 ch->mtu->has_clockevent = true;
341 sh_mtu2_register_clockevent(ch, name);
346 static int sh_mtu2_setup_channel(struct sh_mtu2_channel *ch, unsigned int index,
347 struct sh_mtu2_device *mtu)
349 static const unsigned int channel_offsets[] = {
358 sprintf(name, "tgi%ua", index);
359 irq = platform_get_irq_byname(mtu->pdev, name);
361 /* Skip channels with no declared interrupt. */
365 ret = request_irq(irq, sh_mtu2_interrupt,
366 IRQF_TIMER | IRQF_IRQPOLL | IRQF_NOBALANCING,
367 dev_name(&ch->mtu->pdev->dev), ch);
369 dev_err(&ch->mtu->pdev->dev, "ch%u: failed to request irq %d\n",
374 ch->base = mtu->mapbase + channel_offsets[index];
377 return sh_mtu2_register(ch, dev_name(&mtu->pdev->dev));
380 static int sh_mtu2_map_memory(struct sh_mtu2_device *mtu)
382 struct resource *res;
384 res = platform_get_resource(mtu->pdev, IORESOURCE_MEM, 0);
386 dev_err(&mtu->pdev->dev, "failed to get I/O memory\n");
390 mtu->mapbase = ioremap_nocache(res->start, resource_size(res));
391 if (mtu->mapbase == NULL)
397 static int sh_mtu2_setup(struct sh_mtu2_device *mtu,
398 struct platform_device *pdev)
405 raw_spin_lock_init(&mtu->lock);
407 /* Get hold of clock. */
408 mtu->clk = clk_get(&mtu->pdev->dev, "fck");
409 if (IS_ERR(mtu->clk)) {
410 dev_err(&mtu->pdev->dev, "cannot get clock\n");
411 return PTR_ERR(mtu->clk);
414 ret = clk_prepare(mtu->clk);
418 /* Map the memory resource. */
419 ret = sh_mtu2_map_memory(mtu);
421 dev_err(&mtu->pdev->dev, "failed to remap I/O memory\n");
422 goto err_clk_unprepare;
425 /* Allocate and setup the channels. */
426 mtu->num_channels = 3;
428 mtu->channels = kzalloc(sizeof(*mtu->channels) * mtu->num_channels,
430 if (mtu->channels == NULL) {
435 for (i = 0; i < mtu->num_channels; ++i) {
436 ret = sh_mtu2_setup_channel(&mtu->channels[i], i, mtu);
441 platform_set_drvdata(pdev, mtu);
446 kfree(mtu->channels);
447 iounmap(mtu->mapbase);
449 clk_unprepare(mtu->clk);
455 static int sh_mtu2_probe(struct platform_device *pdev)
457 struct sh_mtu2_device *mtu = platform_get_drvdata(pdev);
460 if (!is_early_platform_device(pdev)) {
461 pm_runtime_set_active(&pdev->dev);
462 pm_runtime_enable(&pdev->dev);
466 dev_info(&pdev->dev, "kept as earlytimer\n");
470 mtu = kzalloc(sizeof(*mtu), GFP_KERNEL);
474 ret = sh_mtu2_setup(mtu, pdev);
477 pm_runtime_idle(&pdev->dev);
480 if (is_early_platform_device(pdev))
484 if (mtu->has_clockevent)
485 pm_runtime_irq_safe(&pdev->dev);
487 pm_runtime_idle(&pdev->dev);
492 static int sh_mtu2_remove(struct platform_device *pdev)
494 return -EBUSY; /* cannot unregister clockevent */
497 static const struct platform_device_id sh_mtu2_id_table[] = {
501 MODULE_DEVICE_TABLE(platform, sh_mtu2_id_table);
503 static struct platform_driver sh_mtu2_device_driver = {
504 .probe = sh_mtu2_probe,
505 .remove = sh_mtu2_remove,
509 .id_table = sh_mtu2_id_table,
512 static int __init sh_mtu2_init(void)
514 return platform_driver_register(&sh_mtu2_device_driver);
517 static void __exit sh_mtu2_exit(void)
519 platform_driver_unregister(&sh_mtu2_device_driver);
522 early_platform_init("earlytimer", &sh_mtu2_device_driver);
523 subsys_initcall(sh_mtu2_init);
524 module_exit(sh_mtu2_exit);
526 MODULE_AUTHOR("Magnus Damm");
527 MODULE_DESCRIPTION("SuperH MTU2 Timer Driver");
528 MODULE_LICENSE("GPL v2");