drivers/clocksource/sh_cmt.c

   1 /*
   2  * SuperH Timer Support - CMT
   3  *
   4  *  Copyright (C) 2008 Magnus Damm
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  18  */
  19
  20 #include <linux/init.h>
  21 #include <linux/platform_device.h>
  22 #include <linux/spinlock.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/ioport.h>
  25 #include <linux/io.h>
  26 #include <linux/clk.h>
  27 #include <linux/irq.h>
  28 #include <linux/err.h>
  29 #include <linux/delay.h>
  30 #include <linux/clocksource.h>
  31 #include <linux/clockchips.h>
  32 #include <linux/sh_timer.h>
  33 #include <linux/slab.h>
  34 #include <linux/module.h>
  35 #include <linux/pm_domain.h>
  36 #include <linux/pm_runtime.h>
  37
  38 struct sh_cmt_device;
  39
  40 struct sh_cmt_channel {
  41         struct sh_cmt_device *cmt;
  42
  43         unsigned long flags;
  44         unsigned long match_value;
  45         unsigned long next_match_value;
  46         unsigned long max_match_value;
  47         unsigned long rate;
  48         raw_spinlock_t lock;
  49         struct clock_event_device ced;
  50         struct clocksource cs;
  51         unsigned long total_cycles;
  52         bool cs_enabled;
  53 };
  54
  55 struct sh_cmt_device {
  56         struct platform_device *pdev;
  57
  58         void __iomem *mapbase;
  59         void __iomem *mapbase_str;
  60         struct clk *clk;
  61
  62         struct sh_cmt_channel channel;
  63
  64         unsigned long width; /* 16 or 32 bit version of hardware block */
  65         unsigned long overflow_bit;
  66         unsigned long clear_bits;
  67
  68         /* callbacks for CMSTR and CMCSR access */
  69         unsigned long (*read_control)(void __iomem *base, unsigned long offs);
  70         void (*write_control)(void __iomem *base, unsigned long offs,
  71                               unsigned long value);
  72
  73         /* callbacks for CMCNT and CMCOR access */
  74         unsigned long (*read_count)(void __iomem *base, unsigned long offs);
  75         void (*write_count)(void __iomem *base, unsigned long offs,
  76                             unsigned long value);
  77 };
  78
  79 /* Examples of supported CMT timer register layouts and I/O access widths:
  80  *
  81  * "16-bit counter and 16-bit control" as found on sh7263:
  82  * CMSTR 0xfffec000 16-bit
  83  * CMCSR 0xfffec002 16-bit
  84  * CMCNT 0xfffec004 16-bit
  85  * CMCOR 0xfffec006 16-bit
  86  *
  87  * "32-bit counter and 16-bit control" as found on sh7372, sh73a0, r8a7740:
  88  * CMSTR 0xffca0000 16-bit
  89  * CMCSR 0xffca0060 16-bit
  90  * CMCNT 0xffca0064 32-bit
  91  * CMCOR 0xffca0068 32-bit
  92  *
  93  * "32-bit counter and 32-bit control" as found on r8a73a4 and r8a7790:
  94  * CMSTR 0xffca0500 32-bit
  95  * CMCSR 0xffca0510 32-bit
  96  * CMCNT 0xffca0514 32-bit
  97  * CMCOR 0xffca0518 32-bit
  98  */
  99
 100 static unsigned long sh_cmt_read16(void __iomem *base, unsigned long offs)
 101 {
 102         return ioread16(base + (offs << 1));
 103 }
 104
 105 static unsigned long sh_cmt_read32(void __iomem *base, unsigned long offs)
 106 {
 107         return ioread32(base + (offs << 2));
 108 }
 109
 110 static void sh_cmt_write16(void __iomem *base, unsigned long offs,
 111                            unsigned long value)
 112 {
 113         iowrite16(value, base + (offs << 1));
 114 }
 115
 116 static void sh_cmt_write32(void __iomem *base, unsigned long offs,
 117                            unsigned long value)
 118 {
 119         iowrite32(value, base + (offs << 2));
 120 }
 121
 122 #define CMCSR 0 /* channel register */
 123 #define CMCNT 1 /* channel register */
 124 #define CMCOR 2 /* channel register */
 125
 126 static inline unsigned long sh_cmt_read_cmstr(struct sh_cmt_channel *ch)
 127 {
 128         return ch->cmt->read_control(ch->cmt->mapbase_str, 0);
 129 }
 130
 131 static inline unsigned long sh_cmt_read_cmcsr(struct sh_cmt_channel *ch)
 132 {
 133         return ch->cmt->read_control(ch->cmt->mapbase, CMCSR);
 134 }
 135
 136 static inline unsigned long sh_cmt_read_cmcnt(struct sh_cmt_channel *ch)
 137 {
 138         return ch->cmt->read_count(ch->cmt->mapbase, CMCNT);
 139 }
 140
 141 static inline void sh_cmt_write_cmstr(struct sh_cmt_channel *ch,
 142                                       unsigned long value)
 143 {
 144         ch->cmt->write_control(ch->cmt->mapbase_str, 0, value);
 145 }
 146
 147 static inline void sh_cmt_write_cmcsr(struct sh_cmt_channel *ch,
 148                                       unsigned long value)
 149 {
 150         ch->cmt->write_control(ch->cmt->mapbase, CMCSR, value);
 151 }
 152
 153 static inline void sh_cmt_write_cmcnt(struct sh_cmt_channel *ch,
 154                                       unsigned long value)
 155 {
 156         ch->cmt->write_count(ch->cmt->mapbase, CMCNT, value);
 157 }
 158
 159 static inline void sh_cmt_write_cmcor(struct sh_cmt_channel *ch,
 160                                       unsigned long value)
 161 {
 162         ch->cmt->write_count(ch->cmt->mapbase, CMCOR, value);
 163 }
 164
 165 static unsigned long sh_cmt_get_counter(struct sh_cmt_channel *ch,
 166                                         int *has_wrapped)
 167 {
 168         unsigned long v1, v2, v3;
 169         int o1, o2;
 170
 171         o1 = sh_cmt_read_cmcsr(ch) & ch->cmt->overflow_bit;
 172
 173         /* Make sure the timer value is stable. Stolen from acpi_pm.c */
 174         do {
 175                 o2 = o1;
 176                 v1 = sh_cmt_read_cmcnt(ch);
 177                 v2 = sh_cmt_read_cmcnt(ch);
 178                 v3 = sh_cmt_read_cmcnt(ch);
 179                 o1 = sh_cmt_read_cmcsr(ch) & ch->cmt->overflow_bit;
 180         } while (unlikely((o1 != o2) || (v1 > v2 && v1 < v3)
 181                           || (v2 > v3 && v2 < v1) || (v3 > v1 && v3 < v2)));
 182
 183         *has_wrapped = o1;
 184         return v2;
 185 }
 186
 187 static DEFINE_RAW_SPINLOCK(sh_cmt_lock);
 188
 189 static void sh_cmt_start_stop_ch(struct sh_cmt_channel *ch, int start)
 190 {
 191         struct sh_timer_config *cfg = ch->cmt->pdev->dev.platform_data;
 192         unsigned long flags, value;
 193
 194         /* start stop register shared by multiple timer channels */
 195         raw_spin_lock_irqsave(&sh_cmt_lock, flags);
 196         value = sh_cmt_read_cmstr(ch);
 197
 198         if (start)
 199                 value |= 1 << cfg->timer_bit;
 200         else
 201                 value &= ~(1 << cfg->timer_bit);
 202
 203         sh_cmt_write_cmstr(ch, value);
 204         raw_spin_unlock_irqrestore(&sh_cmt_lock, flags);
 205 }
 206
 207 static int sh_cmt_enable(struct sh_cmt_channel *ch, unsigned long *rate)
 208 {
 209         int k, ret;
 210
 211         pm_runtime_get_sync(&ch->cmt->pdev->dev);
 212         dev_pm_syscore_device(&ch->cmt->pdev->dev, true);
 213
 214         /* enable clock */
 215         ret = clk_enable(ch->cmt->clk);
 216         if (ret) {
 217                 dev_err(&ch->cmt->pdev->dev, "cannot enable clock\n");
 218                 goto err0;
 219         }
 220
 221         /* make sure channel is disabled */
 222         sh_cmt_start_stop_ch(ch, 0);
 223
 224         /* configure channel, periodic mode and maximum timeout */
 225         if (ch->cmt->width == 16) {
 226                 *rate = clk_get_rate(ch->cmt->clk) / 512;
 227                 sh_cmt_write_cmcsr(ch, 0x43);
 228         } else {
 229                 *rate = clk_get_rate(ch->cmt->clk) / 8;
 230                 sh_cmt_write_cmcsr(ch, 0x01a4);
 231         }
 232
 233         sh_cmt_write_cmcor(ch, 0xffffffff);
 234         sh_cmt_write_cmcnt(ch, 0);
 235
 236         /*
 237          * According to the sh73a0 user's manual, as CMCNT can be operated
 238          * only by the RCLK (Pseudo 32 KHz), there's one restriction on
 239          * modifying CMCNT register; two RCLK cycles are necessary before
 240          * this register is either read or any modification of the value
 241          * it holds is reflected in the LSI's actual operation.
 242          *
 243          * While at it, we're supposed to clear out the CMCNT as of this
 244          * moment, so make sure it's processed properly here.  This will
 245          * take RCLKx2 at maximum.
 246          */
 247         for (k = 0; k < 100; k++) {
 248                 if (!sh_cmt_read_cmcnt(ch))
 249                         break;
 250                 udelay(1);
 251         }
 252
 253         if (sh_cmt_read_cmcnt(ch)) {
 254                 dev_err(&ch->cmt->pdev->dev, "cannot clear CMCNT\n");
 255                 ret = -ETIMEDOUT;
 256                 goto err1;
 257         }
 258
 259         /* enable channel */
 260         sh_cmt_start_stop_ch(ch, 1);
 261         return 0;
 262  err1:
 263         /* stop clock */
 264         clk_disable(ch->cmt->clk);
 265
 266  err0:
 267         return ret;
 268 }
 269
 270 static void sh_cmt_disable(struct sh_cmt_channel *ch)
 271 {
 272         /* disable channel */
 273         sh_cmt_start_stop_ch(ch, 0);
 274
 275         /* disable interrupts in CMT block */
 276         sh_cmt_write_cmcsr(ch, 0);
 277
 278         /* stop clock */
 279         clk_disable(ch->cmt->clk);
 280
 281         dev_pm_syscore_device(&ch->cmt->pdev->dev, false);
 282         pm_runtime_put(&ch->cmt->pdev->dev);
 283 }
 284
 285 /* private flags */
 286 #define FLAG_CLOCKEVENT (1 << 0)
 287 #define FLAG_CLOCKSOURCE (1 << 1)
 288 #define FLAG_REPROGRAM (1 << 2)
 289 #define FLAG_SKIPEVENT (1 << 3)
 290 #define FLAG_IRQCONTEXT (1 << 4)
 291
 292 static void sh_cmt_clock_event_program_verify(struct sh_cmt_channel *ch,
 293                                               int absolute)
 294 {
 295         unsigned long new_match;
 296         unsigned long value = ch->next_match_value;
 297         unsigned long delay = 0;
 298         unsigned long now = 0;
 299         int has_wrapped;
 300
 301         now = sh_cmt_get_counter(ch, &has_wrapped);
 302         ch->flags |= FLAG_REPROGRAM; /* force reprogram */
 303
 304         if (has_wrapped) {
 305                 /* we're competing with the interrupt handler.
 306                  *  -> let the interrupt handler reprogram the timer.
 307                  *  -> interrupt number two handles the event.
 308                  */
 309                 ch->flags |= FLAG_SKIPEVENT;
 310                 return;
 311         }
 312
 313         if (absolute)
 314                 now = 0;
 315
 316         do {
 317                 /* reprogram the timer hardware,
 318                  * but don't save the new match value yet.
 319                  */
 320                 new_match = now + value + delay;
 321                 if (new_match > ch->max_match_value)
 322                         new_match = ch->max_match_value;
 323
 324                 sh_cmt_write_cmcor(ch, new_match);
 325
 326                 now = sh_cmt_get_counter(ch, &has_wrapped);
 327                 if (has_wrapped && (new_match > ch->match_value)) {
 328                         /* we are changing to a greater match value,
 329                          * so this wrap must be caused by the counter
 330                          * matching the old value.
 331                          * -> first interrupt reprograms the timer.
 332                          * -> interrupt number two handles the event.
 333                          */
 334                         ch->flags |= FLAG_SKIPEVENT;
 335                         break;
 336                 }
 337
 338                 if (has_wrapped) {
 339                         /* we are changing to a smaller match value,
 340                          * so the wrap must be caused by the counter
 341                          * matching the new value.
 342                          * -> save programmed match value.
 343                          * -> let isr handle the event.
 344                          */
 345                         ch->match_value = new_match;
 346                         break;
 347                 }
 348
 349                 /* be safe: verify hardware settings */
 350                 if (now < new_match) {
 351                         /* timer value is below match value, all good.
 352                          * this makes sure we won't miss any match events.
 353                          * -> save programmed match value.
 354                          * -> let isr handle the event.
 355                          */
 356                         ch->match_value = new_match;
 357                         break;
 358                 }
 359
 360                 /* the counter has reached a value greater
 361                  * than our new match value. and since the
 362                  * has_wrapped flag isn't set we must have
 363                  * programmed a too close event.
 364                  * -> increase delay and retry.
 365                  */
 366                 if (delay)
 367                         delay <<= 1;
 368                 else
 369                         delay = 1;
 370
 371                 if (!delay)
 372                         dev_warn(&ch->cmt->pdev->dev, "too long delay\n");
 373
 374         } while (delay);
 375 }
 376
 377 static void __sh_cmt_set_next(struct sh_cmt_channel *ch, unsigned long delta)
 378 {
 379         if (delta > ch->max_match_value)
 380                 dev_warn(&ch->cmt->pdev->dev, "delta out of range\n");
 381
 382         ch->next_match_value = delta;
 383         sh_cmt_clock_event_program_verify(ch, 0);
 384 }
 385
 386 static void sh_cmt_set_next(struct sh_cmt_channel *ch, unsigned long delta)
 387 {
 388         unsigned long flags;
 389
 390         raw_spin_lock_irqsave(&ch->lock, flags);
 391         __sh_cmt_set_next(ch, delta);
 392         raw_spin_unlock_irqrestore(&ch->lock, flags);
 393 }
 394
 395 static irqreturn_t sh_cmt_interrupt(int irq, void *dev_id)
 396 {
 397         struct sh_cmt_channel *ch = dev_id;
 398
 399         /* clear flags */
 400         sh_cmt_write_cmcsr(ch, sh_cmt_read_cmcsr(ch) & ch->cmt->clear_bits);
 401
 402         /* update clock source counter to begin with if enabled
 403          * the wrap flag should be cleared by the timer specific
 404          * isr before we end up here.
 405          */
 406         if (ch->flags & FLAG_CLOCKSOURCE)
 407                 ch->total_cycles += ch->match_value + 1;
 408
 409         if (!(ch->flags & FLAG_REPROGRAM))
 410                 ch->next_match_value = ch->max_match_value;
 411
 412         ch->flags |= FLAG_IRQCONTEXT;
 413
 414         if (ch->flags & FLAG_CLOCKEVENT) {
 415                 if (!(ch->flags & FLAG_SKIPEVENT)) {
 416                         if (ch->ced.mode == CLOCK_EVT_MODE_ONESHOT) {
 417                                 ch->next_match_value = ch->max_match_value;
 418                                 ch->flags |= FLAG_REPROGRAM;
 419                         }
 420
 421                         ch->ced.event_handler(&ch->ced);
 422                 }
 423         }
 424
 425         ch->flags &= ~FLAG_SKIPEVENT;
 426
 427         if (ch->flags & FLAG_REPROGRAM) {
 428                 ch->flags &= ~FLAG_REPROGRAM;
 429                 sh_cmt_clock_event_program_verify(ch, 1);
 430
 431                 if (ch->flags & FLAG_CLOCKEVENT)
 432                         if ((ch->ced.mode == CLOCK_EVT_MODE_SHUTDOWN)
 433                             || (ch->match_value == ch->next_match_value))
 434                                 ch->flags &= ~FLAG_REPROGRAM;
 435         }
 436
 437         ch->flags &= ~FLAG_IRQCONTEXT;
 438
 439         return IRQ_HANDLED;
 440 }
 441
 442 static int sh_cmt_start(struct sh_cmt_channel *ch, unsigned long flag)
 443 {
 444         int ret = 0;
 445         unsigned long flags;
 446
 447         raw_spin_lock_irqsave(&ch->lock, flags);
 448
 449         if (!(ch->flags & (FLAG_CLOCKEVENT | FLAG_CLOCKSOURCE)))
 450                 ret = sh_cmt_enable(ch, &ch->rate);
 451
 452         if (ret)
 453                 goto out;
 454         ch->flags |= flag;
 455
 456         /* setup timeout if no clockevent */
 457         if ((flag == FLAG_CLOCKSOURCE) && (!(ch->flags & FLAG_CLOCKEVENT)))
 458                 __sh_cmt_set_next(ch, ch->max_match_value);
 459  out:
 460         raw_spin_unlock_irqrestore(&ch->lock, flags);
 461
 462         return ret;
 463 }
 464
 465 static void sh_cmt_stop(struct sh_cmt_channel *ch, unsigned long flag)
 466 {
 467         unsigned long flags;
 468         unsigned long f;
 469
 470         raw_spin_lock_irqsave(&ch->lock, flags);
 471
 472         f = ch->flags & (FLAG_CLOCKEVENT | FLAG_CLOCKSOURCE);
 473         ch->flags &= ~flag;
 474
 475         if (f && !(ch->flags & (FLAG_CLOCKEVENT | FLAG_CLOCKSOURCE)))
 476                 sh_cmt_disable(ch);
 477
 478         /* adjust the timeout to maximum if only clocksource left */
 479         if ((flag == FLAG_CLOCKEVENT) && (ch->flags & FLAG_CLOCKSOURCE))
 480                 __sh_cmt_set_next(ch, ch->max_match_value);
 481
 482         raw_spin_unlock_irqrestore(&ch->lock, flags);
 483 }
 484
 485 static struct sh_cmt_channel *cs_to_sh_cmt(struct clocksource *cs)
 486 {
 487         return container_of(cs, struct sh_cmt_channel, cs);
 488 }
 489
 490 static cycle_t sh_cmt_clocksource_read(struct clocksource *cs)
 491 {
 492         struct sh_cmt_channel *ch = cs_to_sh_cmt(cs);
 493         unsigned long flags, raw;
 494         unsigned long value;
 495         int has_wrapped;
 496
 497         raw_spin_lock_irqsave(&ch->lock, flags);
 498         value = ch->total_cycles;
 499         raw = sh_cmt_get_counter(ch, &has_wrapped);
 500
 501         if (unlikely(has_wrapped))
 502                 raw += ch->match_value + 1;
 503         raw_spin_unlock_irqrestore(&ch->lock, flags);
 504
 505         return value + raw;
 506 }
 507
 508 static int sh_cmt_clocksource_enable(struct clocksource *cs)
 509 {
 510         int ret;
 511         struct sh_cmt_channel *ch = cs_to_sh_cmt(cs);
 512
 513         WARN_ON(ch->cs_enabled);
 514
 515         ch->total_cycles = 0;
 516
 517         ret = sh_cmt_start(ch, FLAG_CLOCKSOURCE);
 518         if (!ret) {
 519                 __clocksource_updatefreq_hz(cs, ch->rate);
 520                 ch->cs_enabled = true;
 521         }
 522         return ret;
 523 }
 524
 525 static void sh_cmt_clocksource_disable(struct clocksource *cs)
 526 {
 527         struct sh_cmt_channel *ch = cs_to_sh_cmt(cs);
 528
 529         WARN_ON(!ch->cs_enabled);
 530
 531         sh_cmt_stop(ch, FLAG_CLOCKSOURCE);
 532         ch->cs_enabled = false;
 533 }
 534
 535 static void sh_cmt_clocksource_suspend(struct clocksource *cs)
 536 {
 537         struct sh_cmt_channel *ch = cs_to_sh_cmt(cs);
 538
 539         sh_cmt_stop(ch, FLAG_CLOCKSOURCE);
 540         pm_genpd_syscore_poweroff(&ch->cmt->pdev->dev);
 541 }
 542
 543 static void sh_cmt_clocksource_resume(struct clocksource *cs)
 544 {
 545         struct sh_cmt_channel *ch = cs_to_sh_cmt(cs);
 546
 547         pm_genpd_syscore_poweron(&ch->cmt->pdev->dev);
 548         sh_cmt_start(ch, FLAG_CLOCKSOURCE);
 549 }
 550
 551 static int sh_cmt_register_clocksource(struct sh_cmt_channel *ch,
 552                                        char *name, unsigned long rating)
 553 {
 554         struct clocksource *cs = &ch->cs;
 555
 556         cs->name = name;
 557         cs->rating = rating;
 558         cs->read = sh_cmt_clocksource_read;
 559         cs->enable = sh_cmt_clocksource_enable;
 560         cs->disable = sh_cmt_clocksource_disable;
 561         cs->suspend = sh_cmt_clocksource_suspend;
 562         cs->resume = sh_cmt_clocksource_resume;
 563         cs->mask = CLOCKSOURCE_MASK(sizeof(unsigned long) * 8);
 564         cs->flags = CLOCK_SOURCE_IS_CONTINUOUS;
 565
 566         dev_info(&ch->cmt->pdev->dev, "used as clock source\n");
 567
 568         /* Register with dummy 1 Hz value, gets updated in ->enable() */
 569         clocksource_register_hz(cs, 1);
 570         return 0;
 571 }
 572
 573 static struct sh_cmt_channel *ced_to_sh_cmt(struct clock_event_device *ced)
 574 {
 575         return container_of(ced, struct sh_cmt_channel, ced);
 576 }
 577
 578 static void sh_cmt_clock_event_start(struct sh_cmt_channel *ch, int periodic)
 579 {
 580         struct clock_event_device *ced = &ch->ced;
 581
 582         sh_cmt_start(ch, FLAG_CLOCKEVENT);
 583
 584         /* TODO: calculate good shift from rate and counter bit width */
 585
 586         ced->shift = 32;
 587         ced->mult = div_sc(ch->rate, NSEC_PER_SEC, ced->shift);
 588         ced->max_delta_ns = clockevent_delta2ns(ch->max_match_value, ced);
 589         ced->min_delta_ns = clockevent_delta2ns(0x1f, ced);
 590
 591         if (periodic)
 592                 sh_cmt_set_next(ch, ((ch->rate + HZ/2) / HZ) - 1);
 593         else
 594                 sh_cmt_set_next(ch, ch->max_match_value);
 595 }
 596
 597 static void sh_cmt_clock_event_mode(enum clock_event_mode mode,
 598                                     struct clock_event_device *ced)
 599 {
 600         struct sh_cmt_channel *ch = ced_to_sh_cmt(ced);
 601
 602         /* deal with old setting first */
 603         switch (ced->mode) {
 604         case CLOCK_EVT_MODE_PERIODIC:
 605         case CLOCK_EVT_MODE_ONESHOT:
 606                 sh_cmt_stop(ch, FLAG_CLOCKEVENT);
 607                 break;
 608         default:
 609                 break;
 610         }
 611
 612         switch (mode) {
 613         case CLOCK_EVT_MODE_PERIODIC:
 614                 dev_info(&ch->cmt->pdev->dev,
 615                          "used for periodic clock events\n");
 616                 sh_cmt_clock_event_start(ch, 1);
 617                 break;
 618         case CLOCK_EVT_MODE_ONESHOT:
 619                 dev_info(&ch->cmt->pdev->dev,
 620                          "used for oneshot clock events\n");
 621                 sh_cmt_clock_event_start(ch, 0);
 622                 break;
 623         case CLOCK_EVT_MODE_SHUTDOWN:
 624         case CLOCK_EVT_MODE_UNUSED:
 625                 sh_cmt_stop(ch, FLAG_CLOCKEVENT);
 626                 break;
 627         default:
 628                 break;
 629         }
 630 }
 631
 632 static int sh_cmt_clock_event_next(unsigned long delta,
 633                                    struct clock_event_device *ced)
 634 {
 635         struct sh_cmt_channel *ch = ced_to_sh_cmt(ced);
 636
 637         BUG_ON(ced->mode != CLOCK_EVT_MODE_ONESHOT);
 638         if (likely(ch->flags & FLAG_IRQCONTEXT))
 639                 ch->next_match_value = delta - 1;
 640         else
 641                 sh_cmt_set_next(ch, delta - 1);
 642
 643         return 0;
 644 }
 645
 646 static void sh_cmt_clock_event_suspend(struct clock_event_device *ced)
 647 {
 648         struct sh_cmt_channel *ch = ced_to_sh_cmt(ced);
 649
 650         pm_genpd_syscore_poweroff(&ch->cmt->pdev->dev);
 651         clk_unprepare(ch->cmt->clk);
 652 }
 653
 654 static void sh_cmt_clock_event_resume(struct clock_event_device *ced)
 655 {
 656         struct sh_cmt_channel *ch = ced_to_sh_cmt(ced);
 657
 658         clk_prepare(ch->cmt->clk);
 659         pm_genpd_syscore_poweron(&ch->cmt->pdev->dev);
 660 }
 661
 662 static void sh_cmt_register_clockevent(struct sh_cmt_channel *ch,
 663                                        char *name, unsigned long rating)
 664 {
 665         struct clock_event_device *ced = &ch->ced;
 666
 667         memset(ced, 0, sizeof(*ced));
 668
 669         ced->name = name;
 670         ced->features = CLOCK_EVT_FEAT_PERIODIC;
 671         ced->features |= CLOCK_EVT_FEAT_ONESHOT;
 672         ced->rating = rating;
 673         ced->cpumask = cpumask_of(0);
 674         ced->set_next_event = sh_cmt_clock_event_next;
 675         ced->set_mode = sh_cmt_clock_event_mode;
 676         ced->suspend = sh_cmt_clock_event_suspend;
 677         ced->resume = sh_cmt_clock_event_resume;
 678
 679         dev_info(&ch->cmt->pdev->dev, "used for clock events\n");
 680         clockevents_register_device(ced);
 681 }
 682
 683 static int sh_cmt_register(struct sh_cmt_channel *ch, char *name,
 684                            unsigned long clockevent_rating,
 685                            unsigned long clocksource_rating)
 686 {
 687         if (clockevent_rating)
 688                 sh_cmt_register_clockevent(ch, name, clockevent_rating);
 689
 690         if (clocksource_rating)
 691                 sh_cmt_register_clocksource(ch, name, clocksource_rating);
 692
 693         return 0;
 694 }
 695
 696 static int sh_cmt_setup_channel(struct sh_cmt_channel *ch,
 697                                 struct sh_cmt_device *cmt)
 698 {
 699         struct sh_timer_config *cfg = cmt->pdev->dev.platform_data;
 700         int irq;
 701         int ret;
 702
 703         memset(ch, 0, sizeof(*ch));
 704         ch->cmt = cmt;
 705
 706         irq = platform_get_irq(cmt->pdev, 0);
 707         if (irq < 0) {
 708                 dev_err(&cmt->pdev->dev, "failed to get irq\n");
 709                 return irq;
 710         }
 711
 712         if (cmt->width == (sizeof(ch->max_match_value) * 8))
 713                 ch->max_match_value = ~0;
 714         else
 715                 ch->max_match_value = (1 << cmt->width) - 1;
 716
 717         ch->match_value = ch->max_match_value;
 718         raw_spin_lock_init(&ch->lock);
 719
 720         ret = sh_cmt_register(ch, (char *)dev_name(&cmt->pdev->dev),
 721                               cfg->clockevent_rating,
 722                               cfg->clocksource_rating);
 723         if (ret) {
 724                 dev_err(&cmt->pdev->dev, "registration failed\n");
 725                 return ret;
 726         }
 727         ch->cs_enabled = false;
 728
 729         ret = request_irq(irq, sh_cmt_interrupt,
 730                           IRQF_TIMER | IRQF_IRQPOLL | IRQF_NOBALANCING,
 731                           dev_name(&cmt->pdev->dev), ch);
 732         if (ret) {
 733                 dev_err(&cmt->pdev->dev, "failed to request irq %d\n", irq);
 734                 return ret;
 735         }
 736
 737         return 0;
 738 }
 739
 740 static int sh_cmt_setup(struct sh_cmt_device *cmt, struct platform_device *pdev)
 741 {
 742         struct sh_timer_config *cfg = pdev->dev.platform_data;
 743         struct resource *res, *res2;
 744         int ret;
 745         ret = -ENXIO;
 746
 747         memset(cmt, 0, sizeof(*cmt));
 748         cmt->pdev = pdev;
 749
 750         if (!cfg) {
 751                 dev_err(&cmt->pdev->dev, "missing platform data\n");
 752                 goto err0;
 753         }
 754
 755         res = platform_get_resource(cmt->pdev, IORESOURCE_MEM, 0);
 756         if (!res) {
 757                 dev_err(&cmt->pdev->dev, "failed to get I/O memory\n");
 758                 goto err0;
 759         }
 760
 761         /* optional resource for the shared timer start/stop register */
 762         res2 = platform_get_resource(cmt->pdev, IORESOURCE_MEM, 1);
 763
 764         /* map memory, let mapbase point to our channel */
 765         cmt->mapbase = ioremap_nocache(res->start, resource_size(res));
 766         if (cmt->mapbase == NULL) {
 767                 dev_err(&cmt->pdev->dev, "failed to remap I/O memory\n");
 768                 goto err0;
 769         }
 770
 771         /* map second resource for CMSTR */
 772         cmt->mapbase_str = ioremap_nocache(res2 ? res2->start :
 773                                            res->start - cfg->channel_offset,
 774                                            res2 ? resource_size(res2) : 2);
 775         if (cmt->mapbase_str == NULL) {
 776                 dev_err(&cmt->pdev->dev, "failed to remap I/O second memory\n");
 777                 goto err1;
 778         }
 779
 780         /* get hold of clock */
 781         cmt->clk = clk_get(&cmt->pdev->dev, "cmt_fck");
 782         if (IS_ERR(cmt->clk)) {
 783                 dev_err(&cmt->pdev->dev, "cannot get clock\n");
 784                 ret = PTR_ERR(cmt->clk);
 785                 goto err2;
 786         }
 787
 788         ret = clk_prepare(cmt->clk);
 789         if (ret < 0)
 790                 goto err3;
 791
 792         if (res2 && (resource_size(res2) == 4)) {
 793                 /* assume both CMSTR and CMCSR to be 32-bit */
 794                 cmt->read_control = sh_cmt_read32;
 795                 cmt->write_control = sh_cmt_write32;
 796         } else {
 797                 cmt->read_control = sh_cmt_read16;
 798                 cmt->write_control = sh_cmt_write16;
 799         }
 800
 801         if (resource_size(res) == 6) {
 802                 cmt->width = 16;
 803                 cmt->read_count = sh_cmt_read16;
 804                 cmt->write_count = sh_cmt_write16;
 805                 cmt->overflow_bit = 0x80;
 806                 cmt->clear_bits = ~0x80;
 807         } else {
 808                 cmt->width = 32;
 809                 cmt->read_count = sh_cmt_read32;
 810                 cmt->write_count = sh_cmt_write32;
 811                 cmt->overflow_bit = 0x8000;
 812                 cmt->clear_bits = ~0xc000;
 813         }
 814
 815         ret = sh_cmt_setup_channel(&cmt->channel, cmt);
 816         if (ret < 0)
 817                 goto err4;
 818
 819         platform_set_drvdata(pdev, cmt);
 820
 821         return 0;
 822 err4:
 823         clk_unprepare(cmt->clk);
 824 err3:
 825         clk_put(cmt->clk);
 826 err2:
 827         iounmap(cmt->mapbase_str);
 828 err1:
 829         iounmap(cmt->mapbase);
 830 err0:
 831         return ret;
 832 }
 833
 834 static int sh_cmt_probe(struct platform_device *pdev)
 835 {
 836         struct sh_cmt_device *cmt = platform_get_drvdata(pdev);
 837         struct sh_timer_config *cfg = pdev->dev.platform_data;
 838         int ret;
 839
 840         if (!is_early_platform_device(pdev)) {
 841                 pm_runtime_set_active(&pdev->dev);
 842                 pm_runtime_enable(&pdev->dev);
 843         }
 844
 845         if (cmt) {
 846                 dev_info(&pdev->dev, "kept as earlytimer\n");
 847                 goto out;
 848         }
 849
 850         cmt = kmalloc(sizeof(*cmt), GFP_KERNEL);
 851         if (cmt == NULL) {
 852                 dev_err(&pdev->dev, "failed to allocate driver data\n");
 853                 return -ENOMEM;
 854         }
 855
 856         ret = sh_cmt_setup(cmt, pdev);
 857         if (ret) {
 858                 kfree(cmt);
 859                 pm_runtime_idle(&pdev->dev);
 860                 return ret;
 861         }
 862         if (is_early_platform_device(pdev))
 863                 return 0;
 864
 865  out:
 866         if (cfg->clockevent_rating || cfg->clocksource_rating)
 867                 pm_runtime_irq_safe(&pdev->dev);
 868         else
 869                 pm_runtime_idle(&pdev->dev);
 870
 871         return 0;
 872 }
 873
 874 static int sh_cmt_remove(struct platform_device *pdev)
 875 {
 876         return -EBUSY; /* cannot unregister clockevent and clocksource */
 877 }
 878
 879 static struct platform_driver sh_cmt_device_driver = {
 880         .probe          = sh_cmt_probe,
 881         .remove         = sh_cmt_remove,
 882         .driver         = {
 883                 .name   = "sh_cmt",
 884         }
 885 };
 886
 887 static int __init sh_cmt_init(void)
 888 {
 889         return platform_driver_register(&sh_cmt_device_driver);
 890 }
 891
 892 static void __exit sh_cmt_exit(void)
 893 {
 894         platform_driver_unregister(&sh_cmt_device_driver);
 895 }
 896
 897 early_platform_init("earlytimer", &sh_cmt_device_driver);
 898 subsys_initcall(sh_cmt_init);
 899 module_exit(sh_cmt_exit);
 900
 901 MODULE_AUTHOR("Magnus Damm");
 902 MODULE_DESCRIPTION("SuperH CMT Timer Driver");
 903 MODULE_LICENSE("GPL v2");