drivers/clocksource/exynos_mct.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /* linux/arch/arm/mach-exynos4/mct.c
   3  *
   4  * Copyright (c) 2011 Samsung Electronics Co., Ltd.
   5  *              http://www.samsung.com
   6  *
   7  * Exynos4 MCT(Multi-Core Timer) support
   8 */
   9
  10 #include <linux/interrupt.h>
  11 #include <linux/irq.h>
  12 #include <linux/err.h>
  13 #include <linux/clk.h>
  14 #include <linux/clockchips.h>
  15 #include <linux/cpu.h>
  16 #include <linux/delay.h>
  17 #include <linux/percpu.h>
  18 #include <linux/of.h>
  19 #include <linux/of_irq.h>
  20 #include <linux/of_address.h>
  21 #include <linux/clocksource.h>
  22 #include <linux/sched_clock.h>
  23
  24 #define EXYNOS4_MCTREG(x)               (x)
  25 #define EXYNOS4_MCT_G_CNT_L             EXYNOS4_MCTREG(0x100)
  26 #define EXYNOS4_MCT_G_CNT_U             EXYNOS4_MCTREG(0x104)
  27 #define EXYNOS4_MCT_G_CNT_WSTAT         EXYNOS4_MCTREG(0x110)
  28 #define EXYNOS4_MCT_G_COMP0_L           EXYNOS4_MCTREG(0x200)
  29 #define EXYNOS4_MCT_G_COMP0_U           EXYNOS4_MCTREG(0x204)
  30 #define EXYNOS4_MCT_G_COMP0_ADD_INCR    EXYNOS4_MCTREG(0x208)
  31 #define EXYNOS4_MCT_G_TCON              EXYNOS4_MCTREG(0x240)
  32 #define EXYNOS4_MCT_G_INT_CSTAT         EXYNOS4_MCTREG(0x244)
  33 #define EXYNOS4_MCT_G_INT_ENB           EXYNOS4_MCTREG(0x248)
  34 #define EXYNOS4_MCT_G_WSTAT             EXYNOS4_MCTREG(0x24C)
  35 #define _EXYNOS4_MCT_L_BASE             EXYNOS4_MCTREG(0x300)
  36 #define EXYNOS4_MCT_L_BASE(x)           (_EXYNOS4_MCT_L_BASE + (0x100 * x))
  37 #define EXYNOS4_MCT_L_MASK              (0xffffff00)
  38
  39 #define MCT_L_TCNTB_OFFSET              (0x00)
  40 #define MCT_L_ICNTB_OFFSET              (0x08)
  41 #define MCT_L_TCON_OFFSET               (0x20)
  42 #define MCT_L_INT_CSTAT_OFFSET          (0x30)
  43 #define MCT_L_INT_ENB_OFFSET            (0x34)
  44 #define MCT_L_WSTAT_OFFSET              (0x40)
  45 #define MCT_G_TCON_START                (1 << 8)
  46 #define MCT_G_TCON_COMP0_AUTO_INC       (1 << 1)
  47 #define MCT_G_TCON_COMP0_ENABLE         (1 << 0)
  48 #define MCT_L_TCON_INTERVAL_MODE        (1 << 2)
  49 #define MCT_L_TCON_INT_START            (1 << 1)
  50 #define MCT_L_TCON_TIMER_START          (1 << 0)
  51
  52 #define TICK_BASE_CNT   1
  53
  54 #ifdef CONFIG_ARM
  55 /* Use values higher than ARM arch timer. See 6282edb72bed. */
  56 #define MCT_CLKSOURCE_RATING            450
  57 #define MCT_CLKEVENTS_RATING            500
  58 #else
  59 #define MCT_CLKSOURCE_RATING            350
  60 #define MCT_CLKEVENTS_RATING            350
  61 #endif
  62
  63 /* There are four Global timers starting with 0 offset */
  64 #define MCT_G0_IRQ      0
  65 /* Local timers count starts after global timer count */
  66 #define MCT_L0_IRQ      4
  67 /* Max number of IRQ as per DT binding document */
  68 #define MCT_NR_IRQS     20
  69
  70 enum {
  71         MCT_INT_SPI,
  72         MCT_INT_PPI
  73 };
  74
  75 static void __iomem *reg_base;
  76 static unsigned long clk_rate;
  77 static unsigned int mct_int_type;
  78 static int mct_irqs[MCT_NR_IRQS];
  79
  80 struct mct_clock_event_device {
  81         struct clock_event_device evt;
  82         unsigned long base;
  83         /**
  84          *  The length of the name must be adjusted if number of
  85          *  local timer interrupts grow over two digits
  86          */
  87         char name[11];
  88 };
  89
  90 static void exynos4_mct_write(unsigned int value, unsigned long offset)
  91 {
  92         unsigned long stat_addr;
  93         u32 mask;
  94         u32 i;
  95
  96         writel_relaxed(value, reg_base + offset);
  97
  98         if (likely(offset >= EXYNOS4_MCT_L_BASE(0))) {
  99                 stat_addr = (offset & EXYNOS4_MCT_L_MASK) + MCT_L_WSTAT_OFFSET;
 100                 switch (offset & ~EXYNOS4_MCT_L_MASK) {
 101                 case MCT_L_TCON_OFFSET:
 102                         mask = 1 << 3;          /* L_TCON write status */
 103                         break;
 104                 case MCT_L_ICNTB_OFFSET:
 105                         mask = 1 << 1;          /* L_ICNTB write status */
 106                         break;
 107                 case MCT_L_TCNTB_OFFSET:
 108                         mask = 1 << 0;          /* L_TCNTB write status */
 109                         break;
 110                 default:
 111                         return;
 112                 }
 113         } else {
 114                 switch (offset) {
 115                 case EXYNOS4_MCT_G_TCON:
 116                         stat_addr = EXYNOS4_MCT_G_WSTAT;
 117                         mask = 1 << 16;         /* G_TCON write status */
 118                         break;
 119                 case EXYNOS4_MCT_G_COMP0_L:
 120                         stat_addr = EXYNOS4_MCT_G_WSTAT;
 121                         mask = 1 << 0;          /* G_COMP0_L write status */
 122                         break;
 123                 case EXYNOS4_MCT_G_COMP0_U:
 124                         stat_addr = EXYNOS4_MCT_G_WSTAT;
 125                         mask = 1 << 1;          /* G_COMP0_U write status */
 126                         break;
 127                 case EXYNOS4_MCT_G_COMP0_ADD_INCR:
 128                         stat_addr = EXYNOS4_MCT_G_WSTAT;
 129                         mask = 1 << 2;          /* G_COMP0_ADD_INCR w status */
 130                         break;
 131                 case EXYNOS4_MCT_G_CNT_L:
 132                         stat_addr = EXYNOS4_MCT_G_CNT_WSTAT;
 133                         mask = 1 << 0;          /* G_CNT_L write status */
 134                         break;
 135                 case EXYNOS4_MCT_G_CNT_U:
 136                         stat_addr = EXYNOS4_MCT_G_CNT_WSTAT;
 137                         mask = 1 << 1;          /* G_CNT_U write status */
 138                         break;
 139                 default:
 140                         return;
 141                 }
 142         }
 143
 144         /* Wait maximum 1 ms until written values are applied */
 145         for (i = 0; i < loops_per_jiffy / 1000 * HZ; i++)
 146                 if (readl_relaxed(reg_base + stat_addr) & mask) {
 147                         writel_relaxed(mask, reg_base + stat_addr);
 148                         return;
 149                 }
 150
 151         panic("MCT hangs after writing %d (offset:0x%lx)\n", value, offset);
 152 }
 153
 154 /* Clocksource handling */
 155 static void exynos4_mct_frc_start(void)
 156 {
 157         u32 reg;
 158
 159         reg = readl_relaxed(reg_base + EXYNOS4_MCT_G_TCON);
 160         reg |= MCT_G_TCON_START;
 161         exynos4_mct_write(reg, EXYNOS4_MCT_G_TCON);
 162 }
 163
 164 /**
 165  * exynos4_read_count_64 - Read all 64-bits of the global counter
 166  *
 167  * This will read all 64-bits of the global counter taking care to make sure
 168  * that the upper and lower half match.  Note that reading the MCT can be quite
 169  * slow (hundreds of nanoseconds) so you should use the 32-bit (lower half
 170  * only) version when possible.
 171  *
 172  * Returns the number of cycles in the global counter.
 173  */
 174 static u64 exynos4_read_count_64(void)
 175 {
 176         unsigned int lo, hi;
 177         u32 hi2 = readl_relaxed(reg_base + EXYNOS4_MCT_G_CNT_U);
 178
 179         do {
 180                 hi = hi2;
 181                 lo = readl_relaxed(reg_base + EXYNOS4_MCT_G_CNT_L);
 182                 hi2 = readl_relaxed(reg_base + EXYNOS4_MCT_G_CNT_U);
 183         } while (hi != hi2);
 184
 185         return ((u64)hi << 32) | lo;
 186 }
 187
 188 /**
 189  * exynos4_read_count_32 - Read the lower 32-bits of the global counter
 190  *
 191  * This will read just the lower 32-bits of the global counter.  This is marked
 192  * as notrace so it can be used by the scheduler clock.
 193  *
 194  * Returns the number of cycles in the global counter (lower 32 bits).
 195  */
 196 static u32 notrace exynos4_read_count_32(void)
 197 {
 198         return readl_relaxed(reg_base + EXYNOS4_MCT_G_CNT_L);
 199 }
 200
 201 static u64 exynos4_frc_read(struct clocksource *cs)
 202 {
 203         return exynos4_read_count_32();
 204 }
 205
 206 static void exynos4_frc_resume(struct clocksource *cs)
 207 {
 208         exynos4_mct_frc_start();
 209 }
 210
 211 static struct clocksource mct_frc = {
 212         .name           = "mct-frc",
 213         .rating         = MCT_CLKSOURCE_RATING,
 214         .read           = exynos4_frc_read,
 215         .mask           = CLOCKSOURCE_MASK(32),
 216         .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
 217         .resume         = exynos4_frc_resume,
 218 };
 219
 220 static u64 notrace exynos4_read_sched_clock(void)
 221 {
 222         return exynos4_read_count_32();
 223 }
 224
 225 #if defined(CONFIG_ARM)
 226 static struct delay_timer exynos4_delay_timer;
 227
 228 static cycles_t exynos4_read_current_timer(void)
 229 {
 230         BUILD_BUG_ON_MSG(sizeof(cycles_t) != sizeof(u32),
 231                          "cycles_t needs to move to 32-bit for ARM64 usage");
 232         return exynos4_read_count_32();
 233 }
 234 #endif
 235
 236 static int __init exynos4_clocksource_init(void)
 237 {
 238         exynos4_mct_frc_start();
 239
 240 #if defined(CONFIG_ARM)
 241         exynos4_delay_timer.read_current_timer = &exynos4_read_current_timer;
 242         exynos4_delay_timer.freq = clk_rate;
 243         register_current_timer_delay(&exynos4_delay_timer);
 244 #endif
 245
 246         if (clocksource_register_hz(&mct_frc, clk_rate))
 247                 panic("%s: can't register clocksource\n", mct_frc.name);
 248
 249         sched_clock_register(exynos4_read_sched_clock, 32, clk_rate);
 250
 251         return 0;
 252 }
 253
 254 static void exynos4_mct_comp0_stop(void)
 255 {
 256         unsigned int tcon;
 257
 258         tcon = readl_relaxed(reg_base + EXYNOS4_MCT_G_TCON);
 259         tcon &= ~(MCT_G_TCON_COMP0_ENABLE | MCT_G_TCON_COMP0_AUTO_INC);
 260
 261         exynos4_mct_write(tcon, EXYNOS4_MCT_G_TCON);
 262         exynos4_mct_write(0, EXYNOS4_MCT_G_INT_ENB);
 263 }
 264
 265 static void exynos4_mct_comp0_start(bool periodic, unsigned long cycles)
 266 {
 267         unsigned int tcon;
 268         u64 comp_cycle;
 269
 270         tcon = readl_relaxed(reg_base + EXYNOS4_MCT_G_TCON);
 271
 272         if (periodic) {
 273                 tcon |= MCT_G_TCON_COMP0_AUTO_INC;
 274                 exynos4_mct_write(cycles, EXYNOS4_MCT_G_COMP0_ADD_INCR);
 275         }
 276
 277         comp_cycle = exynos4_read_count_64() + cycles;
 278         exynos4_mct_write((u32)comp_cycle, EXYNOS4_MCT_G_COMP0_L);
 279         exynos4_mct_write((u32)(comp_cycle >> 32), EXYNOS4_MCT_G_COMP0_U);
 280
 281         exynos4_mct_write(0x1, EXYNOS4_MCT_G_INT_ENB);
 282
 283         tcon |= MCT_G_TCON_COMP0_ENABLE;
 284         exynos4_mct_write(tcon , EXYNOS4_MCT_G_TCON);
 285 }
 286
 287 static int exynos4_comp_set_next_event(unsigned long cycles,
 288                                        struct clock_event_device *evt)
 289 {
 290         exynos4_mct_comp0_start(false, cycles);
 291
 292         return 0;
 293 }
 294
 295 static int mct_set_state_shutdown(struct clock_event_device *evt)
 296 {
 297         exynos4_mct_comp0_stop();
 298         return 0;
 299 }
 300
 301 static int mct_set_state_periodic(struct clock_event_device *evt)
 302 {
 303         unsigned long cycles_per_jiffy;
 304
 305         cycles_per_jiffy = (((unsigned long long)NSEC_PER_SEC / HZ * evt->mult)
 306                             >> evt->shift);
 307         exynos4_mct_comp0_stop();
 308         exynos4_mct_comp0_start(true, cycles_per_jiffy);
 309         return 0;
 310 }
 311
 312 static struct clock_event_device mct_comp_device = {
 313         .name                   = "mct-comp",
 314         .features               = CLOCK_EVT_FEAT_PERIODIC |
 315                                   CLOCK_EVT_FEAT_ONESHOT,
 316         .rating                 = 250,
 317         .set_next_event         = exynos4_comp_set_next_event,
 318         .set_state_periodic     = mct_set_state_periodic,
 319         .set_state_shutdown     = mct_set_state_shutdown,
 320         .set_state_oneshot      = mct_set_state_shutdown,
 321         .set_state_oneshot_stopped = mct_set_state_shutdown,
 322         .tick_resume            = mct_set_state_shutdown,
 323 };
 324
 325 static irqreturn_t exynos4_mct_comp_isr(int irq, void *dev_id)
 326 {
 327         struct clock_event_device *evt = dev_id;
 328
 329         exynos4_mct_write(0x1, EXYNOS4_MCT_G_INT_CSTAT);
 330
 331         evt->event_handler(evt);
 332
 333         return IRQ_HANDLED;
 334 }
 335
 336 static int exynos4_clockevent_init(void)
 337 {
 338         mct_comp_device.cpumask = cpumask_of(0);
 339         clockevents_config_and_register(&mct_comp_device, clk_rate,
 340                                         0xf, 0xffffffff);
 341         if (request_irq(mct_irqs[MCT_G0_IRQ], exynos4_mct_comp_isr,
 342                         IRQF_TIMER | IRQF_IRQPOLL, "mct_comp_irq",
 343                         &mct_comp_device))
 344                 pr_err("%s: request_irq() failed\n", "mct_comp_irq");
 345
 346         return 0;
 347 }
 348
 349 static DEFINE_PER_CPU(struct mct_clock_event_device, percpu_mct_tick);
 350
 351 /* Clock event handling */
 352 static void exynos4_mct_tick_stop(struct mct_clock_event_device *mevt)
 353 {
 354         unsigned long tmp;
 355         unsigned long mask = MCT_L_TCON_INT_START | MCT_L_TCON_TIMER_START;
 356         unsigned long offset = mevt->base + MCT_L_TCON_OFFSET;
 357
 358         tmp = readl_relaxed(reg_base + offset);
 359         if (tmp & mask) {
 360                 tmp &= ~mask;
 361                 exynos4_mct_write(tmp, offset);
 362         }
 363 }
 364
 365 static void exynos4_mct_tick_start(unsigned long cycles,
 366                                    struct mct_clock_event_device *mevt)
 367 {
 368         unsigned long tmp;
 369
 370         exynos4_mct_tick_stop(mevt);
 371
 372         tmp = (1 << 31) | cycles;       /* MCT_L_UPDATE_ICNTB */
 373
 374         /* update interrupt count buffer */
 375         exynos4_mct_write(tmp, mevt->base + MCT_L_ICNTB_OFFSET);
 376
 377         /* enable MCT tick interrupt */
 378         exynos4_mct_write(0x1, mevt->base + MCT_L_INT_ENB_OFFSET);
 379
 380         tmp = readl_relaxed(reg_base + mevt->base + MCT_L_TCON_OFFSET);
 381         tmp |= MCT_L_TCON_INT_START | MCT_L_TCON_TIMER_START |
 382                MCT_L_TCON_INTERVAL_MODE;
 383         exynos4_mct_write(tmp, mevt->base + MCT_L_TCON_OFFSET);
 384 }
 385
 386 static void exynos4_mct_tick_clear(struct mct_clock_event_device *mevt)
 387 {
 388         /* Clear the MCT tick interrupt */
 389         if (readl_relaxed(reg_base + mevt->base + MCT_L_INT_CSTAT_OFFSET) & 1)
 390                 exynos4_mct_write(0x1, mevt->base + MCT_L_INT_CSTAT_OFFSET);
 391 }
 392
 393 static int exynos4_tick_set_next_event(unsigned long cycles,
 394                                        struct clock_event_device *evt)
 395 {
 396         struct mct_clock_event_device *mevt;
 397
 398         mevt = container_of(evt, struct mct_clock_event_device, evt);
 399         exynos4_mct_tick_start(cycles, mevt);
 400         return 0;
 401 }
 402
 403 static int set_state_shutdown(struct clock_event_device *evt)
 404 {
 405         struct mct_clock_event_device *mevt;
 406
 407         mevt = container_of(evt, struct mct_clock_event_device, evt);
 408         exynos4_mct_tick_stop(mevt);
 409         exynos4_mct_tick_clear(mevt);
 410         return 0;
 411 }
 412
 413 static int set_state_periodic(struct clock_event_device *evt)
 414 {
 415         struct mct_clock_event_device *mevt;
 416         unsigned long cycles_per_jiffy;
 417
 418         mevt = container_of(evt, struct mct_clock_event_device, evt);
 419         cycles_per_jiffy = (((unsigned long long)NSEC_PER_SEC / HZ * evt->mult)
 420                             >> evt->shift);
 421         exynos4_mct_tick_stop(mevt);
 422         exynos4_mct_tick_start(cycles_per_jiffy, mevt);
 423         return 0;
 424 }
 425
 426 static irqreturn_t exynos4_mct_tick_isr(int irq, void *dev_id)
 427 {
 428         struct mct_clock_event_device *mevt = dev_id;
 429         struct clock_event_device *evt = &mevt->evt;
 430
 431         /*
 432          * This is for supporting oneshot mode.
 433          * Mct would generate interrupt periodically
 434          * without explicit stopping.
 435          */
 436         if (!clockevent_state_periodic(&mevt->evt))
 437                 exynos4_mct_tick_stop(mevt);
 438
 439         exynos4_mct_tick_clear(mevt);
 440
 441         evt->event_handler(evt);
 442
 443         return IRQ_HANDLED;
 444 }
 445
 446 static int exynos4_mct_starting_cpu(unsigned int cpu)
 447 {
 448         struct mct_clock_event_device *mevt =
 449                 per_cpu_ptr(&percpu_mct_tick, cpu);
 450         struct clock_event_device *evt = &mevt->evt;
 451
 452         mevt->base = EXYNOS4_MCT_L_BASE(cpu);
 453         snprintf(mevt->name, sizeof(mevt->name), "mct_tick%d", cpu);
 454
 455         evt->name = mevt->name;
 456         evt->cpumask = cpumask_of(cpu);
 457         evt->set_next_event = exynos4_tick_set_next_event;
 458         evt->set_state_periodic = set_state_periodic;
 459         evt->set_state_shutdown = set_state_shutdown;
 460         evt->set_state_oneshot = set_state_shutdown;
 461         evt->set_state_oneshot_stopped = set_state_shutdown;
 462         evt->tick_resume = set_state_shutdown;
 463         evt->features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT |
 464                         CLOCK_EVT_FEAT_PERCPU;
 465         evt->rating = MCT_CLKEVENTS_RATING;
 466
 467         exynos4_mct_write(TICK_BASE_CNT, mevt->base + MCT_L_TCNTB_OFFSET);
 468
 469         if (mct_int_type == MCT_INT_SPI) {
 470
 471                 if (evt->irq == -1)
 472                         return -EIO;
 473
 474                 irq_force_affinity(evt->irq, cpumask_of(cpu));
 475                 enable_irq(evt->irq);
 476         } else {
 477                 enable_percpu_irq(mct_irqs[MCT_L0_IRQ], 0);
 478         }
 479         clockevents_config_and_register(evt, clk_rate / (TICK_BASE_CNT + 1),
 480                                         0xf, 0x7fffffff);
 481
 482         return 0;
 483 }
 484
 485 static int exynos4_mct_dying_cpu(unsigned int cpu)
 486 {
 487         struct mct_clock_event_device *mevt =
 488                 per_cpu_ptr(&percpu_mct_tick, cpu);
 489         struct clock_event_device *evt = &mevt->evt;
 490
 491         evt->set_state_shutdown(evt);
 492         if (mct_int_type == MCT_INT_SPI) {
 493                 if (evt->irq != -1)
 494                         disable_irq_nosync(evt->irq);
 495                 exynos4_mct_write(0x1, mevt->base + MCT_L_INT_CSTAT_OFFSET);
 496         } else {
 497                 disable_percpu_irq(mct_irqs[MCT_L0_IRQ]);
 498         }
 499         return 0;
 500 }
 501
 502 static int __init exynos4_timer_resources(struct device_node *np)
 503 {
 504         struct clk *mct_clk, *tick_clk;
 505
 506         reg_base = of_iomap(np, 0);
 507         if (!reg_base)
 508                 panic("%s: unable to ioremap mct address space\n", __func__);
 509
 510         tick_clk = of_clk_get_by_name(np, "fin_pll");
 511         if (IS_ERR(tick_clk))
 512                 panic("%s: unable to determine tick clock rate\n", __func__);
 513         clk_rate = clk_get_rate(tick_clk);
 514
 515         mct_clk = of_clk_get_by_name(np, "mct");
 516         if (IS_ERR(mct_clk))
 517                 panic("%s: unable to retrieve mct clock instance\n", __func__);
 518         clk_prepare_enable(mct_clk);
 519
 520         return 0;
 521 }
 522
 523 static int __init exynos4_timer_interrupts(struct device_node *np,
 524                                            unsigned int int_type)
 525 {
 526         int nr_irqs, i, err, cpu;
 527
 528         mct_int_type = int_type;
 529
 530         /* This driver uses only one global timer interrupt */
 531         mct_irqs[MCT_G0_IRQ] = irq_of_parse_and_map(np, MCT_G0_IRQ);
 532
 533         /*
 534          * Find out the number of local irqs specified. The local
 535          * timer irqs are specified after the four global timer
 536          * irqs are specified.
 537          */
 538         nr_irqs = of_irq_count(np);
 539         if (nr_irqs > ARRAY_SIZE(mct_irqs)) {
 540                 pr_err("exynos-mct: too many (%d) interrupts configured in DT\n",
 541                         nr_irqs);
 542                 nr_irqs = ARRAY_SIZE(mct_irqs);
 543         }
 544         for (i = MCT_L0_IRQ; i < nr_irqs; i++)
 545                 mct_irqs[i] = irq_of_parse_and_map(np, i);
 546
 547         if (mct_int_type == MCT_INT_PPI) {
 548
 549                 err = request_percpu_irq(mct_irqs[MCT_L0_IRQ],
 550                                          exynos4_mct_tick_isr, "MCT",
 551                                          &percpu_mct_tick);
 552                 WARN(err, "MCT: can't request IRQ %d (%d)\n",
 553                      mct_irqs[MCT_L0_IRQ], err);
 554         } else {
 555                 for_each_possible_cpu(cpu) {
 556                         int mct_irq;
 557                         struct mct_clock_event_device *pcpu_mevt =
 558                                 per_cpu_ptr(&percpu_mct_tick, cpu);
 559
 560                         pcpu_mevt->evt.irq = -1;
 561                         if (MCT_L0_IRQ + cpu >= ARRAY_SIZE(mct_irqs))
 562                                 break;
 563                         mct_irq = mct_irqs[MCT_L0_IRQ + cpu];
 564
 565                         irq_set_status_flags(mct_irq, IRQ_NOAUTOEN);
 566                         if (request_irq(mct_irq,
 567                                         exynos4_mct_tick_isr,
 568                                         IRQF_TIMER | IRQF_NOBALANCING,
 569                                         pcpu_mevt->name, pcpu_mevt)) {
 570                                 pr_err("exynos-mct: cannot register IRQ (cpu%d)\n",
 571                                                                         cpu);
 572
 573                                 continue;
 574                         }
 575                         pcpu_mevt->evt.irq = mct_irq;
 576                 }
 577         }
 578
 579         /* Install hotplug callbacks which configure the timer on this CPU */
 580         err = cpuhp_setup_state(CPUHP_AP_EXYNOS4_MCT_TIMER_STARTING,
 581                                 "clockevents/exynos4/mct_timer:starting",
 582                                 exynos4_mct_starting_cpu,
 583                                 exynos4_mct_dying_cpu);
 584         if (err)
 585                 goto out_irq;
 586
 587         return 0;
 588
 589 out_irq:
 590         if (mct_int_type == MCT_INT_PPI) {
 591                 free_percpu_irq(mct_irqs[MCT_L0_IRQ], &percpu_mct_tick);
 592         } else {
 593                 for_each_possible_cpu(cpu) {
 594                         struct mct_clock_event_device *pcpu_mevt =
 595                                 per_cpu_ptr(&percpu_mct_tick, cpu);
 596
 597                         if (pcpu_mevt->evt.irq != -1) {
 598                                 free_irq(pcpu_mevt->evt.irq, pcpu_mevt);
 599                                 pcpu_mevt->evt.irq = -1;
 600                         }
 601                 }
 602         }
 603         return err;
 604 }
 605
 606 static int __init mct_init_dt(struct device_node *np, unsigned int int_type)
 607 {
 608         int ret;
 609
 610         ret = exynos4_timer_resources(np);
 611         if (ret)
 612                 return ret;
 613
 614         ret = exynos4_timer_interrupts(np, int_type);
 615         if (ret)
 616                 return ret;
 617
 618         ret = exynos4_clocksource_init();
 619         if (ret)
 620                 return ret;
 621
 622         return exynos4_clockevent_init();
 623 }
 624
 625
 626 static int __init mct_init_spi(struct device_node *np)
 627 {
 628         return mct_init_dt(np, MCT_INT_SPI);
 629 }
 630
 631 static int __init mct_init_ppi(struct device_node *np)
 632 {
 633         return mct_init_dt(np, MCT_INT_PPI);
 634 }
 635 TIMER_OF_DECLARE(exynos4210, "samsung,exynos4210-mct", mct_init_spi);
 636 TIMER_OF_DECLARE(exynos4412, "samsung,exynos4412-mct", mct_init_ppi);