2 * linux/drivers/clocksource/arm_arch_timer.c
4 * Copyright (C) 2011 ARM Ltd.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
12 #define pr_fmt(fmt) "arm_arch_timer: " fmt
14 #include <linux/init.h>
15 #include <linux/kernel.h>
16 #include <linux/device.h>
17 #include <linux/smp.h>
18 #include <linux/cpu.h>
19 #include <linux/cpu_pm.h>
20 #include <linux/clockchips.h>
21 #include <linux/clocksource.h>
22 #include <linux/interrupt.h>
23 #include <linux/of_irq.h>
24 #include <linux/of_address.h>
26 #include <linux/slab.h>
27 #include <linux/sched/clock.h>
28 #include <linux/sched_clock.h>
29 #include <linux/acpi.h>
31 #include <asm/arch_timer.h>
34 #include <clocksource/arm_arch_timer.h>
37 #define pr_fmt(fmt) "arch_timer: " fmt
40 #define CNTTIDR_VIRT(n) (BIT(1) << ((n) * 4))
42 #define CNTACR(n) (0x40 + ((n) * 4))
43 #define CNTACR_RPCT BIT(0)
44 #define CNTACR_RVCT BIT(1)
45 #define CNTACR_RFRQ BIT(2)
46 #define CNTACR_RVOFF BIT(3)
47 #define CNTACR_RWVT BIT(4)
48 #define CNTACR_RWPT BIT(5)
50 #define CNTVCT_LO 0x08
51 #define CNTVCT_HI 0x0c
53 #define CNTP_TVAL 0x28
55 #define CNTV_TVAL 0x38
58 static unsigned arch_timers_present __initdata;
60 static void __iomem *arch_counter_base;
64 struct clock_event_device evt;
67 #define to_arch_timer(e) container_of(e, struct arch_timer, evt)
69 static u32 arch_timer_rate;
70 static int arch_timer_ppi[ARCH_TIMER_MAX_TIMER_PPI];
72 static struct clock_event_device __percpu *arch_timer_evt;
74 static enum arch_timer_ppi_nr arch_timer_uses_ppi = ARCH_TIMER_VIRT_PPI;
75 static bool arch_timer_c3stop;
76 static bool arch_timer_mem_use_virtual;
77 static bool arch_counter_suspend_stop;
78 static bool vdso_default = true;
80 static bool evtstrm_enable = IS_ENABLED(CONFIG_ARM_ARCH_TIMER_EVTSTREAM);
81 static bool mct_enable = IS_ENABLED(CONFIG_CLKSRC_EXYNOS_MCT);
83 static int __init early_evtstrm_cfg(char *buf)
85 return strtobool(buf, &evtstrm_enable);
87 early_param("clocksource.arm_arch_timer.evtstrm", early_evtstrm_cfg);
90 * Architected system timer support.
93 static __always_inline
94 void arch_timer_reg_write(int access, enum arch_timer_reg reg, u32 val,
95 struct clock_event_device *clk)
97 if (access == ARCH_TIMER_MEM_PHYS_ACCESS) {
98 struct arch_timer *timer = to_arch_timer(clk);
100 case ARCH_TIMER_REG_CTRL:
101 writel_relaxed(val, timer->base + CNTP_CTL);
103 case ARCH_TIMER_REG_TVAL:
104 writel_relaxed(val, timer->base + CNTP_TVAL);
107 } else if (access == ARCH_TIMER_MEM_VIRT_ACCESS) {
108 struct arch_timer *timer = to_arch_timer(clk);
110 case ARCH_TIMER_REG_CTRL:
111 writel_relaxed(val, timer->base + CNTV_CTL);
113 case ARCH_TIMER_REG_TVAL:
114 writel_relaxed(val, timer->base + CNTV_TVAL);
118 arch_timer_reg_write_cp15(access, reg, val);
122 static __always_inline
123 u32 arch_timer_reg_read(int access, enum arch_timer_reg reg,
124 struct clock_event_device *clk)
128 if (access == ARCH_TIMER_MEM_PHYS_ACCESS) {
129 struct arch_timer *timer = to_arch_timer(clk);
131 case ARCH_TIMER_REG_CTRL:
132 val = readl_relaxed(timer->base + CNTP_CTL);
134 case ARCH_TIMER_REG_TVAL:
135 val = readl_relaxed(timer->base + CNTP_TVAL);
138 } else if (access == ARCH_TIMER_MEM_VIRT_ACCESS) {
139 struct arch_timer *timer = to_arch_timer(clk);
141 case ARCH_TIMER_REG_CTRL:
142 val = readl_relaxed(timer->base + CNTV_CTL);
144 case ARCH_TIMER_REG_TVAL:
145 val = readl_relaxed(timer->base + CNTV_TVAL);
149 val = arch_timer_reg_read_cp15(access, reg);
156 * Default to cp15 based access because arm64 uses this function for
157 * sched_clock() before DT is probed and the cp15 method is guaranteed
158 * to exist on arm64. arm doesn't use this before DT is probed so even
159 * if we don't have the cp15 accessors we won't have a problem.
161 u64 (*arch_timer_read_counter)(void) = arch_counter_get_cntvct;
163 static u64 arch_counter_read(struct clocksource *cs)
165 return arch_timer_read_counter();
168 static u64 arch_counter_read_cc(const struct cyclecounter *cc)
170 return arch_timer_read_counter();
173 static struct clocksource clocksource_counter = {
174 .name = "arch_sys_counter",
176 .read = arch_counter_read,
177 .mask = CLOCKSOURCE_MASK(56),
178 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
181 static struct cyclecounter cyclecounter __ro_after_init = {
182 .read = arch_counter_read_cc,
183 .mask = CLOCKSOURCE_MASK(56),
186 struct ate_acpi_oem_info {
187 char oem_id[ACPI_OEM_ID_SIZE + 1];
188 char oem_table_id[ACPI_OEM_TABLE_ID_SIZE + 1];
192 #ifdef CONFIG_FSL_ERRATUM_A008585
194 * The number of retries is an arbitrary value well beyond the highest number
195 * of iterations the loop has been observed to take.
197 #define __fsl_a008585_read_reg(reg) ({ \
199 int _retries = 200; \
202 _old = read_sysreg(reg); \
203 _new = read_sysreg(reg); \
205 } while (unlikely(_old != _new) && _retries); \
207 WARN_ON_ONCE(!_retries); \
211 static u32 notrace fsl_a008585_read_cntp_tval_el0(void)
213 return __fsl_a008585_read_reg(cntp_tval_el0);
216 static u32 notrace fsl_a008585_read_cntv_tval_el0(void)
218 return __fsl_a008585_read_reg(cntv_tval_el0);
221 static u64 notrace fsl_a008585_read_cntvct_el0(void)
223 return __fsl_a008585_read_reg(cntvct_el0);
227 #ifdef CONFIG_HISILICON_ERRATUM_161010101
229 * Verify whether the value of the second read is larger than the first by
230 * less than 32 is the only way to confirm the value is correct, so clear the
231 * lower 5 bits to check whether the difference is greater than 32 or not.
232 * Theoretically the erratum should not occur more than twice in succession
233 * when reading the system counter, but it is possible that some interrupts
234 * may lead to more than twice read errors, triggering the warning, so setting
235 * the number of retries far beyond the number of iterations the loop has been
238 #define __hisi_161010101_read_reg(reg) ({ \
243 _old = read_sysreg(reg); \
244 _new = read_sysreg(reg); \
246 } while (unlikely((_new - _old) >> 5) && _retries); \
248 WARN_ON_ONCE(!_retries); \
252 static u32 notrace hisi_161010101_read_cntp_tval_el0(void)
254 return __hisi_161010101_read_reg(cntp_tval_el0);
257 static u32 notrace hisi_161010101_read_cntv_tval_el0(void)
259 return __hisi_161010101_read_reg(cntv_tval_el0);
262 static u64 notrace hisi_161010101_read_cntvct_el0(void)
264 return __hisi_161010101_read_reg(cntvct_el0);
267 static struct ate_acpi_oem_info hisi_161010101_oem_info[] = {
269 * Note that trailing spaces are required to properly match
270 * the OEM table information.
274 .oem_table_id = "HIP05 ",
279 .oem_table_id = "HIP06 ",
284 .oem_table_id = "HIP07 ",
287 { /* Sentinel indicating the end of the OEM array */ },
291 #ifdef CONFIG_ARM64_ERRATUM_858921
292 static u64 notrace arm64_858921_read_cntvct_el0(void)
296 old = read_sysreg(cntvct_el0);
297 new = read_sysreg(cntvct_el0);
298 return (((old ^ new) >> 32) & 1) ? old : new;
302 #ifdef CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND
303 DEFINE_PER_CPU(const struct arch_timer_erratum_workaround *, timer_unstable_counter_workaround);
304 EXPORT_SYMBOL_GPL(timer_unstable_counter_workaround);
306 DEFINE_STATIC_KEY_FALSE(arch_timer_read_ool_enabled);
307 EXPORT_SYMBOL_GPL(arch_timer_read_ool_enabled);
309 static void erratum_set_next_event_tval_generic(const int access, unsigned long evt,
310 struct clock_event_device *clk)
313 u64 cval = evt + arch_counter_get_cntvct();
315 ctrl = arch_timer_reg_read(access, ARCH_TIMER_REG_CTRL, clk);
316 ctrl |= ARCH_TIMER_CTRL_ENABLE;
317 ctrl &= ~ARCH_TIMER_CTRL_IT_MASK;
319 if (access == ARCH_TIMER_PHYS_ACCESS)
320 write_sysreg(cval, cntp_cval_el0);
322 write_sysreg(cval, cntv_cval_el0);
324 arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl, clk);
327 static __maybe_unused int erratum_set_next_event_tval_virt(unsigned long evt,
328 struct clock_event_device *clk)
330 erratum_set_next_event_tval_generic(ARCH_TIMER_VIRT_ACCESS, evt, clk);
334 static __maybe_unused int erratum_set_next_event_tval_phys(unsigned long evt,
335 struct clock_event_device *clk)
337 erratum_set_next_event_tval_generic(ARCH_TIMER_PHYS_ACCESS, evt, clk);
341 static const struct arch_timer_erratum_workaround ool_workarounds[] = {
342 #ifdef CONFIG_FSL_ERRATUM_A008585
344 .match_type = ate_match_dt,
345 .id = "fsl,erratum-a008585",
346 .desc = "Freescale erratum a005858",
347 .read_cntp_tval_el0 = fsl_a008585_read_cntp_tval_el0,
348 .read_cntv_tval_el0 = fsl_a008585_read_cntv_tval_el0,
349 .read_cntvct_el0 = fsl_a008585_read_cntvct_el0,
350 .set_next_event_phys = erratum_set_next_event_tval_phys,
351 .set_next_event_virt = erratum_set_next_event_tval_virt,
354 #ifdef CONFIG_HISILICON_ERRATUM_161010101
356 .match_type = ate_match_dt,
357 .id = "hisilicon,erratum-161010101",
358 .desc = "HiSilicon erratum 161010101",
359 .read_cntp_tval_el0 = hisi_161010101_read_cntp_tval_el0,
360 .read_cntv_tval_el0 = hisi_161010101_read_cntv_tval_el0,
361 .read_cntvct_el0 = hisi_161010101_read_cntvct_el0,
362 .set_next_event_phys = erratum_set_next_event_tval_phys,
363 .set_next_event_virt = erratum_set_next_event_tval_virt,
366 .match_type = ate_match_acpi_oem_info,
367 .id = hisi_161010101_oem_info,
368 .desc = "HiSilicon erratum 161010101",
369 .read_cntp_tval_el0 = hisi_161010101_read_cntp_tval_el0,
370 .read_cntv_tval_el0 = hisi_161010101_read_cntv_tval_el0,
371 .read_cntvct_el0 = hisi_161010101_read_cntvct_el0,
372 .set_next_event_phys = erratum_set_next_event_tval_phys,
373 .set_next_event_virt = erratum_set_next_event_tval_virt,
376 #ifdef CONFIG_ARM64_ERRATUM_858921
378 .match_type = ate_match_local_cap_id,
379 .id = (void *)ARM64_WORKAROUND_858921,
380 .desc = "ARM erratum 858921",
381 .read_cntvct_el0 = arm64_858921_read_cntvct_el0,
386 typedef bool (*ate_match_fn_t)(const struct arch_timer_erratum_workaround *,
390 bool arch_timer_check_dt_erratum(const struct arch_timer_erratum_workaround *wa,
393 const struct device_node *np = arg;
395 return of_property_read_bool(np, wa->id);
399 bool arch_timer_check_local_cap_erratum(const struct arch_timer_erratum_workaround *wa,
402 return this_cpu_has_cap((uintptr_t)wa->id);
407 bool arch_timer_check_acpi_oem_erratum(const struct arch_timer_erratum_workaround *wa,
410 static const struct ate_acpi_oem_info empty_oem_info = {};
411 const struct ate_acpi_oem_info *info = wa->id;
412 const struct acpi_table_header *table = arg;
414 /* Iterate over the ACPI OEM info array, looking for a match */
415 while (memcmp(info, &empty_oem_info, sizeof(*info))) {
416 if (!memcmp(info->oem_id, table->oem_id, ACPI_OEM_ID_SIZE) &&
417 !memcmp(info->oem_table_id, table->oem_table_id, ACPI_OEM_TABLE_ID_SIZE) &&
418 info->oem_revision == table->oem_revision)
427 static const struct arch_timer_erratum_workaround *
428 arch_timer_iterate_errata(enum arch_timer_erratum_match_type type,
429 ate_match_fn_t match_fn,
434 for (i = 0; i < ARRAY_SIZE(ool_workarounds); i++) {
435 if (ool_workarounds[i].match_type != type)
438 if (match_fn(&ool_workarounds[i], arg))
439 return &ool_workarounds[i];
446 void arch_timer_enable_workaround(const struct arch_timer_erratum_workaround *wa,
452 __this_cpu_write(timer_unstable_counter_workaround, wa);
454 for_each_possible_cpu(i)
455 per_cpu(timer_unstable_counter_workaround, i) = wa;
459 * Use the locked version, as we're called from the CPU
460 * hotplug framework. Otherwise, we end-up in deadlock-land.
462 static_branch_enable_cpuslocked(&arch_timer_read_ool_enabled);
465 * Don't use the vdso fastpath if errata require using the
466 * out-of-line counter accessor. We may change our mind pretty
467 * late in the game (with a per-CPU erratum, for example), so
468 * change both the default value and the vdso itself.
470 if (wa->read_cntvct_el0) {
471 clocksource_counter.archdata.vdso_direct = false;
472 vdso_default = false;
476 static void arch_timer_check_ool_workaround(enum arch_timer_erratum_match_type type,
479 const struct arch_timer_erratum_workaround *wa;
480 ate_match_fn_t match_fn = NULL;
485 match_fn = arch_timer_check_dt_erratum;
487 case ate_match_local_cap_id:
488 match_fn = arch_timer_check_local_cap_erratum;
491 case ate_match_acpi_oem_info:
492 match_fn = arch_timer_check_acpi_oem_erratum;
499 wa = arch_timer_iterate_errata(type, match_fn, arg);
503 if (needs_unstable_timer_counter_workaround()) {
504 const struct arch_timer_erratum_workaround *__wa;
505 __wa = __this_cpu_read(timer_unstable_counter_workaround);
506 if (__wa && wa != __wa)
507 pr_warn("Can't enable workaround for %s (clashes with %s\n)",
508 wa->desc, __wa->desc);
514 arch_timer_enable_workaround(wa, local);
515 pr_info("Enabling %s workaround for %s\n",
516 local ? "local" : "global", wa->desc);
519 #define erratum_handler(fn, r, ...) \
522 if (needs_unstable_timer_counter_workaround()) { \
523 const struct arch_timer_erratum_workaround *__wa; \
524 __wa = __this_cpu_read(timer_unstable_counter_workaround); \
525 if (__wa && __wa->fn) { \
526 r = __wa->fn(__VA_ARGS__); \
537 static bool arch_timer_this_cpu_has_cntvct_wa(void)
539 const struct arch_timer_erratum_workaround *wa;
541 wa = __this_cpu_read(timer_unstable_counter_workaround);
542 return wa && wa->read_cntvct_el0;
545 #define arch_timer_check_ool_workaround(t,a) do { } while(0)
546 #define erratum_set_next_event_tval_virt(...) ({BUG(); 0;})
547 #define erratum_set_next_event_tval_phys(...) ({BUG(); 0;})
548 #define erratum_handler(fn, r, ...) ({false;})
549 #define arch_timer_this_cpu_has_cntvct_wa() ({false;})
550 #endif /* CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND */
552 static __always_inline irqreturn_t timer_handler(const int access,
553 struct clock_event_device *evt)
557 ctrl = arch_timer_reg_read(access, ARCH_TIMER_REG_CTRL, evt);
558 if (ctrl & ARCH_TIMER_CTRL_IT_STAT) {
559 ctrl |= ARCH_TIMER_CTRL_IT_MASK;
560 arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl, evt);
561 evt->event_handler(evt);
568 static irqreturn_t arch_timer_handler_virt(int irq, void *dev_id)
570 struct clock_event_device *evt = dev_id;
572 return timer_handler(ARCH_TIMER_VIRT_ACCESS, evt);
575 static irqreturn_t arch_timer_handler_phys(int irq, void *dev_id)
577 struct clock_event_device *evt = dev_id;
579 return timer_handler(ARCH_TIMER_PHYS_ACCESS, evt);
582 static irqreturn_t arch_timer_handler_phys_mem(int irq, void *dev_id)
584 struct clock_event_device *evt = dev_id;
586 return timer_handler(ARCH_TIMER_MEM_PHYS_ACCESS, evt);
589 static irqreturn_t arch_timer_handler_virt_mem(int irq, void *dev_id)
591 struct clock_event_device *evt = dev_id;
593 return timer_handler(ARCH_TIMER_MEM_VIRT_ACCESS, evt);
596 static __always_inline int timer_shutdown(const int access,
597 struct clock_event_device *clk)
601 ctrl = arch_timer_reg_read(access, ARCH_TIMER_REG_CTRL, clk);
602 ctrl &= ~ARCH_TIMER_CTRL_ENABLE;
603 arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl, clk);
608 static int arch_timer_shutdown_virt(struct clock_event_device *clk)
610 return timer_shutdown(ARCH_TIMER_VIRT_ACCESS, clk);
613 static int arch_timer_shutdown_phys(struct clock_event_device *clk)
615 return timer_shutdown(ARCH_TIMER_PHYS_ACCESS, clk);
618 static int arch_timer_shutdown_virt_mem(struct clock_event_device *clk)
620 return timer_shutdown(ARCH_TIMER_MEM_VIRT_ACCESS, clk);
623 static int arch_timer_shutdown_phys_mem(struct clock_event_device *clk)
625 return timer_shutdown(ARCH_TIMER_MEM_PHYS_ACCESS, clk);
628 static __always_inline void set_next_event(const int access, unsigned long evt,
629 struct clock_event_device *clk)
632 ctrl = arch_timer_reg_read(access, ARCH_TIMER_REG_CTRL, clk);
633 ctrl |= ARCH_TIMER_CTRL_ENABLE;
634 ctrl &= ~ARCH_TIMER_CTRL_IT_MASK;
635 arch_timer_reg_write(access, ARCH_TIMER_REG_TVAL, evt, clk);
636 arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl, clk);
639 static int arch_timer_set_next_event_virt(unsigned long evt,
640 struct clock_event_device *clk)
644 if (erratum_handler(set_next_event_virt, ret, evt, clk))
647 set_next_event(ARCH_TIMER_VIRT_ACCESS, evt, clk);
651 static int arch_timer_set_next_event_phys(unsigned long evt,
652 struct clock_event_device *clk)
656 if (erratum_handler(set_next_event_phys, ret, evt, clk))
659 set_next_event(ARCH_TIMER_PHYS_ACCESS, evt, clk);
663 static int arch_timer_set_next_event_virt_mem(unsigned long evt,
664 struct clock_event_device *clk)
666 set_next_event(ARCH_TIMER_MEM_VIRT_ACCESS, evt, clk);
670 static int arch_timer_set_next_event_phys_mem(unsigned long evt,
671 struct clock_event_device *clk)
673 set_next_event(ARCH_TIMER_MEM_PHYS_ACCESS, evt, clk);
677 static void __arch_timer_setup(unsigned type,
678 struct clock_event_device *clk)
680 clk->features = CLOCK_EVT_FEAT_ONESHOT;
682 if (type == ARCH_TIMER_TYPE_CP15) {
683 if (arch_timer_c3stop)
684 clk->features |= CLOCK_EVT_FEAT_C3STOP;
685 clk->name = "arch_sys_timer";
687 clk->cpumask = cpumask_of(smp_processor_id());
688 clk->irq = arch_timer_ppi[arch_timer_uses_ppi];
689 switch (arch_timer_uses_ppi) {
690 case ARCH_TIMER_VIRT_PPI:
691 clk->set_state_shutdown = arch_timer_shutdown_virt;
692 clk->set_state_oneshot_stopped = arch_timer_shutdown_virt;
693 clk->set_next_event = arch_timer_set_next_event_virt;
695 case ARCH_TIMER_PHYS_SECURE_PPI:
696 case ARCH_TIMER_PHYS_NONSECURE_PPI:
697 case ARCH_TIMER_HYP_PPI:
698 clk->set_state_shutdown = arch_timer_shutdown_phys;
699 clk->set_state_oneshot_stopped = arch_timer_shutdown_phys;
700 clk->set_next_event = arch_timer_set_next_event_phys;
706 arch_timer_check_ool_workaround(ate_match_local_cap_id, NULL);
708 clk->features |= CLOCK_EVT_FEAT_DYNIRQ;
709 clk->name = "arch_mem_timer";
711 clk->cpumask = cpu_all_mask;
712 if (arch_timer_mem_use_virtual) {
713 clk->set_state_shutdown = arch_timer_shutdown_virt_mem;
714 clk->set_state_oneshot_stopped = arch_timer_shutdown_virt_mem;
715 clk->set_next_event =
716 arch_timer_set_next_event_virt_mem;
718 clk->set_state_shutdown = arch_timer_shutdown_phys_mem;
719 clk->set_state_oneshot_stopped = arch_timer_shutdown_phys_mem;
720 clk->set_next_event =
721 arch_timer_set_next_event_phys_mem;
725 clk->set_state_shutdown(clk);
727 clockevents_config_and_register(clk, arch_timer_rate, 0xf, 0x7fffffff);
730 static void arch_timer_evtstrm_enable(int divider)
732 u32 cntkctl = arch_timer_get_cntkctl();
734 cntkctl &= ~ARCH_TIMER_EVT_TRIGGER_MASK;
735 /* Set the divider and enable virtual event stream */
736 cntkctl |= (divider << ARCH_TIMER_EVT_TRIGGER_SHIFT)
737 | ARCH_TIMER_VIRT_EVT_EN;
738 arch_timer_set_cntkctl(cntkctl);
739 elf_hwcap |= HWCAP_EVTSTRM;
741 compat_elf_hwcap |= COMPAT_HWCAP_EVTSTRM;
745 static void arch_timer_configure_evtstream(void)
747 int evt_stream_div, pos;
749 /* Find the closest power of two to the divisor */
750 evt_stream_div = arch_timer_rate / ARCH_TIMER_EVT_STREAM_FREQ;
751 pos = fls(evt_stream_div);
752 if (pos > 1 && !(evt_stream_div & (1 << (pos - 2))))
754 /* enable event stream */
755 arch_timer_evtstrm_enable(min(pos, 15));
758 static void arch_counter_set_user_access(void)
760 u32 cntkctl = arch_timer_get_cntkctl();
762 /* Disable user access to the timers and both counters */
763 /* Also disable virtual event stream */
764 cntkctl &= ~(ARCH_TIMER_USR_PT_ACCESS_EN
765 | ARCH_TIMER_USR_VT_ACCESS_EN
766 | ARCH_TIMER_USR_VCT_ACCESS_EN
767 | ARCH_TIMER_VIRT_EVT_EN
768 | ARCH_TIMER_USR_PCT_ACCESS_EN);
771 * Enable user access to the virtual counter if it doesn't
772 * need to be workaround. The vdso may have been already
775 if (arch_timer_this_cpu_has_cntvct_wa())
776 pr_info("CPU%d: Trapping CNTVCT access\n", smp_processor_id());
778 cntkctl |= ARCH_TIMER_USR_VCT_ACCESS_EN;
780 arch_timer_set_cntkctl(cntkctl);
783 static bool arch_timer_has_nonsecure_ppi(void)
785 return (arch_timer_uses_ppi == ARCH_TIMER_PHYS_SECURE_PPI &&
786 arch_timer_ppi[ARCH_TIMER_PHYS_NONSECURE_PPI]);
789 static u32 check_ppi_trigger(int irq)
791 u32 flags = irq_get_trigger_type(irq);
793 if (flags != IRQF_TRIGGER_HIGH && flags != IRQF_TRIGGER_LOW) {
794 pr_warn("WARNING: Invalid trigger for IRQ%d, assuming level low\n", irq);
795 pr_warn("WARNING: Please fix your firmware\n");
796 flags = IRQF_TRIGGER_LOW;
802 static int arch_timer_starting_cpu(unsigned int cpu)
804 struct clock_event_device *clk = this_cpu_ptr(arch_timer_evt);
807 __arch_timer_setup(ARCH_TIMER_TYPE_CP15, clk);
809 flags = check_ppi_trigger(arch_timer_ppi[arch_timer_uses_ppi]);
810 enable_percpu_irq(arch_timer_ppi[arch_timer_uses_ppi], flags);
812 if (arch_timer_has_nonsecure_ppi()) {
813 flags = check_ppi_trigger(arch_timer_ppi[ARCH_TIMER_PHYS_NONSECURE_PPI]);
814 enable_percpu_irq(arch_timer_ppi[ARCH_TIMER_PHYS_NONSECURE_PPI],
818 arch_counter_set_user_access();
820 arch_timer_configure_evtstream();
826 * For historical reasons, when probing with DT we use whichever (non-zero)
827 * rate was probed first, and don't verify that others match. If the first node
828 * probed has a clock-frequency property, this overrides the HW register.
830 static void arch_timer_of_configure_rate(u32 rate, struct device_node *np)
832 /* Who has more than one independent system counter? */
836 if (of_property_read_u32(np, "clock-frequency", &arch_timer_rate))
837 arch_timer_rate = rate;
839 /* Check the timer frequency. */
840 if (arch_timer_rate == 0)
841 pr_warn("frequency not available\n");
844 static void arch_timer_banner(unsigned type)
846 pr_info("%s%s%s timer(s) running at %lu.%02luMHz (%s%s%s).\n",
847 type & ARCH_TIMER_TYPE_CP15 ? "cp15" : "",
848 type == (ARCH_TIMER_TYPE_CP15 | ARCH_TIMER_TYPE_MEM) ?
850 type & ARCH_TIMER_TYPE_MEM ? "mmio" : "",
851 (unsigned long)arch_timer_rate / 1000000,
852 (unsigned long)(arch_timer_rate / 10000) % 100,
853 type & ARCH_TIMER_TYPE_CP15 ?
854 (arch_timer_uses_ppi == ARCH_TIMER_VIRT_PPI) ? "virt" : "phys" :
856 type == (ARCH_TIMER_TYPE_CP15 | ARCH_TIMER_TYPE_MEM) ? "/" : "",
857 type & ARCH_TIMER_TYPE_MEM ?
858 arch_timer_mem_use_virtual ? "virt" : "phys" :
862 u32 arch_timer_get_rate(void)
864 return arch_timer_rate;
867 static u64 arch_counter_get_cntvct_mem(void)
869 u32 vct_lo, vct_hi, tmp_hi;
872 vct_hi = readl_relaxed(arch_counter_base + CNTVCT_HI);
873 vct_lo = readl_relaxed(arch_counter_base + CNTVCT_LO);
874 tmp_hi = readl_relaxed(arch_counter_base + CNTVCT_HI);
875 } while (vct_hi != tmp_hi);
877 return ((u64) vct_hi << 32) | vct_lo;
880 static struct arch_timer_kvm_info arch_timer_kvm_info;
882 struct arch_timer_kvm_info *arch_timer_get_kvm_info(void)
884 return &arch_timer_kvm_info;
887 static void __init arch_counter_register(unsigned type)
891 /* Register the CP15 based counter if we have one */
892 if (type & ARCH_TIMER_TYPE_CP15) {
893 if (IS_ENABLED(CONFIG_ARM64) ||
894 arch_timer_uses_ppi == ARCH_TIMER_VIRT_PPI)
895 arch_timer_read_counter = arch_counter_get_cntpct;
897 arch_timer_read_counter = arch_counter_get_cntpct;
899 clocksource_counter.archdata.vdso_direct = vdso_default;
901 arch_timer_read_counter = arch_counter_get_cntvct_mem;
904 if (!arch_counter_suspend_stop)
905 clocksource_counter.flags |= CLOCK_SOURCE_SUSPEND_NONSTOP;
906 start_count = arch_timer_read_counter();
907 clocksource_register_hz(&clocksource_counter, arch_timer_rate);
908 cyclecounter.mult = clocksource_counter.mult;
909 cyclecounter.shift = clocksource_counter.shift;
910 timecounter_init(&arch_timer_kvm_info.timecounter,
911 &cyclecounter, start_count);
913 /* 56 bits minimum, so we assume worst case rollover */
914 sched_clock_register(arch_timer_read_counter, 56, arch_timer_rate);
917 static void arch_timer_stop(struct clock_event_device *clk)
919 pr_debug("disable IRQ%d cpu #%d\n", clk->irq, smp_processor_id());
921 disable_percpu_irq(arch_timer_ppi[arch_timer_uses_ppi]);
922 if (arch_timer_has_nonsecure_ppi())
923 disable_percpu_irq(arch_timer_ppi[ARCH_TIMER_PHYS_NONSECURE_PPI]);
925 clk->set_state_shutdown(clk);
928 static int arch_timer_dying_cpu(unsigned int cpu)
930 struct clock_event_device *clk = this_cpu_ptr(arch_timer_evt);
932 arch_timer_stop(clk);
937 static DEFINE_PER_CPU(unsigned long, saved_cntkctl);
938 static int arch_timer_cpu_pm_notify(struct notifier_block *self,
939 unsigned long action, void *hcpu)
941 if (action == CPU_PM_ENTER)
942 __this_cpu_write(saved_cntkctl, arch_timer_get_cntkctl());
943 else if (action == CPU_PM_ENTER_FAILED || action == CPU_PM_EXIT)
944 arch_timer_set_cntkctl(__this_cpu_read(saved_cntkctl));
948 static struct notifier_block arch_timer_cpu_pm_notifier = {
949 .notifier_call = arch_timer_cpu_pm_notify,
952 static int __init arch_timer_cpu_pm_init(void)
954 return cpu_pm_register_notifier(&arch_timer_cpu_pm_notifier);
957 static void __init arch_timer_cpu_pm_deinit(void)
959 WARN_ON(cpu_pm_unregister_notifier(&arch_timer_cpu_pm_notifier));
963 static int __init arch_timer_cpu_pm_init(void)
968 static void __init arch_timer_cpu_pm_deinit(void)
973 static int __init arch_timer_register(void)
978 arch_timer_evt = alloc_percpu(struct clock_event_device);
979 if (!arch_timer_evt) {
984 ppi = arch_timer_ppi[arch_timer_uses_ppi];
985 switch (arch_timer_uses_ppi) {
986 case ARCH_TIMER_VIRT_PPI:
987 err = request_percpu_irq(ppi, arch_timer_handler_virt,
988 "arch_timer", arch_timer_evt);
990 case ARCH_TIMER_PHYS_SECURE_PPI:
991 case ARCH_TIMER_PHYS_NONSECURE_PPI:
992 err = request_percpu_irq(ppi, arch_timer_handler_phys,
993 "arch_timer", arch_timer_evt);
994 if (!err && arch_timer_has_nonsecure_ppi()) {
995 ppi = arch_timer_ppi[ARCH_TIMER_PHYS_NONSECURE_PPI];
996 err = request_percpu_irq(ppi, arch_timer_handler_phys,
997 "arch_timer", arch_timer_evt);
999 free_percpu_irq(arch_timer_ppi[ARCH_TIMER_PHYS_SECURE_PPI],
1003 case ARCH_TIMER_HYP_PPI:
1004 err = request_percpu_irq(ppi, arch_timer_handler_phys,
1005 "arch_timer", arch_timer_evt);
1012 pr_err("can't register interrupt %d (%d)\n", ppi, err);
1016 err = arch_timer_cpu_pm_init();
1018 goto out_unreg_notify;
1023 * FIXME: The arm64 architecture enables the arm_arch_timer always
1024 * even if arm_arch_timer is not stable. When Exynos5433 uses the
1025 * arm_arch_timer, it fails to enable/disble the secondary cpu.
1026 * To fix the hotplug issue of secondary cpu, if Exynos's MCT timer
1027 * is enabled, arm_arch_timer doesn't register the clockevent
1032 /* Register and immediately configure the timer on the boot CPU */
1033 err = cpuhp_setup_state(CPUHP_AP_ARM_ARCH_TIMER_STARTING,
1034 "clockevents/arm/arch_timer:starting",
1035 arch_timer_starting_cpu, arch_timer_dying_cpu);
1037 goto out_unreg_cpupm;
1043 arch_timer_cpu_pm_deinit();
1046 free_percpu_irq(arch_timer_ppi[arch_timer_uses_ppi], arch_timer_evt);
1047 if (arch_timer_has_nonsecure_ppi())
1048 free_percpu_irq(arch_timer_ppi[ARCH_TIMER_PHYS_NONSECURE_PPI],
1052 free_percpu(arch_timer_evt);
1057 static int __init arch_timer_mem_register(void __iomem *base, unsigned int irq)
1061 struct arch_timer *t;
1063 t = kzalloc(sizeof(*t), GFP_KERNEL);
1069 __arch_timer_setup(ARCH_TIMER_TYPE_MEM, &t->evt);
1071 if (arch_timer_mem_use_virtual)
1072 func = arch_timer_handler_virt_mem;
1074 func = arch_timer_handler_phys_mem;
1076 ret = request_irq(irq, func, IRQF_TIMER, "arch_mem_timer", &t->evt);
1078 pr_err("Failed to request mem timer irq\n");
1085 static const struct of_device_id arch_timer_of_match[] __initconst = {
1086 { .compatible = "arm,armv7-timer", },
1087 { .compatible = "arm,armv8-timer", },
1091 static const struct of_device_id arch_timer_mem_of_match[] __initconst = {
1092 { .compatible = "arm,armv7-timer-mem", },
1096 static bool __init arch_timer_needs_of_probing(void)
1098 struct device_node *dn;
1099 bool needs_probing = false;
1100 unsigned int mask = ARCH_TIMER_TYPE_CP15 | ARCH_TIMER_TYPE_MEM;
1102 /* We have two timers, and both device-tree nodes are probed. */
1103 if ((arch_timers_present & mask) == mask)
1107 * Only one type of timer is probed,
1108 * check if we have another type of timer node in device-tree.
1110 if (arch_timers_present & ARCH_TIMER_TYPE_CP15)
1111 dn = of_find_matching_node(NULL, arch_timer_mem_of_match);
1113 dn = of_find_matching_node(NULL, arch_timer_of_match);
1115 if (dn && of_device_is_available(dn))
1116 needs_probing = true;
1120 return needs_probing;
1123 static int __init arch_timer_common_init(void)
1125 arch_timer_banner(arch_timers_present);
1126 arch_counter_register(arch_timers_present);
1127 return arch_timer_arch_init();
1131 * arch_timer_select_ppi() - Select suitable PPI for the current system.
1133 * If HYP mode is available, we know that the physical timer
1134 * has been configured to be accessible from PL1. Use it, so
1135 * that a guest can use the virtual timer instead.
1137 * On ARMv8.1 with VH extensions, the kernel runs in HYP. VHE
1138 * accesses to CNTP_*_EL1 registers are silently redirected to
1139 * their CNTHP_*_EL2 counterparts, and use a different PPI
1142 * If no interrupt provided for virtual timer, we'll have to
1143 * stick to the physical timer. It'd better be accessible...
1144 * For arm64 we never use the secure interrupt.
1146 * Return: a suitable PPI type for the current system.
1148 static enum arch_timer_ppi_nr __init arch_timer_select_ppi(void)
1150 if (is_kernel_in_hyp_mode())
1151 return ARCH_TIMER_HYP_PPI;
1153 if (!is_hyp_mode_available() && arch_timer_ppi[ARCH_TIMER_VIRT_PPI])
1154 return ARCH_TIMER_VIRT_PPI;
1156 if (IS_ENABLED(CONFIG_ARM64))
1157 return ARCH_TIMER_PHYS_NONSECURE_PPI;
1159 return ARCH_TIMER_PHYS_SECURE_PPI;
1162 static int __init arch_timer_of_init(struct device_node *np)
1167 if (arch_timers_present & ARCH_TIMER_TYPE_CP15) {
1168 pr_warn("multiple nodes in dt, skipping\n");
1172 arch_timers_present |= ARCH_TIMER_TYPE_CP15;
1173 for (i = ARCH_TIMER_PHYS_SECURE_PPI; i < ARCH_TIMER_MAX_TIMER_PPI; i++)
1174 arch_timer_ppi[i] = irq_of_parse_and_map(np, i);
1176 arch_timer_kvm_info.virtual_irq = arch_timer_ppi[ARCH_TIMER_VIRT_PPI];
1178 rate = arch_timer_get_cntfrq();
1179 arch_timer_of_configure_rate(rate, np);
1181 arch_timer_c3stop = !of_property_read_bool(np, "always-on");
1183 /* Check for globally applicable workarounds */
1184 arch_timer_check_ool_workaround(ate_match_dt, np);
1187 * If we cannot rely on firmware initializing the timer registers then
1188 * we should use the physical timers instead.
1190 if (IS_ENABLED(CONFIG_ARM) &&
1191 of_property_read_bool(np, "arm,cpu-registers-not-fw-configured"))
1192 arch_timer_uses_ppi = ARCH_TIMER_PHYS_SECURE_PPI;
1194 arch_timer_uses_ppi = arch_timer_select_ppi();
1196 if (!arch_timer_ppi[arch_timer_uses_ppi]) {
1197 pr_err("No interrupt available, giving up\n");
1201 /* On some systems, the counter stops ticking when in suspend. */
1202 arch_counter_suspend_stop = of_property_read_bool(np,
1203 "arm,no-tick-in-suspend");
1205 ret = arch_timer_register();
1209 if (arch_timer_needs_of_probing())
1212 return arch_timer_common_init();
1214 TIMER_OF_DECLARE(armv7_arch_timer, "arm,armv7-timer", arch_timer_of_init);
1215 TIMER_OF_DECLARE(armv8_arch_timer, "arm,armv8-timer", arch_timer_of_init);
1218 arch_timer_mem_frame_get_cntfrq(struct arch_timer_mem_frame *frame)
1223 base = ioremap(frame->cntbase, frame->size);
1225 pr_err("Unable to map frame @ %pa\n", &frame->cntbase);
1229 rate = readl_relaxed(base + CNTFRQ);
1236 static struct arch_timer_mem_frame * __init
1237 arch_timer_mem_find_best_frame(struct arch_timer_mem *timer_mem)
1239 struct arch_timer_mem_frame *frame, *best_frame = NULL;
1240 void __iomem *cntctlbase;
1244 cntctlbase = ioremap(timer_mem->cntctlbase, timer_mem->size);
1246 pr_err("Can't map CNTCTLBase @ %pa\n",
1247 &timer_mem->cntctlbase);
1251 cnttidr = readl_relaxed(cntctlbase + CNTTIDR);
1254 * Try to find a virtual capable frame. Otherwise fall back to a
1255 * physical capable frame.
1257 for (i = 0; i < ARCH_TIMER_MEM_MAX_FRAMES; i++) {
1258 u32 cntacr = CNTACR_RFRQ | CNTACR_RWPT | CNTACR_RPCT |
1259 CNTACR_RWVT | CNTACR_RVOFF | CNTACR_RVCT;
1261 frame = &timer_mem->frame[i];
1265 /* Try enabling everything, and see what sticks */
1266 writel_relaxed(cntacr, cntctlbase + CNTACR(i));
1267 cntacr = readl_relaxed(cntctlbase + CNTACR(i));
1269 if ((cnttidr & CNTTIDR_VIRT(i)) &&
1270 !(~cntacr & (CNTACR_RWVT | CNTACR_RVCT))) {
1272 arch_timer_mem_use_virtual = true;
1276 if (~cntacr & (CNTACR_RWPT | CNTACR_RPCT))
1282 iounmap(cntctlbase);
1288 arch_timer_mem_frame_register(struct arch_timer_mem_frame *frame)
1293 if (arch_timer_mem_use_virtual)
1294 irq = frame->virt_irq;
1296 irq = frame->phys_irq;
1299 pr_err("Frame missing %s irq.\n",
1300 arch_timer_mem_use_virtual ? "virt" : "phys");
1304 if (!request_mem_region(frame->cntbase, frame->size,
1308 base = ioremap(frame->cntbase, frame->size);
1310 pr_err("Can't map frame's registers\n");
1314 ret = arch_timer_mem_register(base, irq);
1320 arch_counter_base = base;
1321 arch_timers_present |= ARCH_TIMER_TYPE_MEM;
1326 static int __init arch_timer_mem_of_init(struct device_node *np)
1328 struct arch_timer_mem *timer_mem;
1329 struct arch_timer_mem_frame *frame;
1330 struct device_node *frame_node;
1331 struct resource res;
1335 timer_mem = kzalloc(sizeof(*timer_mem), GFP_KERNEL);
1339 if (of_address_to_resource(np, 0, &res))
1341 timer_mem->cntctlbase = res.start;
1342 timer_mem->size = resource_size(&res);
1344 for_each_available_child_of_node(np, frame_node) {
1346 struct arch_timer_mem_frame *frame;
1348 if (of_property_read_u32(frame_node, "frame-number", &n)) {
1349 pr_err(FW_BUG "Missing frame-number.\n");
1350 of_node_put(frame_node);
1353 if (n >= ARCH_TIMER_MEM_MAX_FRAMES) {
1354 pr_err(FW_BUG "Wrong frame-number, only 0-%u are permitted.\n",
1355 ARCH_TIMER_MEM_MAX_FRAMES - 1);
1356 of_node_put(frame_node);
1359 frame = &timer_mem->frame[n];
1362 pr_err(FW_BUG "Duplicated frame-number.\n");
1363 of_node_put(frame_node);
1367 if (of_address_to_resource(frame_node, 0, &res)) {
1368 of_node_put(frame_node);
1371 frame->cntbase = res.start;
1372 frame->size = resource_size(&res);
1374 frame->virt_irq = irq_of_parse_and_map(frame_node,
1375 ARCH_TIMER_VIRT_SPI);
1376 frame->phys_irq = irq_of_parse_and_map(frame_node,
1377 ARCH_TIMER_PHYS_SPI);
1379 frame->valid = true;
1382 frame = arch_timer_mem_find_best_frame(timer_mem);
1384 pr_err("Unable to find a suitable frame in timer @ %pa\n",
1385 &timer_mem->cntctlbase);
1390 rate = arch_timer_mem_frame_get_cntfrq(frame);
1391 arch_timer_of_configure_rate(rate, np);
1393 ret = arch_timer_mem_frame_register(frame);
1394 if (!ret && !arch_timer_needs_of_probing())
1395 ret = arch_timer_common_init();
1400 TIMER_OF_DECLARE(armv7_arch_timer_mem, "arm,armv7-timer-mem",
1401 arch_timer_mem_of_init);
1403 #ifdef CONFIG_ACPI_GTDT
1405 arch_timer_mem_verify_cntfrq(struct arch_timer_mem *timer_mem)
1407 struct arch_timer_mem_frame *frame;
1411 for (i = 0; i < ARCH_TIMER_MEM_MAX_FRAMES; i++) {
1412 frame = &timer_mem->frame[i];
1417 rate = arch_timer_mem_frame_get_cntfrq(frame);
1418 if (rate == arch_timer_rate)
1421 pr_err(FW_BUG "CNTFRQ mismatch: frame @ %pa: (0x%08lx), CPU: (0x%08lx)\n",
1423 (unsigned long)rate, (unsigned long)arch_timer_rate);
1431 static int __init arch_timer_mem_acpi_init(int platform_timer_count)
1433 struct arch_timer_mem *timers, *timer;
1434 struct arch_timer_mem_frame *frame, *best_frame = NULL;
1435 int timer_count, i, ret = 0;
1437 timers = kcalloc(platform_timer_count, sizeof(*timers),
1442 ret = acpi_arch_timer_mem_init(timers, &timer_count);
1443 if (ret || !timer_count)
1447 * While unlikely, it's theoretically possible that none of the frames
1448 * in a timer expose the combination of feature we want.
1450 for (i = 0; i < timer_count; i++) {
1453 frame = arch_timer_mem_find_best_frame(timer);
1457 ret = arch_timer_mem_verify_cntfrq(timer);
1459 pr_err("Disabling MMIO timers due to CNTFRQ mismatch\n");
1463 if (!best_frame) /* implies !frame */
1465 * Only complain about missing suitable frames if we
1466 * haven't already found one in a previous iteration.
1468 pr_err("Unable to find a suitable frame in timer @ %pa\n",
1469 &timer->cntctlbase);
1473 ret = arch_timer_mem_frame_register(best_frame);
1479 /* Initialize per-processor generic timer and memory-mapped timer(if present) */
1480 static int __init arch_timer_acpi_init(struct acpi_table_header *table)
1482 int ret, platform_timer_count;
1484 if (arch_timers_present & ARCH_TIMER_TYPE_CP15) {
1485 pr_warn("already initialized, skipping\n");
1489 arch_timers_present |= ARCH_TIMER_TYPE_CP15;
1491 ret = acpi_gtdt_init(table, &platform_timer_count);
1493 pr_err("Failed to init GTDT table.\n");
1497 arch_timer_ppi[ARCH_TIMER_PHYS_NONSECURE_PPI] =
1498 acpi_gtdt_map_ppi(ARCH_TIMER_PHYS_NONSECURE_PPI);
1500 arch_timer_ppi[ARCH_TIMER_VIRT_PPI] =
1501 acpi_gtdt_map_ppi(ARCH_TIMER_VIRT_PPI);
1503 arch_timer_ppi[ARCH_TIMER_HYP_PPI] =
1504 acpi_gtdt_map_ppi(ARCH_TIMER_HYP_PPI);
1506 arch_timer_kvm_info.virtual_irq = arch_timer_ppi[ARCH_TIMER_VIRT_PPI];
1509 * When probing via ACPI, we have no mechanism to override the sysreg
1510 * CNTFRQ value. This *must* be correct.
1512 arch_timer_rate = arch_timer_get_cntfrq();
1513 if (!arch_timer_rate) {
1514 pr_err(FW_BUG "frequency not available.\n");
1518 arch_timer_uses_ppi = arch_timer_select_ppi();
1519 if (!arch_timer_ppi[arch_timer_uses_ppi]) {
1520 pr_err("No interrupt available, giving up\n");
1524 /* Always-on capability */
1525 arch_timer_c3stop = acpi_gtdt_c3stop(arch_timer_uses_ppi);
1527 /* Check for globally applicable workarounds */
1528 arch_timer_check_ool_workaround(ate_match_acpi_oem_info, table);
1530 ret = arch_timer_register();
1534 if (platform_timer_count &&
1535 arch_timer_mem_acpi_init(platform_timer_count))
1536 pr_err("Failed to initialize memory-mapped timer.\n");
1538 return arch_timer_common_init();
1540 TIMER_ACPI_DECLARE(arch_timer, ACPI_SIG_GTDT, arch_timer_acpi_init);