1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2016-2017 Socionext Inc.
4 * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
8 #include <clk-uclass.h>
10 #include <dm/device_compat.h>
11 #include <linux/bitops.h>
12 #include <linux/bug.h>
14 #include <linux/sizes.h>
16 #include "clk-uniphier.h"
19 * struct uniphier_clk_priv - private data for UniPhier clock driver
21 * @base: base address of the clock provider
22 * @data: SoC specific data
24 struct uniphier_clk_priv {
27 const struct uniphier_clk_data *data;
30 static void uniphier_clk_gate_enable(struct uniphier_clk_priv *priv,
31 const struct uniphier_clk_gate_data *gate)
35 val = readl(priv->base + gate->reg);
36 val |= BIT(gate->bit);
37 writel(val, priv->base + gate->reg);
40 static void uniphier_clk_mux_set_parent(struct uniphier_clk_priv *priv,
41 const struct uniphier_clk_mux_data *mux,
47 for (i = 0; i < mux->num_parents; i++) {
48 if (mux->parent_ids[i] != id)
51 val = readl(priv->base + mux->reg);
52 val &= ~mux->masks[i];
54 writel(val, priv->base + mux->reg);
61 static u8 uniphier_clk_mux_get_parent(struct uniphier_clk_priv *priv,
62 const struct uniphier_clk_mux_data *mux)
67 val = readl(priv->base + mux->reg);
69 for (i = 0; i < mux->num_parents; i++)
70 if ((mux->masks[i] & val) == mux->vals[i])
71 return mux->parent_ids[i];
73 dev_err(priv->dev, "invalid mux setting\n");
75 return UNIPHIER_CLK_ID_INVALID;
78 static const struct uniphier_clk_data *uniphier_clk_get_data(
79 struct uniphier_clk_priv *priv, u8 id)
81 const struct uniphier_clk_data *data;
83 for (data = priv->data; data->type != UNIPHIER_CLK_TYPE_END; data++)
87 dev_err(priv->dev, "id=%u not found\n", id);
92 static const struct uniphier_clk_data *uniphier_clk_get_parent_data(
93 struct uniphier_clk_priv *priv,
94 const struct uniphier_clk_data *data)
96 const struct uniphier_clk_data *parent_data;
97 u8 parent_id = UNIPHIER_CLK_ID_INVALID;
100 case UNIPHIER_CLK_TYPE_GATE:
101 parent_id = data->data.gate.parent_id;
103 case UNIPHIER_CLK_TYPE_MUX:
104 parent_id = uniphier_clk_mux_get_parent(priv, &data->data.mux);
110 if (parent_id == UNIPHIER_CLK_ID_INVALID)
113 parent_data = uniphier_clk_get_data(priv, parent_id);
115 WARN_ON(!parent_data);
120 static void __uniphier_clk_enable(struct uniphier_clk_priv *priv,
121 const struct uniphier_clk_data *data)
123 const struct uniphier_clk_data *parent_data;
125 if (data->type == UNIPHIER_CLK_TYPE_GATE)
126 uniphier_clk_gate_enable(priv, &data->data.gate);
128 parent_data = uniphier_clk_get_parent_data(priv, data);
132 return __uniphier_clk_enable(priv, parent_data);
135 static int uniphier_clk_enable(struct clk *clk)
137 struct uniphier_clk_priv *priv = dev_get_priv(clk->dev);
138 const struct uniphier_clk_data *data;
140 data = uniphier_clk_get_data(priv, clk->id);
144 __uniphier_clk_enable(priv, data);
149 static unsigned long __uniphier_clk_get_rate(
150 struct uniphier_clk_priv *priv,
151 const struct uniphier_clk_data *data)
153 const struct uniphier_clk_data *parent_data;
155 if (data->type == UNIPHIER_CLK_TYPE_FIXED_RATE)
156 return data->data.rate.fixed_rate;
158 parent_data = uniphier_clk_get_parent_data(priv, data);
162 return __uniphier_clk_get_rate(priv, parent_data);
165 static unsigned long uniphier_clk_get_rate(struct clk *clk)
167 struct uniphier_clk_priv *priv = dev_get_priv(clk->dev);
168 const struct uniphier_clk_data *data;
170 data = uniphier_clk_get_data(priv, clk->id);
174 return __uniphier_clk_get_rate(priv, data);
177 static unsigned long __uniphier_clk_set_rate(
178 struct uniphier_clk_priv *priv,
179 const struct uniphier_clk_data *data,
180 unsigned long rate, bool set)
182 const struct uniphier_clk_data *best_parent_data = NULL;
183 const struct uniphier_clk_data *parent_data;
184 unsigned long best_rate = 0;
185 unsigned long parent_rate;
189 if (data->type == UNIPHIER_CLK_TYPE_FIXED_RATE)
190 return data->data.rate.fixed_rate;
192 if (data->type == UNIPHIER_CLK_TYPE_GATE) {
193 parent_data = uniphier_clk_get_parent_data(priv, data);
197 return __uniphier_clk_set_rate(priv, parent_data, rate, set);
200 if (WARN_ON(data->type != UNIPHIER_CLK_TYPE_MUX))
203 for (i = 0; i < data->data.mux.num_parents; i++) {
204 parent_id = data->data.mux.parent_ids[i];
205 parent_data = uniphier_clk_get_data(priv, parent_id);
206 if (WARN_ON(!parent_data))
209 parent_rate = __uniphier_clk_set_rate(priv, parent_data, rate,
212 if (parent_rate <= rate && best_rate < parent_rate) {
213 best_rate = parent_rate;
214 best_parent_data = parent_data;
218 dev_dbg(priv->dev, "id=%u, best_rate=%lu\n", data->id, best_rate);
220 if (!best_parent_data)
226 uniphier_clk_mux_set_parent(priv, &data->data.mux,
227 best_parent_data->id);
229 return best_rate = __uniphier_clk_set_rate(priv, best_parent_data,
233 static unsigned long uniphier_clk_set_rate(struct clk *clk, ulong rate)
235 struct uniphier_clk_priv *priv = dev_get_priv(clk->dev);
236 const struct uniphier_clk_data *data;
238 data = uniphier_clk_get_data(priv, clk->id);
242 return __uniphier_clk_set_rate(priv, data, rate, true);
245 static const struct clk_ops uniphier_clk_ops = {
246 .enable = uniphier_clk_enable,
247 .get_rate = uniphier_clk_get_rate,
248 .set_rate = uniphier_clk_set_rate,
251 static int uniphier_clk_probe(struct udevice *dev)
253 struct uniphier_clk_priv *priv = dev_get_priv(dev);
256 addr = dev_read_addr(dev->parent);
257 if (addr == FDT_ADDR_T_NONE)
260 priv->base = devm_ioremap(dev, addr, SZ_4K);
265 priv->data = (void *)dev_get_driver_data(dev);
270 static const struct udevice_id uniphier_clk_match[] = {
273 .compatible = "socionext,uniphier-ld4-clock",
274 .data = (ulong)uniphier_pxs2_sys_clk_data,
277 .compatible = "socionext,uniphier-pro4-clock",
278 .data = (ulong)uniphier_pxs2_sys_clk_data,
281 .compatible = "socionext,uniphier-sld8-clock",
282 .data = (ulong)uniphier_pxs2_sys_clk_data,
285 .compatible = "socionext,uniphier-pro5-clock",
286 .data = (ulong)uniphier_pxs2_sys_clk_data,
289 .compatible = "socionext,uniphier-pxs2-clock",
290 .data = (ulong)uniphier_pxs2_sys_clk_data,
293 .compatible = "socionext,uniphier-ld11-clock",
294 .data = (ulong)uniphier_ld20_sys_clk_data,
297 .compatible = "socionext,uniphier-ld20-clock",
298 .data = (ulong)uniphier_ld20_sys_clk_data,
301 .compatible = "socionext,uniphier-pxs3-clock",
302 .data = (ulong)uniphier_pxs3_sys_clk_data,
304 /* Media I/O clock */
306 .compatible = "socionext,uniphier-ld4-mio-clock",
307 .data = (ulong)uniphier_mio_clk_data,
310 .compatible = "socionext,uniphier-pro4-mio-clock",
311 .data = (ulong)uniphier_mio_clk_data,
314 .compatible = "socionext,uniphier-sld8-mio-clock",
315 .data = (ulong)uniphier_mio_clk_data,
318 .compatible = "socionext,uniphier-pro5-sd-clock",
319 .data = (ulong)uniphier_mio_clk_data,
322 .compatible = "socionext,uniphier-pxs2-sd-clock",
323 .data = (ulong)uniphier_mio_clk_data,
326 .compatible = "socionext,uniphier-ld11-mio-clock",
327 .data = (ulong)uniphier_mio_clk_data,
330 .compatible = "socionext,uniphier-ld20-sd-clock",
331 .data = (ulong)uniphier_mio_clk_data,
334 .compatible = "socionext,uniphier-pxs3-sd-clock",
335 .data = (ulong)uniphier_mio_clk_data,
340 U_BOOT_DRIVER(uniphier_clk) = {
341 .name = "uniphier-clk",
343 .of_match = uniphier_clk_match,
344 .probe = uniphier_clk_probe,
345 .priv_auto_alloc_size = sizeof(struct uniphier_clk_priv),
346 .ops = &uniphier_clk_ops,