1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2013 Texas Instruments, Inc.
7 * Tero Kristo <t-kristo@ti.com>
10 #include <linux/clk-provider.h>
11 #include <linux/slab.h>
12 #include <linux/err.h>
14 #include <linux/of_address.h>
15 #include <linux/clk/ti.h>
19 #define pr_fmt(fmt) "%s: " fmt, __func__
21 static u8 ti_clk_mux_get_parent(struct clk_hw *hw)
23 struct clk_omap_mux *mux = to_clk_omap_mux(hw);
24 int num_parents = clk_hw_get_num_parents(hw);
28 * FIXME need a mux-specific flag to determine if val is bitwise or
29 * numeric. e.g. sys_clkin_ck's clksel field is 3 bits wide, but ranges
30 * from 0x1 to 0x7 (index starts at one)
31 * OTOH, pmd_trace_clk_mux_ck uses a separate bit for each clock, so
32 * val = 0x4 really means "bit 2, index starts at bit 0"
34 val = ti_clk_ll_ops->clk_readl(&mux->reg) >> mux->shift;
40 for (i = 0; i < num_parents; i++)
41 if (mux->table[i] == val)
46 if (val && (mux->flags & CLK_MUX_INDEX_BIT))
49 if (val && (mux->flags & CLK_MUX_INDEX_ONE))
52 if (val >= num_parents)
58 static int ti_clk_mux_set_parent(struct clk_hw *hw, u8 index)
60 struct clk_omap_mux *mux = to_clk_omap_mux(hw);
64 index = mux->table[index];
66 if (mux->flags & CLK_MUX_INDEX_BIT)
67 index = (1 << ffs(index));
69 if (mux->flags & CLK_MUX_INDEX_ONE)
73 if (mux->flags & CLK_MUX_HIWORD_MASK) {
74 val = mux->mask << (mux->shift + 16);
76 val = ti_clk_ll_ops->clk_readl(&mux->reg);
77 val &= ~(mux->mask << mux->shift);
79 val |= index << mux->shift;
80 ti_clk_ll_ops->clk_writel(val, &mux->reg);
81 ti_clk_latch(&mux->reg, mux->latch);
87 * clk_mux_save_context - Save the parent selcted in the mux
88 * @hw: pointer struct clk_hw
90 * Save the parent mux value.
92 static int clk_mux_save_context(struct clk_hw *hw)
94 struct clk_omap_mux *mux = to_clk_omap_mux(hw);
96 mux->saved_parent = ti_clk_mux_get_parent(hw);
101 * clk_mux_restore_context - Restore the parent in the mux
102 * @hw: pointer struct clk_hw
104 * Restore the saved parent mux value.
106 static void clk_mux_restore_context(struct clk_hw *hw)
108 struct clk_omap_mux *mux = to_clk_omap_mux(hw);
110 ti_clk_mux_set_parent(hw, mux->saved_parent);
113 const struct clk_ops ti_clk_mux_ops = {
114 .get_parent = ti_clk_mux_get_parent,
115 .set_parent = ti_clk_mux_set_parent,
116 .determine_rate = __clk_mux_determine_rate,
117 .save_context = clk_mux_save_context,
118 .restore_context = clk_mux_restore_context,
121 static struct clk *_register_mux(struct device_node *node, const char *name,
122 const char * const *parent_names,
123 u8 num_parents, unsigned long flags,
124 struct clk_omap_reg *reg, u8 shift, u32 mask,
125 s8 latch, u8 clk_mux_flags, u32 *table)
127 struct clk_omap_mux *mux;
129 struct clk_init_data init;
131 /* allocate the mux */
132 mux = kzalloc(sizeof(*mux), GFP_KERNEL);
134 return ERR_PTR(-ENOMEM);
137 init.ops = &ti_clk_mux_ops;
139 init.parent_names = parent_names;
140 init.num_parents = num_parents;
142 /* struct clk_mux assignments */
143 memcpy(&mux->reg, reg, sizeof(*reg));
147 mux->flags = clk_mux_flags;
149 mux->hw.init = &init;
151 clk = of_ti_clk_register(node, &mux->hw, name);
160 * of_mux_clk_setup - Setup function for simple mux rate clock
161 * @node: DT node for the clock
163 * Sets up a basic clock multiplexer.
165 static void of_mux_clk_setup(struct device_node *node)
168 struct clk_omap_reg reg;
169 unsigned int num_parents;
170 const char **parent_names;
172 u8 clk_mux_flags = 0;
176 u32 flags = CLK_SET_RATE_NO_REPARENT;
178 num_parents = of_clk_get_parent_count(node);
179 if (num_parents < 2) {
180 pr_err("mux-clock %pOFn must have parents\n", node);
183 parent_names = kzalloc((sizeof(char *) * num_parents), GFP_KERNEL);
187 of_clk_parent_fill(node, parent_names, num_parents);
189 if (ti_clk_get_reg_addr(node, 0, ®))
192 of_property_read_u32(node, "ti,bit-shift", &shift);
194 of_property_read_u32(node, "ti,latch-bit", &latch);
196 if (of_property_read_bool(node, "ti,index-starts-at-one"))
197 clk_mux_flags |= CLK_MUX_INDEX_ONE;
199 if (of_property_read_bool(node, "ti,set-rate-parent"))
200 flags |= CLK_SET_RATE_PARENT;
202 /* Generate bit-mask based on parent info */
204 if (!(clk_mux_flags & CLK_MUX_INDEX_ONE))
207 mask = (1 << fls(mask)) - 1;
209 name = ti_dt_clk_name(node);
210 clk = _register_mux(node, name, parent_names, num_parents,
211 flags, ®, shift, mask, latch, clk_mux_flags,
215 of_clk_add_provider(node, of_clk_src_simple_get, clk);
220 CLK_OF_DECLARE(mux_clk, "ti,mux-clock", of_mux_clk_setup);
222 struct clk_hw *ti_clk_build_component_mux(struct ti_clk_mux *setup)
224 struct clk_omap_mux *mux;
230 mux = kzalloc(sizeof(*mux), GFP_KERNEL);
232 return ERR_PTR(-ENOMEM);
234 mux->shift = setup->bit_shift;
235 mux->latch = -EINVAL;
237 mux->reg.index = setup->module;
238 mux->reg.offset = setup->reg;
240 if (setup->flags & CLKF_INDEX_STARTS_AT_ONE)
241 mux->flags |= CLK_MUX_INDEX_ONE;
243 num_parents = setup->num_parents;
245 mux->mask = num_parents - 1;
246 mux->mask = (1 << fls(mux->mask)) - 1;
251 static void __init of_ti_composite_mux_clk_setup(struct device_node *node)
253 struct clk_omap_mux *mux;
254 unsigned int num_parents;
257 mux = kzalloc(sizeof(*mux), GFP_KERNEL);
261 if (ti_clk_get_reg_addr(node, 0, &mux->reg))
264 if (!of_property_read_u32(node, "ti,bit-shift", &val))
267 if (of_property_read_bool(node, "ti,index-starts-at-one"))
268 mux->flags |= CLK_MUX_INDEX_ONE;
270 num_parents = of_clk_get_parent_count(node);
272 if (num_parents < 2) {
273 pr_err("%pOFn must have parents\n", node);
277 mux->mask = num_parents - 1;
278 mux->mask = (1 << fls(mux->mask)) - 1;
280 if (!ti_clk_add_component(node, &mux->hw, CLK_COMPONENT_TYPE_MUX))
286 CLK_OF_DECLARE(ti_composite_mux_clk_setup, "ti,composite-mux-clock",
287 of_ti_composite_mux_clk_setup);