4 * Copyright (C) 2013 Texas Instruments, Inc.
6 * Tero Kristo <t-kristo@ti.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
12 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
13 * kind, whether express or implied; without even the implied warranty
14 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
18 #include <linux/clk-provider.h>
19 #include <linux/slab.h>
20 #include <linux/err.h>
22 #include <linux/of_address.h>
23 #include <linux/clk/ti.h>
27 #define pr_fmt(fmt) "%s: " fmt, __func__
29 static u8 ti_clk_mux_get_parent(struct clk_hw *hw)
31 struct clk_mux *mux = to_clk_mux(hw);
32 int num_parents = clk_hw_get_num_parents(hw);
36 * FIXME need a mux-specific flag to determine if val is bitwise or
37 * numeric. e.g. sys_clkin_ck's clksel field is 3 bits wide, but ranges
38 * from 0x1 to 0x7 (index starts at one)
39 * OTOH, pmd_trace_clk_mux_ck uses a separate bit for each clock, so
40 * val = 0x4 really means "bit 2, index starts at bit 0"
42 val = ti_clk_ll_ops->clk_readl(mux->reg) >> mux->shift;
48 for (i = 0; i < num_parents; i++)
49 if (mux->table[i] == val)
54 if (val && (mux->flags & CLK_MUX_INDEX_BIT))
57 if (val && (mux->flags & CLK_MUX_INDEX_ONE))
60 if (val >= num_parents)
66 static int ti_clk_mux_set_parent(struct clk_hw *hw, u8 index)
68 struct clk_mux *mux = to_clk_mux(hw);
72 index = mux->table[index];
74 if (mux->flags & CLK_MUX_INDEX_BIT)
75 index = (1 << ffs(index));
77 if (mux->flags & CLK_MUX_INDEX_ONE)
81 if (mux->flags & CLK_MUX_HIWORD_MASK) {
82 val = mux->mask << (mux->shift + 16);
84 val = ti_clk_ll_ops->clk_readl(mux->reg);
85 val &= ~(mux->mask << mux->shift);
87 val |= index << mux->shift;
88 ti_clk_ll_ops->clk_writel(val, mux->reg);
93 const struct clk_ops ti_clk_mux_ops = {
94 .get_parent = ti_clk_mux_get_parent,
95 .set_parent = ti_clk_mux_set_parent,
96 .determine_rate = __clk_mux_determine_rate,
99 static struct clk *_register_mux(struct device *dev, const char *name,
100 const char **parent_names, u8 num_parents,
101 unsigned long flags, void __iomem *reg,
102 u8 shift, u32 mask, u8 clk_mux_flags,
107 struct clk_init_data init;
109 /* allocate the mux */
110 mux = kzalloc(sizeof(*mux), GFP_KERNEL);
112 pr_err("%s: could not allocate mux clk\n", __func__);
113 return ERR_PTR(-ENOMEM);
117 init.ops = &ti_clk_mux_ops;
118 init.flags = flags | CLK_IS_BASIC;
119 init.parent_names = parent_names;
120 init.num_parents = num_parents;
122 /* struct clk_mux assignments */
126 mux->flags = clk_mux_flags;
128 mux->hw.init = &init;
130 clk = ti_clk_register(dev, &mux->hw, name);
138 struct clk *ti_clk_register_mux(struct ti_clk *setup)
140 struct ti_clk_mux *mux;
143 struct clk_omap_reg *reg_setup;
147 reg_setup = (struct clk_omap_reg *)®
150 flags = CLK_SET_RATE_NO_REPARENT;
152 mask = mux->num_parents;
153 if (!(mux->flags & CLKF_INDEX_STARTS_AT_ONE))
156 mask = (1 << fls(mask)) - 1;
157 reg_setup->index = mux->module;
158 reg_setup->offset = mux->reg;
160 if (mux->flags & CLKF_INDEX_STARTS_AT_ONE)
161 mux_flags |= CLK_MUX_INDEX_ONE;
163 if (mux->flags & CLKF_SET_RATE_PARENT)
164 flags |= CLK_SET_RATE_PARENT;
166 return _register_mux(NULL, setup->name, mux->parents, mux->num_parents,
167 flags, (void __iomem *)reg, mux->bit_shift, mask,
172 * of_mux_clk_setup - Setup function for simple mux rate clock
173 * @node: DT node for the clock
175 * Sets up a basic clock multiplexer.
177 static void of_mux_clk_setup(struct device_node *node)
181 unsigned int num_parents;
182 const char **parent_names;
183 u8 clk_mux_flags = 0;
186 u32 flags = CLK_SET_RATE_NO_REPARENT;
188 num_parents = of_clk_get_parent_count(node);
189 if (num_parents < 2) {
190 pr_err("mux-clock %s must have parents\n", node->name);
193 parent_names = kzalloc((sizeof(char *) * num_parents), GFP_KERNEL);
197 of_clk_parent_fill(node, parent_names, num_parents);
199 reg = ti_clk_get_reg_addr(node, 0);
204 of_property_read_u32(node, "ti,bit-shift", &shift);
206 if (of_property_read_bool(node, "ti,index-starts-at-one"))
207 clk_mux_flags |= CLK_MUX_INDEX_ONE;
209 if (of_property_read_bool(node, "ti,set-rate-parent"))
210 flags |= CLK_SET_RATE_PARENT;
212 /* Generate bit-mask based on parent info */
214 if (!(clk_mux_flags & CLK_MUX_INDEX_ONE))
217 mask = (1 << fls(mask)) - 1;
219 clk = _register_mux(NULL, node->name, parent_names, num_parents,
220 flags, reg, shift, mask, clk_mux_flags, NULL);
223 of_clk_add_provider(node, of_clk_src_simple_get, clk);
228 CLK_OF_DECLARE(mux_clk, "ti,mux-clock", of_mux_clk_setup);
230 struct clk_hw *ti_clk_build_component_mux(struct ti_clk_mux *setup)
233 struct clk_omap_reg *reg;
239 mux = kzalloc(sizeof(*mux), GFP_KERNEL);
241 return ERR_PTR(-ENOMEM);
243 reg = (struct clk_omap_reg *)&mux->reg;
245 mux->shift = setup->bit_shift;
247 reg->index = setup->module;
248 reg->offset = setup->reg;
250 if (setup->flags & CLKF_INDEX_STARTS_AT_ONE)
251 mux->flags |= CLK_MUX_INDEX_ONE;
253 num_parents = setup->num_parents;
255 mux->mask = num_parents - 1;
256 mux->mask = (1 << fls(mux->mask)) - 1;
261 static void __init of_ti_composite_mux_clk_setup(struct device_node *node)
264 unsigned int num_parents;
267 mux = kzalloc(sizeof(*mux), GFP_KERNEL);
271 mux->reg = ti_clk_get_reg_addr(node, 0);
273 if (IS_ERR(mux->reg))
276 if (!of_property_read_u32(node, "ti,bit-shift", &val))
279 if (of_property_read_bool(node, "ti,index-starts-at-one"))
280 mux->flags |= CLK_MUX_INDEX_ONE;
282 num_parents = of_clk_get_parent_count(node);
284 if (num_parents < 2) {
285 pr_err("%s must have parents\n", node->name);
289 mux->mask = num_parents - 1;
290 mux->mask = (1 << fls(mux->mask)) - 1;
292 if (!ti_clk_add_component(node, &mux->hw, CLK_COMPONENT_TYPE_MUX))
298 CLK_OF_DECLARE(ti_composite_mux_clk_setup, "ti,composite-mux-clock",
299 of_ti_composite_mux_clk_setup);