1 // SPDX-License-Identifier: GPL-2.0-only
3 * OMAP clkctrl clock support
5 * Copyright (C) 2017 Texas Instruments, Inc.
7 * Tero Kristo <t-kristo@ti.com>
10 #include <linux/clk-provider.h>
11 #include <linux/slab.h>
13 #include <linux/of_address.h>
14 #include <linux/clk/ti.h>
15 #include <linux/delay.h>
16 #include <linux/timekeeping.h>
21 #define OMAP4_MODULEMODE_MASK 0x3
23 #define MODULEMODE_HWCTRL 0x1
24 #define MODULEMODE_SWCTRL 0x2
26 #define OMAP4_IDLEST_MASK (0x3 << 16)
27 #define OMAP4_IDLEST_SHIFT 16
29 #define OMAP4_STBYST_MASK BIT(18)
30 #define OMAP4_STBYST_SHIFT 18
32 #define CLKCTRL_IDLEST_FUNCTIONAL 0x0
33 #define CLKCTRL_IDLEST_INTERFACE_IDLE 0x2
34 #define CLKCTRL_IDLEST_DISABLED 0x3
36 /* These timeouts are in us */
37 #define OMAP4_MAX_MODULE_READY_TIME 2000
38 #define OMAP4_MAX_MODULE_DISABLE_TIME 5000
40 static bool _early_timeout = true;
42 struct omap_clkctrl_provider {
44 struct list_head clocks;
48 struct omap_clkctrl_clk {
52 struct list_head node;
60 static const struct omap_clkctrl_data default_clkctrl_data[] __initconst = {
64 static u32 _omap4_idlest(u32 val)
66 val &= OMAP4_IDLEST_MASK;
67 val >>= OMAP4_IDLEST_SHIFT;
72 static bool _omap4_is_idle(u32 val)
74 val = _omap4_idlest(val);
76 return val == CLKCTRL_IDLEST_DISABLED;
79 static bool _omap4_is_ready(u32 val)
81 val = _omap4_idlest(val);
83 return val == CLKCTRL_IDLEST_FUNCTIONAL ||
84 val == CLKCTRL_IDLEST_INTERFACE_IDLE;
87 static bool _omap4_is_timeout(union omap4_timeout *time, u32 timeout)
90 * There are two special cases where ktime_to_ns() can't be
91 * used to track the timeouts. First one is during early boot
92 * when the timers haven't been initialized yet. The second
93 * one is during suspend-resume cycle while timekeeping is
94 * being suspended / resumed. Clocksource for the system
95 * can be from a timer that requires pm_runtime access, which
96 * will eventually bring us here with timekeeping_suspended,
97 * during both suspend entry and resume paths. This happens
98 * at least on am43xx platform. Account for flakeyness
99 * with udelay() by multiplying the timeout value by 2.
101 if (unlikely(_early_timeout || timekeeping_suspended)) {
102 if (time->cycles++ < timeout) {
107 if (!ktime_to_ns(time->start)) {
108 time->start = ktime_get();
112 if (ktime_us_delta(ktime_get(), time->start) < timeout) {
121 static int __init _omap4_disable_early_timeout(void)
123 _early_timeout = false;
127 arch_initcall(_omap4_disable_early_timeout);
129 static int _omap4_clkctrl_clk_enable(struct clk_hw *hw)
131 struct clk_hw_omap *clk = to_clk_hw_omap(hw);
134 union omap4_timeout timeout = { 0 };
137 ret = ti_clk_ll_ops->clkdm_clk_enable(clk->clkdm, hw->clk);
140 "%s: could not enable %s's clockdomain %s: %d\n",
141 __func__, clk_hw_get_name(hw),
142 clk->clkdm_name, ret);
147 if (!clk->enable_bit)
150 val = ti_clk_ll_ops->clk_readl(&clk->enable_reg);
152 val &= ~OMAP4_MODULEMODE_MASK;
153 val |= clk->enable_bit;
155 ti_clk_ll_ops->clk_writel(val, &clk->enable_reg);
157 if (test_bit(NO_IDLEST, &clk->flags))
160 /* Wait until module is enabled */
161 while (!_omap4_is_ready(ti_clk_ll_ops->clk_readl(&clk->enable_reg))) {
162 if (_omap4_is_timeout(&timeout, OMAP4_MAX_MODULE_READY_TIME)) {
163 pr_err("%s: failed to enable\n", clk_hw_get_name(hw));
171 static void _omap4_clkctrl_clk_disable(struct clk_hw *hw)
173 struct clk_hw_omap *clk = to_clk_hw_omap(hw);
175 union omap4_timeout timeout = { 0 };
177 if (!clk->enable_bit)
180 val = ti_clk_ll_ops->clk_readl(&clk->enable_reg);
182 val &= ~OMAP4_MODULEMODE_MASK;
184 ti_clk_ll_ops->clk_writel(val, &clk->enable_reg);
186 if (test_bit(NO_IDLEST, &clk->flags))
189 /* Wait until module is disabled */
190 while (!_omap4_is_idle(ti_clk_ll_ops->clk_readl(&clk->enable_reg))) {
191 if (_omap4_is_timeout(&timeout,
192 OMAP4_MAX_MODULE_DISABLE_TIME)) {
193 pr_err("%s: failed to disable\n", clk_hw_get_name(hw));
200 ti_clk_ll_ops->clkdm_clk_disable(clk->clkdm, hw->clk);
203 static int _omap4_clkctrl_clk_is_enabled(struct clk_hw *hw)
205 struct clk_hw_omap *clk = to_clk_hw_omap(hw);
208 val = ti_clk_ll_ops->clk_readl(&clk->enable_reg);
210 if (val & clk->enable_bit)
216 static const struct clk_ops omap4_clkctrl_clk_ops = {
217 .enable = _omap4_clkctrl_clk_enable,
218 .disable = _omap4_clkctrl_clk_disable,
219 .is_enabled = _omap4_clkctrl_clk_is_enabled,
220 .init = omap2_init_clk_clkdm,
223 static struct clk_hw *_ti_omap4_clkctrl_xlate(struct of_phandle_args *clkspec,
226 struct omap_clkctrl_provider *provider = data;
227 struct omap_clkctrl_clk *entry = NULL, *iter;
229 if (clkspec->args_count != 2)
230 return ERR_PTR(-EINVAL);
232 pr_debug("%s: looking for %x:%x\n", __func__,
233 clkspec->args[0], clkspec->args[1]);
235 list_for_each_entry(iter, &provider->clocks, node) {
236 if (iter->reg_offset == clkspec->args[0] &&
237 iter->bit_offset == clkspec->args[1]) {
244 return ERR_PTR(-EINVAL);
249 /* Get clkctrl clock base name based on clkctrl_name or dts node */
250 static const char * __init clkctrl_get_clock_name(struct device_node *np,
251 const char *clkctrl_name,
252 int offset, int index,
257 /* l4per-clkctrl:1234:0 style naming based on clkctrl_name */
258 if (clkctrl_name && !legacy_naming) {
259 clock_name = kasprintf(GFP_KERNEL, "%s-clkctrl:%04x:%d",
260 clkctrl_name, offset, index);
261 strreplace(clock_name, '_', '-');
266 /* l4per:1234:0 old style naming based on clkctrl_name */
268 return kasprintf(GFP_KERNEL, "%s_cm:clk:%04x:%d",
269 clkctrl_name, offset, index);
271 /* l4per_cm:1234:0 old style naming based on parent node name */
273 return kasprintf(GFP_KERNEL, "%pOFn:clk:%04x:%d",
274 np->parent, offset, index);
276 /* l4per-clkctrl:1234:0 style naming based on node name */
277 return kasprintf(GFP_KERNEL, "%pOFn:%04x:%d", np, offset, index);
281 _ti_clkctrl_clk_register(struct omap_clkctrl_provider *provider,
282 struct device_node *node, struct clk_hw *clk_hw,
283 u16 offset, u8 bit, const char * const *parents,
284 int num_parents, const struct clk_ops *ops,
285 const char *clkctrl_name)
287 struct clk_init_data init = { NULL };
289 struct omap_clkctrl_clk *clkctrl_clk;
292 init.name = clkctrl_get_clock_name(node, clkctrl_name, offset, bit,
293 ti_clk_get_features()->flags &
294 TI_CLK_CLKCTRL_COMPAT);
296 clkctrl_clk = kzalloc(sizeof(*clkctrl_clk), GFP_KERNEL);
297 if (!init.name || !clkctrl_clk) {
302 clk_hw->init = &init;
303 init.parent_names = parents;
304 init.num_parents = num_parents;
308 clk = ti_clk_register(NULL, clk_hw, init.name);
309 if (IS_ERR_OR_NULL(clk)) {
314 clkctrl_clk->reg_offset = offset;
315 clkctrl_clk->bit_offset = bit;
316 clkctrl_clk->clk = clk_hw;
318 list_add(&clkctrl_clk->node, &provider->clocks);
329 _ti_clkctrl_setup_gate(struct omap_clkctrl_provider *provider,
330 struct device_node *node, u16 offset,
331 const struct omap_clkctrl_bit_data *data,
332 void __iomem *reg, const char *clkctrl_name)
334 struct clk_hw_omap *clk_hw;
336 clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL);
340 clk_hw->enable_bit = data->bit;
341 clk_hw->enable_reg.ptr = reg;
343 if (_ti_clkctrl_clk_register(provider, node, &clk_hw->hw, offset,
344 data->bit, data->parents, 1,
345 &omap_gate_clk_ops, clkctrl_name))
350 _ti_clkctrl_setup_mux(struct omap_clkctrl_provider *provider,
351 struct device_node *node, u16 offset,
352 const struct omap_clkctrl_bit_data *data,
353 void __iomem *reg, const char *clkctrl_name)
355 struct clk_omap_mux *mux;
357 const char * const *pname;
359 mux = kzalloc(sizeof(*mux), GFP_KERNEL);
363 pname = data->parents;
369 mux->mask = num_parents;
370 if (!(mux->flags & CLK_MUX_INDEX_ONE))
373 mux->mask = (1 << fls(mux->mask)) - 1;
375 mux->shift = data->bit;
378 if (_ti_clkctrl_clk_register(provider, node, &mux->hw, offset,
379 data->bit, data->parents, num_parents,
380 &ti_clk_mux_ops, clkctrl_name))
385 _ti_clkctrl_setup_div(struct omap_clkctrl_provider *provider,
386 struct device_node *node, u16 offset,
387 const struct omap_clkctrl_bit_data *data,
388 void __iomem *reg, const char *clkctrl_name)
390 struct clk_omap_divider *div;
391 const struct omap_clkctrl_div_data *div_data = data->data;
394 div = kzalloc(sizeof(*div), GFP_KERNEL);
399 div->shift = data->bit;
400 div->flags = div_data->flags;
402 if (div->flags & CLK_DIVIDER_POWER_OF_TWO)
403 div_flags |= CLKF_INDEX_POWER_OF_TWO;
405 if (ti_clk_parse_divider_data((int *)div_data->dividers, 0,
406 div_data->max_div, div_flags,
408 pr_err("%s: Data parsing for %pOF:%04x:%d failed\n", __func__,
409 node, offset, data->bit);
414 if (_ti_clkctrl_clk_register(provider, node, &div->hw, offset,
415 data->bit, data->parents, 1,
416 &ti_clk_divider_ops, clkctrl_name))
421 _ti_clkctrl_setup_subclks(struct omap_clkctrl_provider *provider,
422 struct device_node *node,
423 const struct omap_clkctrl_reg_data *data,
424 void __iomem *reg, const char *clkctrl_name)
426 const struct omap_clkctrl_bit_data *bits = data->bit_data;
432 switch (bits->type) {
434 _ti_clkctrl_setup_gate(provider, node, data->offset,
435 bits, reg, clkctrl_name);
439 _ti_clkctrl_setup_div(provider, node, data->offset,
440 bits, reg, clkctrl_name);
444 _ti_clkctrl_setup_mux(provider, node, data->offset,
445 bits, reg, clkctrl_name);
449 pr_err("%s: bad subclk type: %d\n", __func__,
457 static void __init _clkctrl_add_provider(void *data,
458 struct device_node *np)
460 of_clk_add_hw_provider(np, _ti_omap4_clkctrl_xlate, data);
464 * Get clock name based on "clock-output-names" property or the
465 * compatible property for clkctrl.
467 static const char * __init clkctrl_get_name(struct device_node *np)
469 struct property *prop;
470 const int prefix_len = 11;
475 if (!of_property_read_string_index(np, "clock-output-names", 0,
480 len = strlen(output);
481 end = strstr(output, "_clkctrl");
484 name = kstrndup(output, len, GFP_KERNEL);
489 of_property_for_each_string(np, "compatible", prop, compat) {
490 if (!strncmp("ti,clkctrl-", compat, prefix_len)) {
491 /* Two letter minimum name length for l3, l4 etc */
492 if (strnlen(compat + prefix_len, 16) < 2)
494 name = kasprintf(GFP_KERNEL, "%s", compat + prefix_len);
497 strreplace(name, '-', '_');
506 static void __init _ti_omap4_clkctrl_setup(struct device_node *node)
508 struct omap_clkctrl_provider *provider;
509 const struct omap_clkctrl_data *data = default_clkctrl_data;
510 const struct omap_clkctrl_reg_data *reg_data;
511 struct clk_init_data init = { NULL };
512 struct clk_hw_omap *hw;
514 struct omap_clkctrl_clk *clkctrl_clk = NULL;
517 const char *clkctrl_name;
523 if (!(ti_clk_get_features()->flags & TI_CLK_CLKCTRL_COMPAT) &&
524 of_node_name_eq(node, "clk"))
525 ti_clk_features.flags |= TI_CLK_CLKCTRL_COMPAT;
527 addrp = of_get_address(node, 0, NULL, NULL);
528 addr = (u32)of_translate_address(node, addrp);
530 #ifdef CONFIG_ARCH_OMAP4
531 if (of_machine_is_compatible("ti,omap4"))
532 data = omap4_clkctrl_data;
534 #ifdef CONFIG_SOC_OMAP5
535 if (of_machine_is_compatible("ti,omap5"))
536 data = omap5_clkctrl_data;
538 #ifdef CONFIG_SOC_DRA7XX
539 if (of_machine_is_compatible("ti,dra7"))
540 data = dra7_clkctrl_data;
541 if (of_machine_is_compatible("ti,dra72"))
542 soc_mask = CLKF_SOC_DRA72;
543 if (of_machine_is_compatible("ti,dra74"))
544 soc_mask = CLKF_SOC_DRA74;
545 if (of_machine_is_compatible("ti,dra76"))
546 soc_mask = CLKF_SOC_DRA76;
548 #ifdef CONFIG_SOC_AM33XX
549 if (of_machine_is_compatible("ti,am33xx"))
550 data = am3_clkctrl_data;
552 #ifdef CONFIG_SOC_AM43XX
553 if (of_machine_is_compatible("ti,am4372"))
554 data = am4_clkctrl_data;
556 if (of_machine_is_compatible("ti,am438x"))
557 data = am438x_clkctrl_data;
559 #ifdef CONFIG_SOC_TI81XX
560 if (of_machine_is_compatible("ti,dm814"))
561 data = dm814_clkctrl_data;
563 if (of_machine_is_compatible("ti,dm816"))
564 data = dm816_clkctrl_data;
567 if (ti_clk_get_features()->flags & TI_CLK_DEVICE_TYPE_GP)
568 soc_mask |= CLKF_SOC_NONSEC;
571 if (addr == data->addr)
578 pr_err("%pOF not found from clkctrl data.\n", node);
582 provider = kzalloc(sizeof(*provider), GFP_KERNEL);
586 provider->base = of_iomap(node, 0);
588 legacy_naming = ti_clk_get_features()->flags & TI_CLK_CLKCTRL_COMPAT;
589 clkctrl_name = clkctrl_get_name(node);
591 provider->clkdm_name = kasprintf(GFP_KERNEL,
592 "%s_clkdm", clkctrl_name);
597 * The code below can be removed when all clkctrl nodes use domain
598 * specific compatible property and standard clock node naming
601 provider->clkdm_name = kasprintf(GFP_KERNEL, "%pOFnxxx", node->parent);
602 if (!provider->clkdm_name) {
608 * Create default clkdm name, replace _cm from end of parent
609 * node name with _clkdm
611 provider->clkdm_name[strlen(provider->clkdm_name) - 2] = 0;
613 provider->clkdm_name = kasprintf(GFP_KERNEL, "%pOFn", node);
614 if (!provider->clkdm_name) {
620 * Create default clkdm name, replace _clkctrl from end of
621 * node name with _clkdm
623 provider->clkdm_name[strlen(provider->clkdm_name) - 7] = 0;
626 strcat(provider->clkdm_name, "clkdm");
628 /* Replace any dash from the clkdm name with underscore */
629 c = provider->clkdm_name;
637 INIT_LIST_HEAD(&provider->clocks);
639 /* Generate clocks */
640 reg_data = data->regs;
642 while (reg_data->parent) {
643 if ((reg_data->flags & CLKF_SOC_MASK) &&
644 (reg_data->flags & soc_mask) == 0) {
649 hw = kzalloc(sizeof(*hw), GFP_KERNEL);
653 hw->enable_reg.ptr = provider->base + reg_data->offset;
655 _ti_clkctrl_setup_subclks(provider, node, reg_data,
656 hw->enable_reg.ptr, clkctrl_name);
658 if (reg_data->flags & CLKF_SW_SUP)
659 hw->enable_bit = MODULEMODE_SWCTRL;
660 if (reg_data->flags & CLKF_HW_SUP)
661 hw->enable_bit = MODULEMODE_HWCTRL;
662 if (reg_data->flags & CLKF_NO_IDLEST)
663 set_bit(NO_IDLEST, &hw->flags);
665 if (reg_data->clkdm_name)
666 hw->clkdm_name = reg_data->clkdm_name;
668 hw->clkdm_name = provider->clkdm_name;
670 init.parent_names = ®_data->parent;
671 init.num_parents = 1;
673 if (reg_data->flags & CLKF_SET_RATE_PARENT)
674 init.flags |= CLK_SET_RATE_PARENT;
676 init.name = clkctrl_get_clock_name(node, clkctrl_name,
682 clkctrl_clk = kzalloc(sizeof(*clkctrl_clk), GFP_KERNEL);
686 init.ops = &omap4_clkctrl_clk_ops;
689 clk = ti_clk_register_omap_hw(NULL, &hw->hw, init.name);
690 if (IS_ERR_OR_NULL(clk))
693 clkctrl_clk->reg_offset = reg_data->offset;
694 clkctrl_clk->clk = &hw->hw;
696 list_add(&clkctrl_clk->node, &provider->clocks);
701 ret = of_clk_add_hw_provider(node, _ti_omap4_clkctrl_xlate, provider);
702 if (ret == -EPROBE_DEFER)
703 ti_clk_retry_init(node, provider, _clkctrl_add_provider);
715 CLK_OF_DECLARE(ti_omap4_clkctrl_clock, "ti,clkctrl",
716 _ti_omap4_clkctrl_setup);
719 * ti_clk_is_in_standby - Check if clkctrl clock is in standby or not
720 * @clk: clock to check standby status for
722 * Finds whether the provided clock is in standby mode or not. Returns
723 * true if the provided clock is a clkctrl type clock and it is in standby,
726 bool ti_clk_is_in_standby(struct clk *clk)
729 struct clk_hw_omap *hwclk;
732 hw = __clk_get_hw(clk);
734 if (!omap2_clk_is_hw_omap(hw))
737 hwclk = to_clk_hw_omap(hw);
739 val = ti_clk_ll_ops->clk_readl(&hwclk->enable_reg);
741 if (val & OMAP4_STBYST_MASK)
746 EXPORT_SYMBOL_GPL(ti_clk_is_in_standby);