1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2012-2020 NVIDIA CORPORATION. All rights reserved.
8 #include <linux/clk-provider.h>
9 #include <linux/clkdev.h>
11 #include <linux/of_address.h>
12 #include <linux/syscore_ops.h>
13 #include <linux/delay.h>
14 #include <linux/export.h>
15 #include <linux/mutex.h>
16 #include <linux/clk/tegra.h>
17 #include <dt-bindings/clock/tegra210-car.h>
18 #include <dt-bindings/reset/tegra210-car.h>
19 #include <linux/sizes.h>
20 #include <soc/tegra/pmc.h>
26 * TEGRA210_CAR_BANK_COUNT: the number of peripheral clock register
27 * banks present in the Tegra210 CAR IP block. The banks are
28 * identified by single letters, e.g.: L, H, U, V, W, X, Y. See
29 * periph_regs[] in drivers/clk/tegra/clk.c
31 #define TEGRA210_CAR_BANK_COUNT 7
33 #define CLK_SOURCE_CSITE 0x1d4
34 #define CLK_SOURCE_EMC 0x19c
35 #define CLK_SOURCE_SOR1 0x410
36 #define CLK_SOURCE_SOR0 0x414
37 #define CLK_SOURCE_LA 0x1f8
38 #define CLK_SOURCE_SDMMC2 0x154
39 #define CLK_SOURCE_SDMMC4 0x164
40 #define CLK_SOURCE_EMC_DLL 0x664
42 #define PLLC_BASE 0x80
44 #define PLLC_MISC0 0x88
45 #define PLLC_MISC1 0x8c
46 #define PLLC_MISC2 0x5d0
47 #define PLLC_MISC3 0x5d4
49 #define PLLC2_BASE 0x4e8
50 #define PLLC2_MISC0 0x4ec
51 #define PLLC2_MISC1 0x4f0
52 #define PLLC2_MISC2 0x4f4
53 #define PLLC2_MISC3 0x4f8
55 #define PLLC3_BASE 0x4fc
56 #define PLLC3_MISC0 0x500
57 #define PLLC3_MISC1 0x504
58 #define PLLC3_MISC2 0x508
59 #define PLLC3_MISC3 0x50c
61 #define PLLM_BASE 0x90
62 #define PLLM_MISC1 0x98
63 #define PLLM_MISC2 0x9c
64 #define PLLP_BASE 0xa0
65 #define PLLP_MISC0 0xac
66 #define PLLP_MISC1 0x680
67 #define PLLA_BASE 0xb0
68 #define PLLA_MISC0 0xbc
69 #define PLLA_MISC1 0xb8
70 #define PLLA_MISC2 0x5d8
71 #define PLLD_BASE 0xd0
72 #define PLLD_MISC0 0xdc
73 #define PLLD_MISC1 0xd8
74 #define PLLU_BASE 0xc0
75 #define PLLU_OUTA 0xc4
76 #define PLLU_MISC0 0xcc
77 #define PLLU_MISC1 0xc8
78 #define PLLX_BASE 0xe0
79 #define PLLX_MISC0 0xe4
80 #define PLLX_MISC1 0x510
81 #define PLLX_MISC2 0x514
82 #define PLLX_MISC3 0x518
83 #define PLLX_MISC4 0x5f0
84 #define PLLX_MISC5 0x5f4
85 #define PLLE_BASE 0xe8
86 #define PLLE_MISC0 0xec
87 #define PLLD2_BASE 0x4b8
88 #define PLLD2_MISC0 0x4bc
89 #define PLLD2_MISC1 0x570
90 #define PLLD2_MISC2 0x574
91 #define PLLD2_MISC3 0x578
92 #define PLLE_AUX 0x48c
93 #define PLLRE_BASE 0x4c4
94 #define PLLRE_MISC0 0x4c8
95 #define PLLRE_OUT1 0x4cc
96 #define PLLDP_BASE 0x590
97 #define PLLDP_MISC 0x594
99 #define PLLC4_BASE 0x5a4
100 #define PLLC4_MISC0 0x5a8
101 #define PLLC4_OUT 0x5e4
102 #define PLLMB_BASE 0x5e8
103 #define PLLMB_MISC1 0x5ec
104 #define PLLA1_BASE 0x6a4
105 #define PLLA1_MISC0 0x6a8
106 #define PLLA1_MISC1 0x6ac
107 #define PLLA1_MISC2 0x6b0
108 #define PLLA1_MISC3 0x6b4
110 #define PLLU_IDDQ_BIT 31
111 #define PLLCX_IDDQ_BIT 27
112 #define PLLRE_IDDQ_BIT 24
113 #define PLLA_IDDQ_BIT 25
114 #define PLLD_IDDQ_BIT 20
115 #define PLLSS_IDDQ_BIT 18
116 #define PLLM_IDDQ_BIT 5
117 #define PLLMB_IDDQ_BIT 17
118 #define PLLXP_IDDQ_BIT 3
120 #define PLLCX_RESET_BIT 30
122 #define PLL_BASE_LOCK BIT(27)
123 #define PLLCX_BASE_LOCK BIT(26)
124 #define PLLE_MISC_LOCK BIT(11)
125 #define PLLRE_MISC_LOCK BIT(27)
127 #define PLL_MISC_LOCK_ENABLE 18
128 #define PLLC_MISC_LOCK_ENABLE 24
129 #define PLLDU_MISC_LOCK_ENABLE 22
130 #define PLLU_MISC_LOCK_ENABLE 29
131 #define PLLE_MISC_LOCK_ENABLE 9
132 #define PLLRE_MISC_LOCK_ENABLE 30
133 #define PLLSS_MISC_LOCK_ENABLE 30
134 #define PLLP_MISC_LOCK_ENABLE 18
135 #define PLLM_MISC_LOCK_ENABLE 4
136 #define PLLMB_MISC_LOCK_ENABLE 16
137 #define PLLA_MISC_LOCK_ENABLE 28
138 #define PLLU_MISC_LOCK_ENABLE 29
139 #define PLLD_MISC_LOCK_ENABLE 18
141 #define PLLA_SDM_DIN_MASK 0xffff
142 #define PLLA_SDM_EN_MASK BIT(26)
144 #define PLLD_SDM_EN_MASK BIT(16)
146 #define PLLD2_SDM_EN_MASK BIT(31)
147 #define PLLD2_SSC_EN_MASK 0
149 #define PLLDP_SS_CFG 0x598
150 #define PLLDP_SDM_EN_MASK BIT(31)
151 #define PLLDP_SSC_EN_MASK BIT(30)
152 #define PLLDP_SS_CTRL1 0x59c
153 #define PLLDP_SS_CTRL2 0x5a0
155 #define PMC_PLLM_WB0_OVERRIDE 0x1dc
156 #define PMC_PLLM_WB0_OVERRIDE_2 0x2b0
158 #define UTMIP_PLL_CFG2 0x488
159 #define UTMIP_PLL_CFG2_STABLE_COUNT(x) (((x) & 0xfff) << 6)
160 #define UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(x) (((x) & 0x3f) << 18)
161 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN BIT(0)
162 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERUP BIT(1)
163 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN BIT(2)
164 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERUP BIT(3)
165 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN BIT(4)
166 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERUP BIT(5)
167 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_D_POWERDOWN BIT(24)
168 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_D_POWERUP BIT(25)
170 #define UTMIP_PLL_CFG1 0x484
171 #define UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(x) (((x) & 0x1f) << 27)
172 #define UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(x) (((x) & 0xfff) << 0)
173 #define UTMIP_PLL_CFG1_FORCE_PLLU_POWERUP BIT(17)
174 #define UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN BIT(16)
175 #define UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP BIT(15)
176 #define UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN BIT(14)
177 #define UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN BIT(12)
179 #define SATA_PLL_CFG0 0x490
180 #define SATA_PLL_CFG0_PADPLL_RESET_SWCTL BIT(0)
181 #define SATA_PLL_CFG0_PADPLL_USE_LOCKDET BIT(2)
182 #define SATA_PLL_CFG0_SATA_SEQ_IN_SWCTL BIT(4)
183 #define SATA_PLL_CFG0_SATA_SEQ_RESET_INPUT_VALUE BIT(5)
184 #define SATA_PLL_CFG0_SATA_SEQ_LANE_PD_INPUT_VALUE BIT(6)
185 #define SATA_PLL_CFG0_SATA_SEQ_PADPLL_PD_INPUT_VALUE BIT(7)
187 #define SATA_PLL_CFG0_PADPLL_SLEEP_IDDQ BIT(13)
188 #define SATA_PLL_CFG0_SEQ_ENABLE BIT(24)
190 #define XUSBIO_PLL_CFG0 0x51c
191 #define XUSBIO_PLL_CFG0_PADPLL_RESET_SWCTL BIT(0)
192 #define XUSBIO_PLL_CFG0_CLK_ENABLE_SWCTL BIT(2)
193 #define XUSBIO_PLL_CFG0_PADPLL_USE_LOCKDET BIT(6)
194 #define XUSBIO_PLL_CFG0_PADPLL_SLEEP_IDDQ BIT(13)
195 #define XUSBIO_PLL_CFG0_SEQ_ENABLE BIT(24)
197 #define UTMIPLL_HW_PWRDN_CFG0 0x52c
198 #define UTMIPLL_HW_PWRDN_CFG0_UTMIPLL_LOCK BIT(31)
199 #define UTMIPLL_HW_PWRDN_CFG0_SEQ_START_STATE BIT(25)
200 #define UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE BIT(24)
201 #define UTMIPLL_HW_PWRDN_CFG0_IDDQ_PD_INCLUDE BIT(7)
202 #define UTMIPLL_HW_PWRDN_CFG0_USE_LOCKDET BIT(6)
203 #define UTMIPLL_HW_PWRDN_CFG0_SEQ_RESET_INPUT_VALUE BIT(5)
204 #define UTMIPLL_HW_PWRDN_CFG0_SEQ_IN_SWCTL BIT(4)
205 #define UTMIPLL_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL BIT(2)
206 #define UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE BIT(1)
207 #define UTMIPLL_HW_PWRDN_CFG0_IDDQ_SWCTL BIT(0)
209 #define PLLU_HW_PWRDN_CFG0 0x530
210 #define PLLU_HW_PWRDN_CFG0_IDDQ_PD_INCLUDE BIT(28)
211 #define PLLU_HW_PWRDN_CFG0_SEQ_ENABLE BIT(24)
212 #define PLLU_HW_PWRDN_CFG0_USE_SWITCH_DETECT BIT(7)
213 #define PLLU_HW_PWRDN_CFG0_USE_LOCKDET BIT(6)
214 #define PLLU_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL BIT(2)
215 #define PLLU_HW_PWRDN_CFG0_CLK_SWITCH_SWCTL BIT(0)
217 #define XUSB_PLL_CFG0 0x534
218 #define XUSB_PLL_CFG0_UTMIPLL_LOCK_DLY 0x3ff
219 #define XUSB_PLL_CFG0_PLLU_LOCK_DLY_MASK (0x3ff << 14)
221 #define SPARE_REG0 0x55c
222 #define CLK_M_DIVISOR_SHIFT 2
223 #define CLK_M_DIVISOR_MASK 0x3
225 #define CLK_MASK_ARM 0x44
226 #define MISC_CLK_ENB 0x48
228 #define RST_DFLL_DVCO 0x2f4
229 #define DVFS_DFLL_RESET_SHIFT 0
231 #define CLK_RST_CONTROLLER_CLK_OUT_ENB_X_SET 0x284
232 #define CLK_RST_CONTROLLER_CLK_OUT_ENB_X_CLR 0x288
233 #define CLK_OUT_ENB_X_CLK_ENB_EMC_DLL BIT(14)
235 #define CLK_RST_CONTROLLER_RST_DEV_Y_SET 0x2a8
236 #define CLK_RST_CONTROLLER_RST_DEV_Y_CLR 0x2ac
237 #define CPU_SOFTRST_CTRL 0x380
239 #define LVL2_CLK_GATE_OVRA 0xf8
240 #define LVL2_CLK_GATE_OVRC 0x3a0
241 #define LVL2_CLK_GATE_OVRD 0x3a4
242 #define LVL2_CLK_GATE_OVRE 0x554
244 /* I2S registers to handle during APE MBIST WAR */
245 #define TEGRA210_I2S_BASE 0x1000
246 #define TEGRA210_I2S_SIZE 0x100
247 #define TEGRA210_I2S_CTRLS 5
248 #define TEGRA210_I2S_CG 0x88
249 #define TEGRA210_I2S_CTRL 0xa0
251 /* DISPA registers to handle during MBIST WAR */
252 #define DC_CMD_DISPLAY_COMMAND 0xc8
253 #define DC_COM_DSC_TOP_CTL 0xcf8
255 /* VIC register to handle during MBIST WAR */
256 #define NV_PVIC_THI_SLCG_OVERRIDE_LOW 0x8c
258 /* APE, DISPA and VIC base addesses needed for MBIST WAR */
259 #define TEGRA210_AHUB_BASE 0x702d0000
260 #define TEGRA210_DISPA_BASE 0x54200000
261 #define TEGRA210_VIC_BASE 0x54340000
264 * SDM fractional divisor is 16-bit 2's complement signed number within
265 * (-2^12 ... 2^12-1) range. Represented in PLL data structure as unsigned
266 * 16-bit value, with "0" divisor mapped to 0xFFFF. Data "0" is used to
267 * indicate that SDM is disabled.
269 * Effective ndiv value when SDM is enabled: ndiv + 1/2 + sdm_din/2^13
271 #define PLL_SDM_COEFF BIT(13)
272 #define sdin_din_to_data(din) ((u16)((din) ? : 0xFFFFU))
273 #define sdin_data_to_din(dat) (((dat) == 0xFFFFU) ? 0 : (s16)dat)
274 /* This macro returns ndiv effective scaled to SDM range */
275 #define sdin_get_n_eff(cfg) ((cfg)->n * PLL_SDM_COEFF + ((cfg)->sdm_data ? \
276 (PLL_SDM_COEFF/2 + sdin_data_to_din((cfg)->sdm_data)) : 0))
278 /* Tegra CPU clock and reset control regs */
279 #define CLK_RST_CONTROLLER_CPU_CMPLX_STATUS 0x470
281 #ifdef CONFIG_PM_SLEEP
282 static struct cpu_clk_suspend_context {
284 } tegra210_cpu_clk_sctx;
287 struct tegra210_domain_mbist_war {
288 void (*handle_lvl2_ovr)(struct tegra210_domain_mbist_war *mbist);
289 const u32 lvl2_offset;
291 const unsigned int num_clks;
292 const unsigned int *clk_init_data;
293 struct clk_bulk_data *clks;
296 static struct clk **clks;
298 static void __iomem *clk_base;
299 static void __iomem *pmc_base;
300 static void __iomem *ahub_base;
301 static void __iomem *dispa_base;
302 static void __iomem *vic_base;
304 static unsigned long osc_freq;
305 static unsigned long pll_ref_freq;
307 static DEFINE_SPINLOCK(pll_d_lock);
308 static DEFINE_SPINLOCK(pll_e_lock);
309 static DEFINE_SPINLOCK(pll_re_lock);
310 static DEFINE_SPINLOCK(pll_u_lock);
311 static DEFINE_SPINLOCK(sor0_lock);
312 static DEFINE_SPINLOCK(sor1_lock);
313 static DEFINE_SPINLOCK(emc_lock);
314 static DEFINE_MUTEX(lvl2_ovr_lock);
316 /* possible OSC frequencies in Hz */
317 static unsigned long tegra210_input_freq[] = {
322 #define PLL_ENABLE (1 << 30)
324 #define PLLCX_MISC1_IDDQ (1 << 27)
325 #define PLLCX_MISC0_RESET (1 << 30)
327 #define PLLCX_MISC0_DEFAULT_VALUE 0x40080000
328 #define PLLCX_MISC0_WRITE_MASK 0x400ffffb
329 #define PLLCX_MISC1_DEFAULT_VALUE 0x08000000
330 #define PLLCX_MISC1_WRITE_MASK 0x08003cff
331 #define PLLCX_MISC2_DEFAULT_VALUE 0x1f720f05
332 #define PLLCX_MISC2_WRITE_MASK 0xffffff17
333 #define PLLCX_MISC3_DEFAULT_VALUE 0x000000c4
334 #define PLLCX_MISC3_WRITE_MASK 0x00ffffff
337 #define PLLA_BASE_IDDQ (1 << 25)
338 #define PLLA_BASE_LOCK (1 << 27)
340 #define PLLA_MISC0_LOCK_ENABLE (1 << 28)
341 #define PLLA_MISC0_LOCK_OVERRIDE (1 << 27)
343 #define PLLA_MISC2_EN_SDM (1 << 26)
344 #define PLLA_MISC2_EN_DYNRAMP (1 << 25)
346 #define PLLA_MISC0_DEFAULT_VALUE 0x12000020
347 #define PLLA_MISC0_WRITE_MASK 0x7fffffff
348 #define PLLA_MISC2_DEFAULT_VALUE 0x0
349 #define PLLA_MISC2_WRITE_MASK 0x06ffffff
352 #define PLLD_BASE_CSI_CLKSOURCE (1 << 23)
354 #define PLLD_MISC0_EN_SDM (1 << 16)
355 #define PLLD_MISC0_LOCK_OVERRIDE (1 << 17)
356 #define PLLD_MISC0_LOCK_ENABLE (1 << 18)
357 #define PLLD_MISC0_IDDQ (1 << 20)
358 #define PLLD_MISC0_DSI_CLKENABLE (1 << 21)
360 #define PLLD_MISC0_DEFAULT_VALUE 0x00140000
361 #define PLLD_MISC0_WRITE_MASK 0x3ff7ffff
362 #define PLLD_MISC1_DEFAULT_VALUE 0x20
363 #define PLLD_MISC1_WRITE_MASK 0x00ffffff
365 /* PLLD2 and PLLDP and PLLC4 */
366 #define PLLDSS_BASE_LOCK (1 << 27)
367 #define PLLDSS_BASE_LOCK_OVERRIDE (1 << 24)
368 #define PLLDSS_BASE_IDDQ (1 << 18)
369 #define PLLDSS_BASE_REF_SEL_SHIFT 25
370 #define PLLDSS_BASE_REF_SEL_MASK (0x3 << PLLDSS_BASE_REF_SEL_SHIFT)
372 #define PLLDSS_MISC0_LOCK_ENABLE (1 << 30)
374 #define PLLDSS_MISC1_CFG_EN_SDM (1 << 31)
375 #define PLLDSS_MISC1_CFG_EN_SSC (1 << 30)
377 #define PLLD2_MISC0_DEFAULT_VALUE 0x40000020
378 #define PLLD2_MISC1_CFG_DEFAULT_VALUE 0x10000000
379 #define PLLD2_MISC2_CTRL1_DEFAULT_VALUE 0x0
380 #define PLLD2_MISC3_CTRL2_DEFAULT_VALUE 0x0
382 #define PLLDP_MISC0_DEFAULT_VALUE 0x40000020
383 #define PLLDP_MISC1_CFG_DEFAULT_VALUE 0xc0000000
384 #define PLLDP_MISC2_CTRL1_DEFAULT_VALUE 0xf400f0da
385 #define PLLDP_MISC3_CTRL2_DEFAULT_VALUE 0x2004f400
387 #define PLLDSS_MISC0_WRITE_MASK 0x47ffffff
388 #define PLLDSS_MISC1_CFG_WRITE_MASK 0xf8000000
389 #define PLLDSS_MISC2_CTRL1_WRITE_MASK 0xffffffff
390 #define PLLDSS_MISC3_CTRL2_WRITE_MASK 0xffffffff
392 #define PLLC4_MISC0_DEFAULT_VALUE 0x40000000
395 #define PLLRE_MISC0_LOCK_ENABLE (1 << 30)
396 #define PLLRE_MISC0_LOCK_OVERRIDE (1 << 29)
397 #define PLLRE_MISC0_LOCK (1 << 27)
398 #define PLLRE_MISC0_IDDQ (1 << 24)
400 #define PLLRE_BASE_DEFAULT_VALUE 0x0
401 #define PLLRE_MISC0_DEFAULT_VALUE 0x41000000
403 #define PLLRE_BASE_DEFAULT_MASK 0x1c000000
404 #define PLLRE_MISC0_WRITE_MASK 0x67ffffff
407 #define PLLE_MISC_IDDQ_SW_CTRL (1 << 14)
408 #define PLLE_AUX_USE_LOCKDET (1 << 3)
409 #define PLLE_AUX_SS_SEQ_INCLUDE (1 << 31)
410 #define PLLE_AUX_ENABLE_SWCTL (1 << 4)
411 #define PLLE_AUX_SS_SWCTL (1 << 6)
412 #define PLLE_AUX_SEQ_ENABLE (1 << 24)
415 #define PLLX_USE_DYN_RAMP 1
416 #define PLLX_BASE_LOCK (1 << 27)
418 #define PLLX_MISC0_FO_G_DISABLE (0x1 << 28)
419 #define PLLX_MISC0_LOCK_ENABLE (0x1 << 18)
421 #define PLLX_MISC2_DYNRAMP_STEPB_SHIFT 24
422 #define PLLX_MISC2_DYNRAMP_STEPB_MASK (0xFF << PLLX_MISC2_DYNRAMP_STEPB_SHIFT)
423 #define PLLX_MISC2_DYNRAMP_STEPA_SHIFT 16
424 #define PLLX_MISC2_DYNRAMP_STEPA_MASK (0xFF << PLLX_MISC2_DYNRAMP_STEPA_SHIFT)
425 #define PLLX_MISC2_NDIV_NEW_SHIFT 8
426 #define PLLX_MISC2_NDIV_NEW_MASK (0xFF << PLLX_MISC2_NDIV_NEW_SHIFT)
427 #define PLLX_MISC2_LOCK_OVERRIDE (0x1 << 4)
428 #define PLLX_MISC2_DYNRAMP_DONE (0x1 << 2)
429 #define PLLX_MISC2_EN_DYNRAMP (0x1 << 0)
431 #define PLLX_MISC3_IDDQ (0x1 << 3)
433 #define PLLX_MISC0_DEFAULT_VALUE PLLX_MISC0_LOCK_ENABLE
434 #define PLLX_MISC0_WRITE_MASK 0x10c40000
435 #define PLLX_MISC1_DEFAULT_VALUE 0x20
436 #define PLLX_MISC1_WRITE_MASK 0x00ffffff
437 #define PLLX_MISC2_DEFAULT_VALUE 0x0
438 #define PLLX_MISC2_WRITE_MASK 0xffffff11
439 #define PLLX_MISC3_DEFAULT_VALUE PLLX_MISC3_IDDQ
440 #define PLLX_MISC3_WRITE_MASK 0x01ff0f0f
441 #define PLLX_MISC4_DEFAULT_VALUE 0x0
442 #define PLLX_MISC4_WRITE_MASK 0x8000ffff
443 #define PLLX_MISC5_DEFAULT_VALUE 0x0
444 #define PLLX_MISC5_WRITE_MASK 0x0000ffff
446 #define PLLX_HW_CTRL_CFG 0x548
447 #define PLLX_HW_CTRL_CFG_SWCTRL (0x1 << 0)
450 #define PLLMB_BASE_LOCK (1 << 27)
452 #define PLLMB_MISC1_LOCK_OVERRIDE (1 << 18)
453 #define PLLMB_MISC1_IDDQ (1 << 17)
454 #define PLLMB_MISC1_LOCK_ENABLE (1 << 16)
456 #define PLLMB_MISC1_DEFAULT_VALUE 0x00030000
457 #define PLLMB_MISC1_WRITE_MASK 0x0007ffff
460 #define PLLP_BASE_OVERRIDE (1 << 28)
461 #define PLLP_BASE_LOCK (1 << 27)
463 #define PLLP_MISC0_LOCK_ENABLE (1 << 18)
464 #define PLLP_MISC0_LOCK_OVERRIDE (1 << 17)
465 #define PLLP_MISC0_IDDQ (1 << 3)
467 #define PLLP_MISC1_HSIO_EN_SHIFT 29
468 #define PLLP_MISC1_HSIO_EN (1 << PLLP_MISC1_HSIO_EN_SHIFT)
469 #define PLLP_MISC1_XUSB_EN_SHIFT 28
470 #define PLLP_MISC1_XUSB_EN (1 << PLLP_MISC1_XUSB_EN_SHIFT)
472 #define PLLP_MISC0_DEFAULT_VALUE 0x00040008
473 #define PLLP_MISC1_DEFAULT_VALUE 0x0
475 #define PLLP_MISC0_WRITE_MASK 0xdc6000f
476 #define PLLP_MISC1_WRITE_MASK 0x70ffffff
479 #define PLLU_BASE_LOCK (1 << 27)
480 #define PLLU_BASE_OVERRIDE (1 << 24)
481 #define PLLU_BASE_CLKENABLE_USB (1 << 21)
482 #define PLLU_BASE_CLKENABLE_HSIC (1 << 22)
483 #define PLLU_BASE_CLKENABLE_ICUSB (1 << 23)
484 #define PLLU_BASE_CLKENABLE_48M (1 << 25)
485 #define PLLU_BASE_CLKENABLE_ALL (PLLU_BASE_CLKENABLE_USB |\
486 PLLU_BASE_CLKENABLE_HSIC |\
487 PLLU_BASE_CLKENABLE_ICUSB |\
488 PLLU_BASE_CLKENABLE_48M)
490 #define PLLU_MISC0_IDDQ (1 << 31)
491 #define PLLU_MISC0_LOCK_ENABLE (1 << 29)
492 #define PLLU_MISC1_LOCK_OVERRIDE (1 << 0)
494 #define PLLU_MISC0_DEFAULT_VALUE 0xa0000000
495 #define PLLU_MISC1_DEFAULT_VALUE 0x0
497 #define PLLU_MISC0_WRITE_MASK 0xbfffffff
498 #define PLLU_MISC1_WRITE_MASK 0x00000007
500 bool tegra210_plle_hw_sequence_is_enabled(void)
504 value = readl_relaxed(clk_base + PLLE_AUX);
505 if (value & PLLE_AUX_SEQ_ENABLE)
510 EXPORT_SYMBOL_GPL(tegra210_plle_hw_sequence_is_enabled);
512 int tegra210_plle_hw_sequence_start(void)
516 if (tegra210_plle_hw_sequence_is_enabled())
519 /* skip if PLLE is not enabled yet */
520 value = readl_relaxed(clk_base + PLLE_MISC0);
521 if (!(value & PLLE_MISC_LOCK))
524 value &= ~PLLE_MISC_IDDQ_SW_CTRL;
525 writel_relaxed(value, clk_base + PLLE_MISC0);
527 value = readl_relaxed(clk_base + PLLE_AUX);
528 value |= (PLLE_AUX_USE_LOCKDET | PLLE_AUX_SS_SEQ_INCLUDE);
529 value &= ~(PLLE_AUX_ENABLE_SWCTL | PLLE_AUX_SS_SWCTL);
530 writel_relaxed(value, clk_base + PLLE_AUX);
532 fence_udelay(1, clk_base);
534 value |= PLLE_AUX_SEQ_ENABLE;
535 writel_relaxed(value, clk_base + PLLE_AUX);
537 fence_udelay(1, clk_base);
541 EXPORT_SYMBOL_GPL(tegra210_plle_hw_sequence_start);
543 void tegra210_xusb_pll_hw_control_enable(void)
547 val = readl_relaxed(clk_base + XUSBIO_PLL_CFG0);
548 val &= ~(XUSBIO_PLL_CFG0_CLK_ENABLE_SWCTL |
549 XUSBIO_PLL_CFG0_PADPLL_RESET_SWCTL);
550 val |= XUSBIO_PLL_CFG0_PADPLL_USE_LOCKDET |
551 XUSBIO_PLL_CFG0_PADPLL_SLEEP_IDDQ;
552 writel_relaxed(val, clk_base + XUSBIO_PLL_CFG0);
554 EXPORT_SYMBOL_GPL(tegra210_xusb_pll_hw_control_enable);
556 void tegra210_xusb_pll_hw_sequence_start(void)
560 val = readl_relaxed(clk_base + XUSBIO_PLL_CFG0);
561 val |= XUSBIO_PLL_CFG0_SEQ_ENABLE;
562 writel_relaxed(val, clk_base + XUSBIO_PLL_CFG0);
564 EXPORT_SYMBOL_GPL(tegra210_xusb_pll_hw_sequence_start);
566 void tegra210_sata_pll_hw_control_enable(void)
570 val = readl_relaxed(clk_base + SATA_PLL_CFG0);
571 val &= ~SATA_PLL_CFG0_PADPLL_RESET_SWCTL;
572 val |= SATA_PLL_CFG0_PADPLL_USE_LOCKDET |
573 SATA_PLL_CFG0_PADPLL_SLEEP_IDDQ;
574 writel_relaxed(val, clk_base + SATA_PLL_CFG0);
576 EXPORT_SYMBOL_GPL(tegra210_sata_pll_hw_control_enable);
578 void tegra210_sata_pll_hw_sequence_start(void)
582 val = readl_relaxed(clk_base + SATA_PLL_CFG0);
583 val |= SATA_PLL_CFG0_SEQ_ENABLE;
584 writel_relaxed(val, clk_base + SATA_PLL_CFG0);
586 EXPORT_SYMBOL_GPL(tegra210_sata_pll_hw_sequence_start);
588 void tegra210_set_sata_pll_seq_sw(bool state)
592 val = readl_relaxed(clk_base + SATA_PLL_CFG0);
594 val |= SATA_PLL_CFG0_SATA_SEQ_IN_SWCTL;
595 val |= SATA_PLL_CFG0_SATA_SEQ_RESET_INPUT_VALUE;
596 val |= SATA_PLL_CFG0_SATA_SEQ_LANE_PD_INPUT_VALUE;
597 val |= SATA_PLL_CFG0_SATA_SEQ_PADPLL_PD_INPUT_VALUE;
599 val &= ~SATA_PLL_CFG0_SATA_SEQ_IN_SWCTL;
600 val &= ~SATA_PLL_CFG0_SATA_SEQ_RESET_INPUT_VALUE;
601 val &= ~SATA_PLL_CFG0_SATA_SEQ_LANE_PD_INPUT_VALUE;
602 val &= ~SATA_PLL_CFG0_SATA_SEQ_PADPLL_PD_INPUT_VALUE;
604 writel_relaxed(val, clk_base + SATA_PLL_CFG0);
606 EXPORT_SYMBOL_GPL(tegra210_set_sata_pll_seq_sw);
608 void tegra210_clk_emc_dll_enable(bool flag)
610 u32 offset = flag ? CLK_RST_CONTROLLER_CLK_OUT_ENB_X_SET :
611 CLK_RST_CONTROLLER_CLK_OUT_ENB_X_CLR;
613 writel_relaxed(CLK_OUT_ENB_X_CLK_ENB_EMC_DLL, clk_base + offset);
615 EXPORT_SYMBOL_GPL(tegra210_clk_emc_dll_enable);
617 void tegra210_clk_emc_dll_update_setting(u32 emc_dll_src_value)
619 writel_relaxed(emc_dll_src_value, clk_base + CLK_SOURCE_EMC_DLL);
621 EXPORT_SYMBOL_GPL(tegra210_clk_emc_dll_update_setting);
623 void tegra210_clk_emc_update_setting(u32 emc_src_value)
625 writel_relaxed(emc_src_value, clk_base + CLK_SOURCE_EMC);
627 EXPORT_SYMBOL_GPL(tegra210_clk_emc_update_setting);
629 static void tegra210_generic_mbist_war(struct tegra210_domain_mbist_war *mbist)
633 val = readl_relaxed(clk_base + mbist->lvl2_offset);
634 writel_relaxed(val | mbist->lvl2_mask, clk_base + mbist->lvl2_offset);
635 fence_udelay(1, clk_base);
636 writel_relaxed(val, clk_base + mbist->lvl2_offset);
637 fence_udelay(1, clk_base);
640 static void tegra210_venc_mbist_war(struct tegra210_domain_mbist_war *mbist)
642 u32 csi_src, ovra, ovre;
643 unsigned long flags = 0;
645 spin_lock_irqsave(&pll_d_lock, flags);
647 csi_src = readl_relaxed(clk_base + PLLD_BASE);
648 writel_relaxed(csi_src | PLLD_BASE_CSI_CLKSOURCE, clk_base + PLLD_BASE);
649 fence_udelay(1, clk_base);
651 ovra = readl_relaxed(clk_base + LVL2_CLK_GATE_OVRA);
652 writel_relaxed(ovra | BIT(15), clk_base + LVL2_CLK_GATE_OVRA);
653 ovre = readl_relaxed(clk_base + LVL2_CLK_GATE_OVRE);
654 writel_relaxed(ovre | BIT(3), clk_base + LVL2_CLK_GATE_OVRE);
655 fence_udelay(1, clk_base);
657 writel_relaxed(ovra, clk_base + LVL2_CLK_GATE_OVRA);
658 writel_relaxed(ovre, clk_base + LVL2_CLK_GATE_OVRE);
659 writel_relaxed(csi_src, clk_base + PLLD_BASE);
660 fence_udelay(1, clk_base);
662 spin_unlock_irqrestore(&pll_d_lock, flags);
665 static void tegra210_disp_mbist_war(struct tegra210_domain_mbist_war *mbist)
667 u32 ovra, dsc_top_ctrl;
669 ovra = readl_relaxed(clk_base + LVL2_CLK_GATE_OVRA);
670 writel_relaxed(ovra | BIT(1), clk_base + LVL2_CLK_GATE_OVRA);
671 fence_udelay(1, clk_base);
673 dsc_top_ctrl = readl_relaxed(dispa_base + DC_COM_DSC_TOP_CTL);
674 writel_relaxed(dsc_top_ctrl | BIT(2), dispa_base + DC_COM_DSC_TOP_CTL);
675 readl_relaxed(dispa_base + DC_CMD_DISPLAY_COMMAND);
676 writel_relaxed(dsc_top_ctrl, dispa_base + DC_COM_DSC_TOP_CTL);
677 readl_relaxed(dispa_base + DC_CMD_DISPLAY_COMMAND);
679 writel_relaxed(ovra, clk_base + LVL2_CLK_GATE_OVRA);
680 fence_udelay(1, clk_base);
683 static void tegra210_vic_mbist_war(struct tegra210_domain_mbist_war *mbist)
687 ovre = readl_relaxed(clk_base + LVL2_CLK_GATE_OVRE);
688 writel_relaxed(ovre | BIT(5), clk_base + LVL2_CLK_GATE_OVRE);
689 fence_udelay(1, clk_base);
691 val = readl_relaxed(vic_base + NV_PVIC_THI_SLCG_OVERRIDE_LOW);
692 writel_relaxed(val | BIT(0) | GENMASK(7, 2) | BIT(24),
693 vic_base + NV_PVIC_THI_SLCG_OVERRIDE_LOW);
694 fence_udelay(1, vic_base + NV_PVIC_THI_SLCG_OVERRIDE_LOW);
696 writel_relaxed(val, vic_base + NV_PVIC_THI_SLCG_OVERRIDE_LOW);
697 readl(vic_base + NV_PVIC_THI_SLCG_OVERRIDE_LOW);
699 writel_relaxed(ovre, clk_base + LVL2_CLK_GATE_OVRE);
700 fence_udelay(1, clk_base);
703 static void tegra210_ape_mbist_war(struct tegra210_domain_mbist_war *mbist)
705 void __iomem *i2s_base;
709 ovrc = readl_relaxed(clk_base + LVL2_CLK_GATE_OVRC);
710 ovre = readl_relaxed(clk_base + LVL2_CLK_GATE_OVRE);
711 writel_relaxed(ovrc | BIT(1), clk_base + LVL2_CLK_GATE_OVRC);
712 writel_relaxed(ovre | BIT(10) | BIT(11),
713 clk_base + LVL2_CLK_GATE_OVRE);
714 fence_udelay(1, clk_base);
716 i2s_base = ahub_base + TEGRA210_I2S_BASE;
718 for (i = 0; i < TEGRA210_I2S_CTRLS; i++) {
721 i2s_ctrl = readl_relaxed(i2s_base + TEGRA210_I2S_CTRL);
722 writel_relaxed(i2s_ctrl | BIT(10),
723 i2s_base + TEGRA210_I2S_CTRL);
724 writel_relaxed(0, i2s_base + TEGRA210_I2S_CG);
725 readl(i2s_base + TEGRA210_I2S_CG);
726 writel_relaxed(1, i2s_base + TEGRA210_I2S_CG);
727 writel_relaxed(i2s_ctrl, i2s_base + TEGRA210_I2S_CTRL);
728 readl(i2s_base + TEGRA210_I2S_CTRL);
730 i2s_base += TEGRA210_I2S_SIZE;
733 writel_relaxed(ovrc, clk_base + LVL2_CLK_GATE_OVRC);
734 writel_relaxed(ovre, clk_base + LVL2_CLK_GATE_OVRE);
735 fence_udelay(1, clk_base);
738 static inline void _pll_misc_chk_default(void __iomem *base,
739 struct tegra_clk_pll_params *params,
740 u8 misc_num, u32 default_val, u32 mask)
742 u32 boot_val = readl_relaxed(base + params->ext_misc_reg[misc_num]);
746 if (boot_val != default_val) {
747 pr_warn("boot misc%d 0x%x: expected 0x%x\n",
748 misc_num, boot_val, default_val);
749 pr_warn(" (comparison mask = 0x%x)\n", mask);
750 params->defaults_set = false;
755 * PLLCX: PLLC, PLLC2, PLLC3, PLLA1
756 * Hybrid PLLs with dynamic ramp. Dynamic ramp is allowed for any transition
757 * that changes NDIV only, while PLL is already locked.
759 static void pllcx_check_defaults(struct tegra_clk_pll_params *params)
763 default_val = PLLCX_MISC0_DEFAULT_VALUE & (~PLLCX_MISC0_RESET);
764 _pll_misc_chk_default(clk_base, params, 0, default_val,
765 PLLCX_MISC0_WRITE_MASK);
767 default_val = PLLCX_MISC1_DEFAULT_VALUE & (~PLLCX_MISC1_IDDQ);
768 _pll_misc_chk_default(clk_base, params, 1, default_val,
769 PLLCX_MISC1_WRITE_MASK);
771 default_val = PLLCX_MISC2_DEFAULT_VALUE;
772 _pll_misc_chk_default(clk_base, params, 2, default_val,
773 PLLCX_MISC2_WRITE_MASK);
775 default_val = PLLCX_MISC3_DEFAULT_VALUE;
776 _pll_misc_chk_default(clk_base, params, 3, default_val,
777 PLLCX_MISC3_WRITE_MASK);
780 static void tegra210_pllcx_set_defaults(const char *name,
781 struct tegra_clk_pll *pllcx)
783 pllcx->params->defaults_set = true;
785 if (readl_relaxed(clk_base + pllcx->params->base_reg) & PLL_ENABLE) {
786 /* PLL is ON: only check if defaults already set */
787 pllcx_check_defaults(pllcx->params);
788 if (!pllcx->params->defaults_set)
789 pr_warn("%s already enabled. Postponing set full defaults\n",
794 /* Defaults assert PLL reset, and set IDDQ */
795 writel_relaxed(PLLCX_MISC0_DEFAULT_VALUE,
796 clk_base + pllcx->params->ext_misc_reg[0]);
797 writel_relaxed(PLLCX_MISC1_DEFAULT_VALUE,
798 clk_base + pllcx->params->ext_misc_reg[1]);
799 writel_relaxed(PLLCX_MISC2_DEFAULT_VALUE,
800 clk_base + pllcx->params->ext_misc_reg[2]);
801 writel_relaxed(PLLCX_MISC3_DEFAULT_VALUE,
802 clk_base + pllcx->params->ext_misc_reg[3]);
806 static void _pllc_set_defaults(struct tegra_clk_pll *pllcx)
808 tegra210_pllcx_set_defaults("PLL_C", pllcx);
811 static void _pllc2_set_defaults(struct tegra_clk_pll *pllcx)
813 tegra210_pllcx_set_defaults("PLL_C2", pllcx);
816 static void _pllc3_set_defaults(struct tegra_clk_pll *pllcx)
818 tegra210_pllcx_set_defaults("PLL_C3", pllcx);
821 static void _plla1_set_defaults(struct tegra_clk_pll *pllcx)
823 tegra210_pllcx_set_defaults("PLL_A1", pllcx);
828 * PLL with dynamic ramp and fractional SDM. Dynamic ramp is not used.
829 * Fractional SDM is allowed to provide exact audio rates.
831 static void tegra210_plla_set_defaults(struct tegra_clk_pll *plla)
834 u32 val = readl_relaxed(clk_base + plla->params->base_reg);
836 plla->params->defaults_set = true;
838 if (val & PLL_ENABLE) {
840 * PLL is ON: check if defaults already set, then set those
841 * that can be updated in flight.
843 if (val & PLLA_BASE_IDDQ) {
844 pr_warn("PLL_A boot enabled with IDDQ set\n");
845 plla->params->defaults_set = false;
848 pr_warn("PLL_A already enabled. Postponing set full defaults\n");
850 val = PLLA_MISC0_DEFAULT_VALUE; /* ignore lock enable */
851 mask = PLLA_MISC0_LOCK_ENABLE | PLLA_MISC0_LOCK_OVERRIDE;
852 _pll_misc_chk_default(clk_base, plla->params, 0, val,
853 ~mask & PLLA_MISC0_WRITE_MASK);
855 val = PLLA_MISC2_DEFAULT_VALUE; /* ignore all but control bit */
856 _pll_misc_chk_default(clk_base, plla->params, 2, val,
857 PLLA_MISC2_EN_DYNRAMP);
859 /* Enable lock detect */
860 val = readl_relaxed(clk_base + plla->params->ext_misc_reg[0]);
862 val |= PLLA_MISC0_DEFAULT_VALUE & mask;
863 writel_relaxed(val, clk_base + plla->params->ext_misc_reg[0]);
869 /* set IDDQ, enable lock detect, disable dynamic ramp and SDM */
870 val |= PLLA_BASE_IDDQ;
871 writel_relaxed(val, clk_base + plla->params->base_reg);
872 writel_relaxed(PLLA_MISC0_DEFAULT_VALUE,
873 clk_base + plla->params->ext_misc_reg[0]);
874 writel_relaxed(PLLA_MISC2_DEFAULT_VALUE,
875 clk_base + plla->params->ext_misc_reg[2]);
881 * PLL with fractional SDM.
883 static void tegra210_plld_set_defaults(struct tegra_clk_pll *plld)
888 plld->params->defaults_set = true;
890 if (readl_relaxed(clk_base + plld->params->base_reg) &
894 * PLL is ON: check if defaults already set, then set those
895 * that can be updated in flight.
897 val = PLLD_MISC1_DEFAULT_VALUE;
898 _pll_misc_chk_default(clk_base, plld->params, 1,
899 val, PLLD_MISC1_WRITE_MASK);
901 /* ignore lock, DSI and SDM controls, make sure IDDQ not set */
902 val = PLLD_MISC0_DEFAULT_VALUE & (~PLLD_MISC0_IDDQ);
903 mask |= PLLD_MISC0_DSI_CLKENABLE | PLLD_MISC0_LOCK_ENABLE |
904 PLLD_MISC0_LOCK_OVERRIDE | PLLD_MISC0_EN_SDM;
905 _pll_misc_chk_default(clk_base, plld->params, 0, val,
906 ~mask & PLLD_MISC0_WRITE_MASK);
908 if (!plld->params->defaults_set)
909 pr_warn("PLL_D already enabled. Postponing set full defaults\n");
911 /* Enable lock detect */
912 mask = PLLD_MISC0_LOCK_ENABLE | PLLD_MISC0_LOCK_OVERRIDE;
913 val = readl_relaxed(clk_base + plld->params->ext_misc_reg[0]);
915 val |= PLLD_MISC0_DEFAULT_VALUE & mask;
916 writel_relaxed(val, clk_base + plld->params->ext_misc_reg[0]);
922 val = readl_relaxed(clk_base + plld->params->ext_misc_reg[0]);
923 val &= PLLD_MISC0_DSI_CLKENABLE;
924 val |= PLLD_MISC0_DEFAULT_VALUE;
925 /* set IDDQ, enable lock detect, disable SDM */
926 writel_relaxed(val, clk_base + plld->params->ext_misc_reg[0]);
927 writel_relaxed(PLLD_MISC1_DEFAULT_VALUE, clk_base +
928 plld->params->ext_misc_reg[1]);
934 * PLL with fractional SDM and Spread Spectrum (SDM is a must if SSC is used).
936 static void plldss_defaults(const char *pll_name, struct tegra_clk_pll *plldss,
937 u32 misc0_val, u32 misc1_val, u32 misc2_val, u32 misc3_val)
940 u32 val = readl_relaxed(clk_base + plldss->params->base_reg);
942 plldss->params->defaults_set = true;
944 if (val & PLL_ENABLE) {
947 * PLL is ON: check if defaults already set, then set those
948 * that can be updated in flight.
950 if (val & PLLDSS_BASE_IDDQ) {
951 pr_warn("plldss boot enabled with IDDQ set\n");
952 plldss->params->defaults_set = false;
955 /* ignore lock enable */
956 default_val = misc0_val;
957 _pll_misc_chk_default(clk_base, plldss->params, 0, default_val,
958 PLLDSS_MISC0_WRITE_MASK &
959 (~PLLDSS_MISC0_LOCK_ENABLE));
962 * If SSC is used, check all settings, otherwise just confirm
963 * that SSC is not used on boot as well. Do nothing when using
964 * this function for PLLC4 that has only MISC0.
966 if (plldss->params->ssc_ctrl_en_mask) {
967 default_val = misc1_val;
968 _pll_misc_chk_default(clk_base, plldss->params, 1,
969 default_val, PLLDSS_MISC1_CFG_WRITE_MASK);
970 default_val = misc2_val;
971 _pll_misc_chk_default(clk_base, plldss->params, 2,
972 default_val, PLLDSS_MISC2_CTRL1_WRITE_MASK);
973 default_val = misc3_val;
974 _pll_misc_chk_default(clk_base, plldss->params, 3,
975 default_val, PLLDSS_MISC3_CTRL2_WRITE_MASK);
976 } else if (plldss->params->ext_misc_reg[1]) {
977 default_val = misc1_val;
978 _pll_misc_chk_default(clk_base, plldss->params, 1,
979 default_val, PLLDSS_MISC1_CFG_WRITE_MASK &
980 (~PLLDSS_MISC1_CFG_EN_SDM));
983 if (!plldss->params->defaults_set)
984 pr_warn("%s already enabled. Postponing set full defaults\n",
987 /* Enable lock detect */
988 if (val & PLLDSS_BASE_LOCK_OVERRIDE) {
989 val &= ~PLLDSS_BASE_LOCK_OVERRIDE;
990 writel_relaxed(val, clk_base +
991 plldss->params->base_reg);
994 val = readl_relaxed(clk_base + plldss->params->ext_misc_reg[0]);
995 val &= ~PLLDSS_MISC0_LOCK_ENABLE;
996 val |= misc0_val & PLLDSS_MISC0_LOCK_ENABLE;
997 writel_relaxed(val, clk_base + plldss->params->ext_misc_reg[0]);
1003 /* set IDDQ, enable lock detect, configure SDM/SSC */
1004 val |= PLLDSS_BASE_IDDQ;
1005 val &= ~PLLDSS_BASE_LOCK_OVERRIDE;
1006 writel_relaxed(val, clk_base + plldss->params->base_reg);
1008 /* When using this function for PLLC4 exit here */
1009 if (!plldss->params->ext_misc_reg[1]) {
1010 writel_relaxed(misc0_val, clk_base +
1011 plldss->params->ext_misc_reg[0]);
1016 writel_relaxed(misc0_val, clk_base +
1017 plldss->params->ext_misc_reg[0]);
1018 /* if SSC used set by 1st enable */
1019 writel_relaxed(misc1_val & (~PLLDSS_MISC1_CFG_EN_SSC),
1020 clk_base + plldss->params->ext_misc_reg[1]);
1021 writel_relaxed(misc2_val, clk_base + plldss->params->ext_misc_reg[2]);
1022 writel_relaxed(misc3_val, clk_base + plldss->params->ext_misc_reg[3]);
1026 static void tegra210_plld2_set_defaults(struct tegra_clk_pll *plld2)
1028 plldss_defaults("PLL_D2", plld2, PLLD2_MISC0_DEFAULT_VALUE,
1029 PLLD2_MISC1_CFG_DEFAULT_VALUE,
1030 PLLD2_MISC2_CTRL1_DEFAULT_VALUE,
1031 PLLD2_MISC3_CTRL2_DEFAULT_VALUE);
1034 static void tegra210_plldp_set_defaults(struct tegra_clk_pll *plldp)
1036 plldss_defaults("PLL_DP", plldp, PLLDP_MISC0_DEFAULT_VALUE,
1037 PLLDP_MISC1_CFG_DEFAULT_VALUE,
1038 PLLDP_MISC2_CTRL1_DEFAULT_VALUE,
1039 PLLDP_MISC3_CTRL2_DEFAULT_VALUE);
1044 * Base and misc0 layout is the same as PLLD2/PLLDP, but no SDM/SSC support.
1045 * VCO is exposed to the clock tree via fixed 1/3 and 1/5 dividers.
1047 static void tegra210_pllc4_set_defaults(struct tegra_clk_pll *pllc4)
1049 plldss_defaults("PLL_C4", pllc4, PLLC4_MISC0_DEFAULT_VALUE, 0, 0, 0);
1054 * VCO is exposed to the clock tree directly along with post-divider output
1056 static void tegra210_pllre_set_defaults(struct tegra_clk_pll *pllre)
1059 u32 val = readl_relaxed(clk_base + pllre->params->base_reg);
1061 pllre->params->defaults_set = true;
1063 if (val & PLL_ENABLE) {
1065 * PLL is ON: check if defaults already set, then set those
1066 * that can be updated in flight.
1068 val &= PLLRE_BASE_DEFAULT_MASK;
1069 if (val != PLLRE_BASE_DEFAULT_VALUE) {
1070 pr_warn("pllre boot base 0x%x : expected 0x%x\n",
1071 val, PLLRE_BASE_DEFAULT_VALUE);
1072 pr_warn("(comparison mask = 0x%x)\n",
1073 PLLRE_BASE_DEFAULT_MASK);
1074 pllre->params->defaults_set = false;
1077 /* Ignore lock enable */
1078 val = PLLRE_MISC0_DEFAULT_VALUE & (~PLLRE_MISC0_IDDQ);
1079 mask = PLLRE_MISC0_LOCK_ENABLE | PLLRE_MISC0_LOCK_OVERRIDE;
1080 _pll_misc_chk_default(clk_base, pllre->params, 0, val,
1081 ~mask & PLLRE_MISC0_WRITE_MASK);
1083 /* The PLL doesn't work if it's in IDDQ. */
1084 val = readl_relaxed(clk_base + pllre->params->ext_misc_reg[0]);
1085 if (val & PLLRE_MISC0_IDDQ)
1086 pr_warn("unexpected IDDQ bit set for enabled clock\n");
1088 /* Enable lock detect */
1090 val |= PLLRE_MISC0_DEFAULT_VALUE & mask;
1091 writel_relaxed(val, clk_base + pllre->params->ext_misc_reg[0]);
1094 if (!pllre->params->defaults_set)
1095 pr_warn("PLL_RE already enabled. Postponing set full defaults\n");
1100 /* set IDDQ, enable lock detect */
1101 val &= ~PLLRE_BASE_DEFAULT_MASK;
1102 val |= PLLRE_BASE_DEFAULT_VALUE & PLLRE_BASE_DEFAULT_MASK;
1103 writel_relaxed(val, clk_base + pllre->params->base_reg);
1104 writel_relaxed(PLLRE_MISC0_DEFAULT_VALUE,
1105 clk_base + pllre->params->ext_misc_reg[0]);
1109 static void pllx_get_dyn_steps(struct clk_hw *hw, u32 *step_a, u32 *step_b)
1111 unsigned long input_rate;
1114 if (!IS_ERR_OR_NULL(hw->clk))
1115 input_rate = clk_hw_get_rate(clk_hw_get_parent(hw));
1117 input_rate = 38400000;
1119 input_rate /= tegra_pll_get_fixed_mdiv(hw, input_rate);
1121 switch (input_rate) {
1137 pr_err("%s: Unexpected reference rate %lu\n",
1138 __func__, input_rate);
1143 static void pllx_check_defaults(struct tegra_clk_pll *pll)
1147 default_val = PLLX_MISC0_DEFAULT_VALUE;
1148 /* ignore lock enable */
1149 _pll_misc_chk_default(clk_base, pll->params, 0, default_val,
1150 PLLX_MISC0_WRITE_MASK & (~PLLX_MISC0_LOCK_ENABLE));
1152 default_val = PLLX_MISC1_DEFAULT_VALUE;
1153 _pll_misc_chk_default(clk_base, pll->params, 1, default_val,
1154 PLLX_MISC1_WRITE_MASK);
1156 /* ignore all but control bit */
1157 default_val = PLLX_MISC2_DEFAULT_VALUE;
1158 _pll_misc_chk_default(clk_base, pll->params, 2,
1159 default_val, PLLX_MISC2_EN_DYNRAMP);
1161 default_val = PLLX_MISC3_DEFAULT_VALUE & (~PLLX_MISC3_IDDQ);
1162 _pll_misc_chk_default(clk_base, pll->params, 3, default_val,
1163 PLLX_MISC3_WRITE_MASK);
1165 default_val = PLLX_MISC4_DEFAULT_VALUE;
1166 _pll_misc_chk_default(clk_base, pll->params, 4, default_val,
1167 PLLX_MISC4_WRITE_MASK);
1169 default_val = PLLX_MISC5_DEFAULT_VALUE;
1170 _pll_misc_chk_default(clk_base, pll->params, 5, default_val,
1171 PLLX_MISC5_WRITE_MASK);
1174 static void tegra210_pllx_set_defaults(struct tegra_clk_pll *pllx)
1179 pllx->params->defaults_set = true;
1181 /* Get ready dyn ramp state machine settings */
1182 pllx_get_dyn_steps(&pllx->hw, &step_a, &step_b);
1183 val = PLLX_MISC2_DEFAULT_VALUE & (~PLLX_MISC2_DYNRAMP_STEPA_MASK) &
1184 (~PLLX_MISC2_DYNRAMP_STEPB_MASK);
1185 val |= step_a << PLLX_MISC2_DYNRAMP_STEPA_SHIFT;
1186 val |= step_b << PLLX_MISC2_DYNRAMP_STEPB_SHIFT;
1188 if (readl_relaxed(clk_base + pllx->params->base_reg) & PLL_ENABLE) {
1191 * PLL is ON: check if defaults already set, then set those
1192 * that can be updated in flight.
1194 pllx_check_defaults(pllx);
1196 if (!pllx->params->defaults_set)
1197 pr_warn("PLL_X already enabled. Postponing set full defaults\n");
1198 /* Configure dyn ramp, disable lock override */
1199 writel_relaxed(val, clk_base + pllx->params->ext_misc_reg[2]);
1201 /* Enable lock detect */
1202 val = readl_relaxed(clk_base + pllx->params->ext_misc_reg[0]);
1203 val &= ~PLLX_MISC0_LOCK_ENABLE;
1204 val |= PLLX_MISC0_DEFAULT_VALUE & PLLX_MISC0_LOCK_ENABLE;
1205 writel_relaxed(val, clk_base + pllx->params->ext_misc_reg[0]);
1211 /* Enable lock detect and CPU output */
1212 writel_relaxed(PLLX_MISC0_DEFAULT_VALUE, clk_base +
1213 pllx->params->ext_misc_reg[0]);
1216 writel_relaxed(PLLX_MISC1_DEFAULT_VALUE, clk_base +
1217 pllx->params->ext_misc_reg[1]);
1219 /* Configure dyn ramp state machine, disable lock override */
1220 writel_relaxed(val, clk_base + pllx->params->ext_misc_reg[2]);
1223 writel_relaxed(PLLX_MISC3_DEFAULT_VALUE, clk_base +
1224 pllx->params->ext_misc_reg[3]);
1227 writel_relaxed(PLLX_MISC4_DEFAULT_VALUE, clk_base +
1228 pllx->params->ext_misc_reg[4]);
1229 writel_relaxed(PLLX_MISC5_DEFAULT_VALUE, clk_base +
1230 pllx->params->ext_misc_reg[5]);
1235 static void tegra210_pllmb_set_defaults(struct tegra_clk_pll *pllmb)
1237 u32 mask, val = readl_relaxed(clk_base + pllmb->params->base_reg);
1239 pllmb->params->defaults_set = true;
1241 if (val & PLL_ENABLE) {
1244 * PLL is ON: check if defaults already set, then set those
1245 * that can be updated in flight.
1247 val = PLLMB_MISC1_DEFAULT_VALUE & (~PLLMB_MISC1_IDDQ);
1248 mask = PLLMB_MISC1_LOCK_ENABLE | PLLMB_MISC1_LOCK_OVERRIDE;
1249 _pll_misc_chk_default(clk_base, pllmb->params, 0, val,
1250 ~mask & PLLMB_MISC1_WRITE_MASK);
1252 if (!pllmb->params->defaults_set)
1253 pr_warn("PLL_MB already enabled. Postponing set full defaults\n");
1254 /* Enable lock detect */
1255 val = readl_relaxed(clk_base + pllmb->params->ext_misc_reg[0]);
1257 val |= PLLMB_MISC1_DEFAULT_VALUE & mask;
1258 writel_relaxed(val, clk_base + pllmb->params->ext_misc_reg[0]);
1264 /* set IDDQ, enable lock detect */
1265 writel_relaxed(PLLMB_MISC1_DEFAULT_VALUE,
1266 clk_base + pllmb->params->ext_misc_reg[0]);
1272 * VCO is exposed to the clock tree directly along with post-divider output.
1273 * Both VCO and post-divider output rates are fixed at 408MHz and 204MHz,
1276 static void pllp_check_defaults(struct tegra_clk_pll *pll, bool enabled)
1280 /* Ignore lock enable (will be set), make sure not in IDDQ if enabled */
1281 val = PLLP_MISC0_DEFAULT_VALUE & (~PLLP_MISC0_IDDQ);
1282 mask = PLLP_MISC0_LOCK_ENABLE | PLLP_MISC0_LOCK_OVERRIDE;
1284 mask |= PLLP_MISC0_IDDQ;
1285 _pll_misc_chk_default(clk_base, pll->params, 0, val,
1286 ~mask & PLLP_MISC0_WRITE_MASK);
1288 /* Ignore branch controls */
1289 val = PLLP_MISC1_DEFAULT_VALUE;
1290 mask = PLLP_MISC1_HSIO_EN | PLLP_MISC1_XUSB_EN;
1291 _pll_misc_chk_default(clk_base, pll->params, 1, val,
1292 ~mask & PLLP_MISC1_WRITE_MASK);
1295 static void tegra210_pllp_set_defaults(struct tegra_clk_pll *pllp)
1298 u32 val = readl_relaxed(clk_base + pllp->params->base_reg);
1300 pllp->params->defaults_set = true;
1302 if (val & PLL_ENABLE) {
1305 * PLL is ON: check if defaults already set, then set those
1306 * that can be updated in flight.
1308 pllp_check_defaults(pllp, true);
1309 if (!pllp->params->defaults_set)
1310 pr_warn("PLL_P already enabled. Postponing set full defaults\n");
1312 /* Enable lock detect */
1313 val = readl_relaxed(clk_base + pllp->params->ext_misc_reg[0]);
1314 mask = PLLP_MISC0_LOCK_ENABLE | PLLP_MISC0_LOCK_OVERRIDE;
1316 val |= PLLP_MISC0_DEFAULT_VALUE & mask;
1317 writel_relaxed(val, clk_base + pllp->params->ext_misc_reg[0]);
1323 /* set IDDQ, enable lock detect */
1324 writel_relaxed(PLLP_MISC0_DEFAULT_VALUE,
1325 clk_base + pllp->params->ext_misc_reg[0]);
1327 /* Preserve branch control */
1328 val = readl_relaxed(clk_base + pllp->params->ext_misc_reg[1]);
1329 mask = PLLP_MISC1_HSIO_EN | PLLP_MISC1_XUSB_EN;
1331 val |= ~mask & PLLP_MISC1_DEFAULT_VALUE;
1332 writel_relaxed(val, clk_base + pllp->params->ext_misc_reg[1]);
1338 * VCO is exposed to the clock tree directly along with post-divider output.
1339 * Both VCO and post-divider output rates are fixed at 480MHz and 240MHz,
1342 static void pllu_check_defaults(struct tegra_clk_pll_params *params,
1347 /* Ignore lock enable (will be set) and IDDQ if under h/w control */
1348 val = PLLU_MISC0_DEFAULT_VALUE & (~PLLU_MISC0_IDDQ);
1349 mask = PLLU_MISC0_LOCK_ENABLE | (hw_control ? PLLU_MISC0_IDDQ : 0);
1350 _pll_misc_chk_default(clk_base, params, 0, val,
1351 ~mask & PLLU_MISC0_WRITE_MASK);
1353 val = PLLU_MISC1_DEFAULT_VALUE;
1354 mask = PLLU_MISC1_LOCK_OVERRIDE;
1355 _pll_misc_chk_default(clk_base, params, 1, val,
1356 ~mask & PLLU_MISC1_WRITE_MASK);
1359 static void tegra210_pllu_set_defaults(struct tegra_clk_pll_params *pllu)
1361 u32 val = readl_relaxed(clk_base + pllu->base_reg);
1363 pllu->defaults_set = true;
1365 if (val & PLL_ENABLE) {
1368 * PLL is ON: check if defaults already set, then set those
1369 * that can be updated in flight.
1371 pllu_check_defaults(pllu, false);
1372 if (!pllu->defaults_set)
1373 pr_warn("PLL_U already enabled. Postponing set full defaults\n");
1375 /* Enable lock detect */
1376 val = readl_relaxed(clk_base + pllu->ext_misc_reg[0]);
1377 val &= ~PLLU_MISC0_LOCK_ENABLE;
1378 val |= PLLU_MISC0_DEFAULT_VALUE & PLLU_MISC0_LOCK_ENABLE;
1379 writel_relaxed(val, clk_base + pllu->ext_misc_reg[0]);
1381 val = readl_relaxed(clk_base + pllu->ext_misc_reg[1]);
1382 val &= ~PLLU_MISC1_LOCK_OVERRIDE;
1383 val |= PLLU_MISC1_DEFAULT_VALUE & PLLU_MISC1_LOCK_OVERRIDE;
1384 writel_relaxed(val, clk_base + pllu->ext_misc_reg[1]);
1390 /* set IDDQ, enable lock detect */
1391 writel_relaxed(PLLU_MISC0_DEFAULT_VALUE,
1392 clk_base + pllu->ext_misc_reg[0]);
1393 writel_relaxed(PLLU_MISC1_DEFAULT_VALUE,
1394 clk_base + pllu->ext_misc_reg[1]);
1398 #define mask(w) ((1 << (w)) - 1)
1399 #define divm_mask(p) mask(p->params->div_nmp->divm_width)
1400 #define divn_mask(p) mask(p->params->div_nmp->divn_width)
1401 #define divp_mask(p) (p->params->flags & TEGRA_PLLU ? PLLU_POST_DIVP_MASK :\
1402 mask(p->params->div_nmp->divp_width))
1404 #define divm_shift(p) ((p)->params->div_nmp->divm_shift)
1405 #define divn_shift(p) ((p)->params->div_nmp->divn_shift)
1406 #define divp_shift(p) ((p)->params->div_nmp->divp_shift)
1408 #define divm_mask_shifted(p) (divm_mask(p) << divm_shift(p))
1409 #define divn_mask_shifted(p) (divn_mask(p) << divn_shift(p))
1410 #define divp_mask_shifted(p) (divp_mask(p) << divp_shift(p))
1412 #define PLL_LOCKDET_DELAY 2 /* Lock detection safety delays */
1413 static int tegra210_wait_for_mask(struct tegra_clk_pll *pll,
1419 for (i = 0; i < pll->params->lock_delay / PLL_LOCKDET_DELAY + 1; i++) {
1420 udelay(PLL_LOCKDET_DELAY);
1421 val = readl_relaxed(clk_base + reg);
1422 if ((val & mask) == mask) {
1423 udelay(PLL_LOCKDET_DELAY);
1430 static int tegra210_pllx_dyn_ramp(struct tegra_clk_pll *pllx,
1431 struct tegra_clk_pll_freq_table *cfg)
1433 u32 val, base, ndiv_new_mask;
1435 ndiv_new_mask = (divn_mask(pllx) >> pllx->params->div_nmp->divn_shift)
1436 << PLLX_MISC2_NDIV_NEW_SHIFT;
1438 val = readl_relaxed(clk_base + pllx->params->ext_misc_reg[2]);
1439 val &= (~ndiv_new_mask);
1440 val |= cfg->n << PLLX_MISC2_NDIV_NEW_SHIFT;
1441 writel_relaxed(val, clk_base + pllx->params->ext_misc_reg[2]);
1444 val = readl_relaxed(clk_base + pllx->params->ext_misc_reg[2]);
1445 val |= PLLX_MISC2_EN_DYNRAMP;
1446 writel_relaxed(val, clk_base + pllx->params->ext_misc_reg[2]);
1449 tegra210_wait_for_mask(pllx, pllx->params->ext_misc_reg[2],
1450 PLLX_MISC2_DYNRAMP_DONE);
1452 base = readl_relaxed(clk_base + pllx->params->base_reg) &
1453 (~divn_mask_shifted(pllx));
1454 base |= cfg->n << pllx->params->div_nmp->divn_shift;
1455 writel_relaxed(base, clk_base + pllx->params->base_reg);
1458 val &= ~PLLX_MISC2_EN_DYNRAMP;
1459 writel_relaxed(val, clk_base + pllx->params->ext_misc_reg[2]);
1462 pr_debug("%s: dynamic ramp to m = %u n = %u p = %u, Fout = %lu kHz\n",
1463 __clk_get_name(pllx->hw.clk), cfg->m, cfg->n, cfg->p,
1464 cfg->input_rate / cfg->m * cfg->n /
1465 pllx->params->pdiv_tohw[cfg->p].pdiv / 1000);
1471 * Common configuration for PLLs with fixed input divider policy:
1472 * - always set fixed M-value based on the reference rate
1473 * - always set P-value value 1:1 for output rates above VCO minimum, and
1474 * choose minimum necessary P-value for output rates below VCO maximum
1475 * - calculate N-value based on selected M and P
1476 * - calculate SDM_DIN fractional part
1478 static int tegra210_pll_fixed_mdiv_cfg(struct clk_hw *hw,
1479 struct tegra_clk_pll_freq_table *cfg,
1480 unsigned long rate, unsigned long input_rate)
1482 struct tegra_clk_pll *pll = to_clk_pll(hw);
1483 struct tegra_clk_pll_params *params = pll->params;
1485 unsigned long cf, p_rate;
1491 if (!(params->flags & TEGRA_PLL_VCO_OUT)) {
1492 p = DIV_ROUND_UP(params->vco_min, rate);
1493 p = params->round_p_to_pdiv(p, &pdiv);
1495 p = rate >= params->vco_min ? 1 : -EINVAL;
1501 cfg->m = tegra_pll_get_fixed_mdiv(hw, input_rate);
1504 /* Store P as HW value, as that is what is expected */
1505 cfg->p = tegra_pll_p_div_to_hw(pll, cfg->p);
1508 if (p_rate > params->vco_max)
1509 p_rate = params->vco_max;
1510 cf = input_rate / cfg->m;
1511 cfg->n = p_rate / cf;
1514 cfg->output_rate = input_rate;
1515 if (params->sdm_ctrl_reg) {
1516 unsigned long rem = p_rate - cf * cfg->n;
1517 /* If ssc is enabled SDM enabled as well, even for integer n */
1518 if (rem || params->ssc_ctrl_reg) {
1519 u64 s = rem * PLL_SDM_COEFF;
1522 s -= PLL_SDM_COEFF / 2;
1523 cfg->sdm_data = sdin_din_to_data(s);
1525 cfg->output_rate *= sdin_get_n_eff(cfg);
1526 cfg->output_rate /= p * cfg->m * PLL_SDM_COEFF;
1528 cfg->output_rate *= cfg->n;
1529 cfg->output_rate /= p * cfg->m;
1532 cfg->input_rate = input_rate;
1538 * clk_pll_set_gain - set gain to m, n to calculate correct VCO rate
1540 * @cfg: struct tegra_clk_pll_freq_table * cfg
1543 * Fvco = Fref * NDIV / MDIV
1545 * For fractional mode:
1546 * Fvco = Fref * (NDIV + 0.5 + SDM_DIN / PLL_SDM_COEFF) / MDIV
1548 static void tegra210_clk_pll_set_gain(struct tegra_clk_pll_freq_table *cfg)
1550 cfg->n = sdin_get_n_eff(cfg);
1551 cfg->m *= PLL_SDM_COEFF;
1554 static unsigned long
1555 tegra210_clk_adjust_vco_min(struct tegra_clk_pll_params *params,
1556 unsigned long parent_rate)
1558 unsigned long vco_min = params->vco_min;
1560 params->vco_min += DIV_ROUND_UP(parent_rate, PLL_SDM_COEFF);
1561 vco_min = min(vco_min, params->vco_min);
1566 static struct div_nmp pllx_nmp = {
1575 * PLL post divider maps - two types: quasi-linear and exponential
1578 #define PLL_QLIN_PDIV_MAX 16
1579 static const struct pdiv_map pll_qlin_pdiv_to_hw[] = {
1580 { .pdiv = 1, .hw_val = 0 },
1581 { .pdiv = 2, .hw_val = 1 },
1582 { .pdiv = 3, .hw_val = 2 },
1583 { .pdiv = 4, .hw_val = 3 },
1584 { .pdiv = 5, .hw_val = 4 },
1585 { .pdiv = 6, .hw_val = 5 },
1586 { .pdiv = 8, .hw_val = 6 },
1587 { .pdiv = 9, .hw_val = 7 },
1588 { .pdiv = 10, .hw_val = 8 },
1589 { .pdiv = 12, .hw_val = 9 },
1590 { .pdiv = 15, .hw_val = 10 },
1591 { .pdiv = 16, .hw_val = 11 },
1592 { .pdiv = 18, .hw_val = 12 },
1593 { .pdiv = 20, .hw_val = 13 },
1594 { .pdiv = 24, .hw_val = 14 },
1595 { .pdiv = 30, .hw_val = 15 },
1596 { .pdiv = 32, .hw_val = 16 },
1599 static u32 pll_qlin_p_to_pdiv(u32 p, u32 *pdiv)
1604 for (i = 0; i <= PLL_QLIN_PDIV_MAX; i++) {
1605 if (p <= pll_qlin_pdiv_to_hw[i].pdiv) {
1608 return pll_qlin_pdiv_to_hw[i].pdiv;
1616 #define PLL_EXPO_PDIV_MAX 7
1617 static const struct pdiv_map pll_expo_pdiv_to_hw[] = {
1618 { .pdiv = 1, .hw_val = 0 },
1619 { .pdiv = 2, .hw_val = 1 },
1620 { .pdiv = 4, .hw_val = 2 },
1621 { .pdiv = 8, .hw_val = 3 },
1622 { .pdiv = 16, .hw_val = 4 },
1623 { .pdiv = 32, .hw_val = 5 },
1624 { .pdiv = 64, .hw_val = 6 },
1625 { .pdiv = 128, .hw_val = 7 },
1628 static u32 pll_expo_p_to_pdiv(u32 p, u32 *pdiv)
1636 if (i <= PLL_EXPO_PDIV_MAX) {
1645 static struct tegra_clk_pll_freq_table pll_x_freq_table[] = {
1647 { 12000000, 1000000000, 166, 1, 2, 0 }, /* actual: 996.0 MHz */
1648 { 13000000, 1000000000, 153, 1, 2, 0 }, /* actual: 994.0 MHz */
1649 { 38400000, 1000000000, 156, 3, 2, 0 }, /* actual: 998.4 MHz */
1650 { 0, 0, 0, 0, 0, 0 },
1653 static struct tegra_clk_pll_params pll_x_params = {
1654 .input_min = 12000000,
1655 .input_max = 800000000,
1658 .vco_min = 1350000000,
1659 .vco_max = 3000000000UL,
1660 .base_reg = PLLX_BASE,
1661 .misc_reg = PLLX_MISC0,
1662 .lock_mask = PLL_BASE_LOCK,
1663 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
1665 .ext_misc_reg[0] = PLLX_MISC0,
1666 .ext_misc_reg[1] = PLLX_MISC1,
1667 .ext_misc_reg[2] = PLLX_MISC2,
1668 .ext_misc_reg[3] = PLLX_MISC3,
1669 .ext_misc_reg[4] = PLLX_MISC4,
1670 .ext_misc_reg[5] = PLLX_MISC5,
1671 .iddq_reg = PLLX_MISC3,
1672 .iddq_bit_idx = PLLXP_IDDQ_BIT,
1673 .max_p = PLL_QLIN_PDIV_MAX,
1675 .dyn_ramp_reg = PLLX_MISC2,
1678 .round_p_to_pdiv = pll_qlin_p_to_pdiv,
1679 .pdiv_tohw = pll_qlin_pdiv_to_hw,
1680 .div_nmp = &pllx_nmp,
1681 .freq_table = pll_x_freq_table,
1682 .flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE,
1683 .dyn_ramp = tegra210_pllx_dyn_ramp,
1684 .set_defaults = tegra210_pllx_set_defaults,
1685 .calc_rate = tegra210_pll_fixed_mdiv_cfg,
1688 static struct div_nmp pllc_nmp = {
1697 static struct tegra_clk_pll_freq_table pll_cx_freq_table[] = {
1698 { 12000000, 510000000, 85, 1, 2, 0 },
1699 { 13000000, 510000000, 78, 1, 2, 0 }, /* actual: 507.0 MHz */
1700 { 38400000, 510000000, 79, 3, 2, 0 }, /* actual: 505.6 MHz */
1701 { 0, 0, 0, 0, 0, 0 },
1704 static struct tegra_clk_pll_params pll_c_params = {
1705 .input_min = 12000000,
1706 .input_max = 700000000,
1709 .vco_min = 600000000,
1710 .vco_max = 1200000000,
1711 .base_reg = PLLC_BASE,
1712 .misc_reg = PLLC_MISC0,
1713 .lock_mask = PLL_BASE_LOCK,
1715 .iddq_reg = PLLC_MISC1,
1716 .iddq_bit_idx = PLLCX_IDDQ_BIT,
1717 .reset_reg = PLLC_MISC0,
1718 .reset_bit_idx = PLLCX_RESET_BIT,
1719 .max_p = PLL_QLIN_PDIV_MAX,
1720 .ext_misc_reg[0] = PLLC_MISC0,
1721 .ext_misc_reg[1] = PLLC_MISC1,
1722 .ext_misc_reg[2] = PLLC_MISC2,
1723 .ext_misc_reg[3] = PLLC_MISC3,
1724 .round_p_to_pdiv = pll_qlin_p_to_pdiv,
1725 .pdiv_tohw = pll_qlin_pdiv_to_hw,
1727 .div_nmp = &pllc_nmp,
1728 .freq_table = pll_cx_freq_table,
1729 .flags = TEGRA_PLL_USE_LOCK,
1730 .set_defaults = _pllc_set_defaults,
1731 .calc_rate = tegra210_pll_fixed_mdiv_cfg,
1734 static struct div_nmp pllcx_nmp = {
1743 static struct tegra_clk_pll_params pll_c2_params = {
1744 .input_min = 12000000,
1745 .input_max = 700000000,
1748 .vco_min = 600000000,
1749 .vco_max = 1200000000,
1750 .base_reg = PLLC2_BASE,
1751 .misc_reg = PLLC2_MISC0,
1752 .iddq_reg = PLLC2_MISC1,
1753 .iddq_bit_idx = PLLCX_IDDQ_BIT,
1754 .reset_reg = PLLC2_MISC0,
1755 .reset_bit_idx = PLLCX_RESET_BIT,
1756 .lock_mask = PLLCX_BASE_LOCK,
1758 .round_p_to_pdiv = pll_qlin_p_to_pdiv,
1759 .pdiv_tohw = pll_qlin_pdiv_to_hw,
1761 .div_nmp = &pllcx_nmp,
1762 .max_p = PLL_QLIN_PDIV_MAX,
1763 .ext_misc_reg[0] = PLLC2_MISC0,
1764 .ext_misc_reg[1] = PLLC2_MISC1,
1765 .ext_misc_reg[2] = PLLC2_MISC2,
1766 .ext_misc_reg[3] = PLLC2_MISC3,
1767 .freq_table = pll_cx_freq_table,
1768 .flags = TEGRA_PLL_USE_LOCK,
1769 .set_defaults = _pllc2_set_defaults,
1770 .calc_rate = tegra210_pll_fixed_mdiv_cfg,
1773 static struct tegra_clk_pll_params pll_c3_params = {
1774 .input_min = 12000000,
1775 .input_max = 700000000,
1778 .vco_min = 600000000,
1779 .vco_max = 1200000000,
1780 .base_reg = PLLC3_BASE,
1781 .misc_reg = PLLC3_MISC0,
1782 .lock_mask = PLLCX_BASE_LOCK,
1784 .iddq_reg = PLLC3_MISC1,
1785 .iddq_bit_idx = PLLCX_IDDQ_BIT,
1786 .reset_reg = PLLC3_MISC0,
1787 .reset_bit_idx = PLLCX_RESET_BIT,
1788 .round_p_to_pdiv = pll_qlin_p_to_pdiv,
1789 .pdiv_tohw = pll_qlin_pdiv_to_hw,
1791 .div_nmp = &pllcx_nmp,
1792 .max_p = PLL_QLIN_PDIV_MAX,
1793 .ext_misc_reg[0] = PLLC3_MISC0,
1794 .ext_misc_reg[1] = PLLC3_MISC1,
1795 .ext_misc_reg[2] = PLLC3_MISC2,
1796 .ext_misc_reg[3] = PLLC3_MISC3,
1797 .freq_table = pll_cx_freq_table,
1798 .flags = TEGRA_PLL_USE_LOCK,
1799 .set_defaults = _pllc3_set_defaults,
1800 .calc_rate = tegra210_pll_fixed_mdiv_cfg,
1803 static struct div_nmp pllss_nmp = {
1812 static struct tegra_clk_pll_freq_table pll_c4_vco_freq_table[] = {
1813 { 12000000, 600000000, 50, 1, 1, 0 },
1814 { 13000000, 600000000, 46, 1, 1, 0 }, /* actual: 598.0 MHz */
1815 { 38400000, 600000000, 62, 4, 1, 0 }, /* actual: 595.2 MHz */
1816 { 0, 0, 0, 0, 0, 0 },
1819 static const struct clk_div_table pll_vco_post_div_table[] = {
1820 { .val = 0, .div = 1 },
1821 { .val = 1, .div = 2 },
1822 { .val = 2, .div = 3 },
1823 { .val = 3, .div = 4 },
1824 { .val = 4, .div = 5 },
1825 { .val = 5, .div = 6 },
1826 { .val = 6, .div = 8 },
1827 { .val = 7, .div = 10 },
1828 { .val = 8, .div = 12 },
1829 { .val = 9, .div = 16 },
1830 { .val = 10, .div = 12 },
1831 { .val = 11, .div = 16 },
1832 { .val = 12, .div = 20 },
1833 { .val = 13, .div = 24 },
1834 { .val = 14, .div = 32 },
1835 { .val = 0, .div = 0 },
1838 static struct tegra_clk_pll_params pll_c4_vco_params = {
1839 .input_min = 9600000,
1840 .input_max = 800000000,
1843 .vco_min = 500000000,
1844 .vco_max = 1080000000,
1845 .base_reg = PLLC4_BASE,
1846 .misc_reg = PLLC4_MISC0,
1847 .lock_mask = PLL_BASE_LOCK,
1849 .max_p = PLL_QLIN_PDIV_MAX,
1850 .ext_misc_reg[0] = PLLC4_MISC0,
1851 .iddq_reg = PLLC4_BASE,
1852 .iddq_bit_idx = PLLSS_IDDQ_BIT,
1853 .round_p_to_pdiv = pll_qlin_p_to_pdiv,
1854 .pdiv_tohw = pll_qlin_pdiv_to_hw,
1856 .div_nmp = &pllss_nmp,
1857 .freq_table = pll_c4_vco_freq_table,
1858 .set_defaults = tegra210_pllc4_set_defaults,
1859 .flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_VCO_OUT,
1860 .calc_rate = tegra210_pll_fixed_mdiv_cfg,
1863 static struct tegra_clk_pll_freq_table pll_m_freq_table[] = {
1864 { 12000000, 800000000, 66, 1, 1, 0 }, /* actual: 792.0 MHz */
1865 { 13000000, 800000000, 61, 1, 1, 0 }, /* actual: 793.0 MHz */
1866 { 38400000, 297600000, 93, 4, 3, 0 },
1867 { 38400000, 400000000, 125, 4, 3, 0 },
1868 { 38400000, 532800000, 111, 4, 2, 0 },
1869 { 38400000, 665600000, 104, 3, 2, 0 },
1870 { 38400000, 800000000, 125, 3, 2, 0 },
1871 { 38400000, 931200000, 97, 4, 1, 0 },
1872 { 38400000, 1065600000, 111, 4, 1, 0 },
1873 { 38400000, 1200000000, 125, 4, 1, 0 },
1874 { 38400000, 1331200000, 104, 3, 1, 0 },
1875 { 38400000, 1459200000, 76, 2, 1, 0 },
1876 { 38400000, 1600000000, 125, 3, 1, 0 },
1877 { 0, 0, 0, 0, 0, 0 },
1880 static struct div_nmp pllm_nmp = {
1883 .override_divm_shift = 0,
1886 .override_divn_shift = 8,
1889 .override_divp_shift = 27,
1892 static struct tegra_clk_pll_params pll_m_params = {
1893 .input_min = 9600000,
1894 .input_max = 500000000,
1897 .vco_min = 800000000,
1898 .vco_max = 1866000000,
1899 .base_reg = PLLM_BASE,
1900 .misc_reg = PLLM_MISC2,
1901 .lock_mask = PLL_BASE_LOCK,
1902 .lock_enable_bit_idx = PLLM_MISC_LOCK_ENABLE,
1904 .iddq_reg = PLLM_MISC2,
1905 .iddq_bit_idx = PLLM_IDDQ_BIT,
1906 .max_p = PLL_QLIN_PDIV_MAX,
1907 .ext_misc_reg[0] = PLLM_MISC2,
1908 .ext_misc_reg[1] = PLLM_MISC1,
1909 .round_p_to_pdiv = pll_qlin_p_to_pdiv,
1910 .pdiv_tohw = pll_qlin_pdiv_to_hw,
1911 .div_nmp = &pllm_nmp,
1912 .pmc_divnm_reg = PMC_PLLM_WB0_OVERRIDE,
1913 .pmc_divp_reg = PMC_PLLM_WB0_OVERRIDE_2,
1914 .freq_table = pll_m_freq_table,
1915 .flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE,
1916 .calc_rate = tegra210_pll_fixed_mdiv_cfg,
1919 static struct tegra_clk_pll_params pll_mb_params = {
1920 .input_min = 9600000,
1921 .input_max = 500000000,
1924 .vco_min = 800000000,
1925 .vco_max = 1866000000,
1926 .base_reg = PLLMB_BASE,
1927 .misc_reg = PLLMB_MISC1,
1928 .lock_mask = PLL_BASE_LOCK,
1930 .iddq_reg = PLLMB_MISC1,
1931 .iddq_bit_idx = PLLMB_IDDQ_BIT,
1932 .max_p = PLL_QLIN_PDIV_MAX,
1933 .ext_misc_reg[0] = PLLMB_MISC1,
1934 .round_p_to_pdiv = pll_qlin_p_to_pdiv,
1935 .pdiv_tohw = pll_qlin_pdiv_to_hw,
1936 .div_nmp = &pllm_nmp,
1937 .freq_table = pll_m_freq_table,
1938 .flags = TEGRA_PLL_USE_LOCK,
1939 .set_defaults = tegra210_pllmb_set_defaults,
1940 .calc_rate = tegra210_pll_fixed_mdiv_cfg,
1944 static struct tegra_clk_pll_freq_table pll_e_freq_table[] = {
1945 /* PLLE special case: use cpcon field to store cml divider value */
1946 { 672000000, 100000000, 125, 42, 0, 13 },
1947 { 624000000, 100000000, 125, 39, 0, 13 },
1948 { 336000000, 100000000, 125, 21, 0, 13 },
1949 { 312000000, 100000000, 200, 26, 0, 14 },
1950 { 38400000, 100000000, 125, 2, 0, 14 },
1951 { 12000000, 100000000, 200, 1, 0, 14 },
1952 { 0, 0, 0, 0, 0, 0 },
1955 static struct div_nmp plle_nmp = {
1964 static struct tegra_clk_pll_params pll_e_params = {
1965 .input_min = 12000000,
1966 .input_max = 800000000,
1969 .vco_min = 1600000000,
1970 .vco_max = 2500000000U,
1971 .base_reg = PLLE_BASE,
1972 .misc_reg = PLLE_MISC0,
1973 .aux_reg = PLLE_AUX,
1974 .lock_mask = PLLE_MISC_LOCK,
1975 .lock_enable_bit_idx = PLLE_MISC_LOCK_ENABLE,
1977 .div_nmp = &plle_nmp,
1978 .freq_table = pll_e_freq_table,
1979 .flags = TEGRA_PLL_FIXED | TEGRA_PLL_LOCK_MISC | TEGRA_PLL_USE_LOCK |
1980 TEGRA_PLL_HAS_LOCK_ENABLE,
1981 .fixed_rate = 100000000,
1982 .calc_rate = tegra210_pll_fixed_mdiv_cfg,
1985 static struct tegra_clk_pll_freq_table pll_re_vco_freq_table[] = {
1986 { 12000000, 672000000, 56, 1, 1, 0 },
1987 { 13000000, 672000000, 51, 1, 1, 0 }, /* actual: 663.0 MHz */
1988 { 38400000, 672000000, 70, 4, 1, 0 },
1989 { 0, 0, 0, 0, 0, 0 },
1992 static struct div_nmp pllre_nmp = {
2001 static struct tegra_clk_pll_params pll_re_vco_params = {
2002 .input_min = 9600000,
2003 .input_max = 800000000,
2006 .vco_min = 350000000,
2007 .vco_max = 700000000,
2008 .base_reg = PLLRE_BASE,
2009 .misc_reg = PLLRE_MISC0,
2010 .lock_mask = PLLRE_MISC_LOCK,
2012 .max_p = PLL_QLIN_PDIV_MAX,
2013 .ext_misc_reg[0] = PLLRE_MISC0,
2014 .iddq_reg = PLLRE_MISC0,
2015 .iddq_bit_idx = PLLRE_IDDQ_BIT,
2016 .round_p_to_pdiv = pll_qlin_p_to_pdiv,
2017 .pdiv_tohw = pll_qlin_pdiv_to_hw,
2018 .div_nmp = &pllre_nmp,
2019 .freq_table = pll_re_vco_freq_table,
2020 .flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_LOCK_MISC | TEGRA_PLL_VCO_OUT,
2021 .set_defaults = tegra210_pllre_set_defaults,
2022 .calc_rate = tegra210_pll_fixed_mdiv_cfg,
2025 static struct div_nmp pllp_nmp = {
2034 static struct tegra_clk_pll_freq_table pll_p_freq_table[] = {
2035 { 12000000, 408000000, 34, 1, 1, 0 },
2036 { 38400000, 408000000, 85, 8, 1, 0 }, /* cf = 4.8MHz, allowed exception */
2037 { 0, 0, 0, 0, 0, 0 },
2040 static struct tegra_clk_pll_params pll_p_params = {
2041 .input_min = 9600000,
2042 .input_max = 800000000,
2045 .vco_min = 350000000,
2046 .vco_max = 700000000,
2047 .base_reg = PLLP_BASE,
2048 .misc_reg = PLLP_MISC0,
2049 .lock_mask = PLL_BASE_LOCK,
2051 .iddq_reg = PLLP_MISC0,
2052 .iddq_bit_idx = PLLXP_IDDQ_BIT,
2053 .ext_misc_reg[0] = PLLP_MISC0,
2054 .ext_misc_reg[1] = PLLP_MISC1,
2055 .div_nmp = &pllp_nmp,
2056 .freq_table = pll_p_freq_table,
2057 .fixed_rate = 408000000,
2058 .flags = TEGRA_PLL_FIXED | TEGRA_PLL_USE_LOCK | TEGRA_PLL_VCO_OUT,
2059 .set_defaults = tegra210_pllp_set_defaults,
2060 .calc_rate = tegra210_pll_fixed_mdiv_cfg,
2063 static struct tegra_clk_pll_params pll_a1_params = {
2064 .input_min = 12000000,
2065 .input_max = 700000000,
2068 .vco_min = 600000000,
2069 .vco_max = 1200000000,
2070 .base_reg = PLLA1_BASE,
2071 .misc_reg = PLLA1_MISC0,
2072 .lock_mask = PLLCX_BASE_LOCK,
2074 .iddq_reg = PLLA1_MISC1,
2075 .iddq_bit_idx = PLLCX_IDDQ_BIT,
2076 .reset_reg = PLLA1_MISC0,
2077 .reset_bit_idx = PLLCX_RESET_BIT,
2078 .round_p_to_pdiv = pll_qlin_p_to_pdiv,
2079 .pdiv_tohw = pll_qlin_pdiv_to_hw,
2080 .div_nmp = &pllc_nmp,
2081 .ext_misc_reg[0] = PLLA1_MISC0,
2082 .ext_misc_reg[1] = PLLA1_MISC1,
2083 .ext_misc_reg[2] = PLLA1_MISC2,
2084 .ext_misc_reg[3] = PLLA1_MISC3,
2085 .freq_table = pll_cx_freq_table,
2086 .flags = TEGRA_PLL_USE_LOCK,
2087 .set_defaults = _plla1_set_defaults,
2088 .calc_rate = tegra210_pll_fixed_mdiv_cfg,
2091 static struct div_nmp plla_nmp = {
2100 static struct tegra_clk_pll_freq_table pll_a_freq_table[] = {
2101 { 12000000, 282240000, 47, 1, 2, 1, 0xf148 }, /* actual: 282240234 */
2102 { 12000000, 368640000, 61, 1, 2, 1, 0xfe15 }, /* actual: 368640381 */
2103 { 12000000, 240000000, 60, 1, 3, 1, 0 },
2104 { 13000000, 282240000, 43, 1, 2, 1, 0xfd7d }, /* actual: 282239807 */
2105 { 13000000, 368640000, 56, 1, 2, 1, 0x06d8 }, /* actual: 368640137 */
2106 { 13000000, 240000000, 55, 1, 3, 1, 0 }, /* actual: 238.3 MHz */
2107 { 38400000, 282240000, 44, 3, 2, 1, 0xf333 }, /* actual: 282239844 */
2108 { 38400000, 368640000, 57, 3, 2, 1, 0x0333 }, /* actual: 368639844 */
2109 { 38400000, 240000000, 75, 3, 3, 1, 0 },
2110 { 0, 0, 0, 0, 0, 0, 0 },
2113 static struct tegra_clk_pll_params pll_a_params = {
2114 .input_min = 12000000,
2115 .input_max = 800000000,
2118 .vco_min = 500000000,
2119 .vco_max = 1000000000,
2120 .base_reg = PLLA_BASE,
2121 .misc_reg = PLLA_MISC0,
2122 .lock_mask = PLL_BASE_LOCK,
2124 .round_p_to_pdiv = pll_qlin_p_to_pdiv,
2125 .pdiv_tohw = pll_qlin_pdiv_to_hw,
2126 .iddq_reg = PLLA_BASE,
2127 .iddq_bit_idx = PLLA_IDDQ_BIT,
2128 .div_nmp = &plla_nmp,
2129 .sdm_din_reg = PLLA_MISC1,
2130 .sdm_din_mask = PLLA_SDM_DIN_MASK,
2131 .sdm_ctrl_reg = PLLA_MISC2,
2132 .sdm_ctrl_en_mask = PLLA_SDM_EN_MASK,
2133 .ext_misc_reg[0] = PLLA_MISC0,
2134 .ext_misc_reg[1] = PLLA_MISC1,
2135 .ext_misc_reg[2] = PLLA_MISC2,
2136 .freq_table = pll_a_freq_table,
2137 .flags = TEGRA_PLL_USE_LOCK | TEGRA_MDIV_NEW,
2138 .set_defaults = tegra210_plla_set_defaults,
2139 .calc_rate = tegra210_pll_fixed_mdiv_cfg,
2140 .set_gain = tegra210_clk_pll_set_gain,
2141 .adjust_vco = tegra210_clk_adjust_vco_min,
2144 static struct div_nmp plld_nmp = {
2153 static struct tegra_clk_pll_freq_table pll_d_freq_table[] = {
2154 { 12000000, 594000000, 99, 1, 2, 0, 0 },
2155 { 13000000, 594000000, 91, 1, 2, 0, 0xfc4f }, /* actual: 594000183 */
2156 { 38400000, 594000000, 30, 1, 2, 0, 0x0e00 },
2157 { 0, 0, 0, 0, 0, 0, 0 },
2160 static struct tegra_clk_pll_params pll_d_params = {
2161 .input_min = 12000000,
2162 .input_max = 800000000,
2165 .vco_min = 750000000,
2166 .vco_max = 1500000000,
2167 .base_reg = PLLD_BASE,
2168 .misc_reg = PLLD_MISC0,
2169 .lock_mask = PLL_BASE_LOCK,
2171 .iddq_reg = PLLD_MISC0,
2172 .iddq_bit_idx = PLLD_IDDQ_BIT,
2173 .round_p_to_pdiv = pll_expo_p_to_pdiv,
2174 .pdiv_tohw = pll_expo_pdiv_to_hw,
2175 .div_nmp = &plld_nmp,
2176 .sdm_din_reg = PLLD_MISC0,
2177 .sdm_din_mask = PLLA_SDM_DIN_MASK,
2178 .sdm_ctrl_reg = PLLD_MISC0,
2179 .sdm_ctrl_en_mask = PLLD_SDM_EN_MASK,
2180 .ext_misc_reg[0] = PLLD_MISC0,
2181 .ext_misc_reg[1] = PLLD_MISC1,
2182 .freq_table = pll_d_freq_table,
2183 .flags = TEGRA_PLL_USE_LOCK,
2185 .set_defaults = tegra210_plld_set_defaults,
2186 .calc_rate = tegra210_pll_fixed_mdiv_cfg,
2187 .set_gain = tegra210_clk_pll_set_gain,
2188 .adjust_vco = tegra210_clk_adjust_vco_min,
2191 static struct tegra_clk_pll_freq_table tegra210_pll_d2_freq_table[] = {
2192 { 12000000, 594000000, 99, 1, 2, 0, 0xf000 },
2193 { 13000000, 594000000, 91, 1, 2, 0, 0xfc4f }, /* actual: 594000183 */
2194 { 38400000, 594000000, 30, 1, 2, 0, 0x0e00 },
2195 { 0, 0, 0, 0, 0, 0, 0 },
2198 /* s/w policy, always tegra_pll_ref */
2199 static struct tegra_clk_pll_params pll_d2_params = {
2200 .input_min = 12000000,
2201 .input_max = 800000000,
2204 .vco_min = 750000000,
2205 .vco_max = 1500000000,
2206 .base_reg = PLLD2_BASE,
2207 .misc_reg = PLLD2_MISC0,
2208 .lock_mask = PLL_BASE_LOCK,
2210 .iddq_reg = PLLD2_BASE,
2211 .iddq_bit_idx = PLLSS_IDDQ_BIT,
2212 .sdm_din_reg = PLLD2_MISC3,
2213 .sdm_din_mask = PLLA_SDM_DIN_MASK,
2214 .sdm_ctrl_reg = PLLD2_MISC1,
2215 .sdm_ctrl_en_mask = PLLD2_SDM_EN_MASK,
2216 /* disable spread-spectrum for pll_d2 */
2218 .ssc_ctrl_en_mask = 0,
2219 .round_p_to_pdiv = pll_qlin_p_to_pdiv,
2220 .pdiv_tohw = pll_qlin_pdiv_to_hw,
2221 .div_nmp = &pllss_nmp,
2222 .ext_misc_reg[0] = PLLD2_MISC0,
2223 .ext_misc_reg[1] = PLLD2_MISC1,
2224 .ext_misc_reg[2] = PLLD2_MISC2,
2225 .ext_misc_reg[3] = PLLD2_MISC3,
2226 .max_p = PLL_QLIN_PDIV_MAX,
2228 .freq_table = tegra210_pll_d2_freq_table,
2229 .set_defaults = tegra210_plld2_set_defaults,
2230 .flags = TEGRA_PLL_USE_LOCK,
2231 .calc_rate = tegra210_pll_fixed_mdiv_cfg,
2232 .set_gain = tegra210_clk_pll_set_gain,
2233 .adjust_vco = tegra210_clk_adjust_vco_min,
2236 static struct tegra_clk_pll_freq_table pll_dp_freq_table[] = {
2237 { 12000000, 270000000, 90, 1, 4, 0, 0xf000 },
2238 { 13000000, 270000000, 83, 1, 4, 0, 0xf000 }, /* actual: 269.8 MHz */
2239 { 38400000, 270000000, 28, 1, 4, 0, 0xf400 },
2240 { 0, 0, 0, 0, 0, 0, 0 },
2243 static struct tegra_clk_pll_params pll_dp_params = {
2244 .input_min = 12000000,
2245 .input_max = 800000000,
2248 .vco_min = 750000000,
2249 .vco_max = 1500000000,
2250 .base_reg = PLLDP_BASE,
2251 .misc_reg = PLLDP_MISC,
2252 .lock_mask = PLL_BASE_LOCK,
2254 .iddq_reg = PLLDP_BASE,
2255 .iddq_bit_idx = PLLSS_IDDQ_BIT,
2256 .sdm_din_reg = PLLDP_SS_CTRL2,
2257 .sdm_din_mask = PLLA_SDM_DIN_MASK,
2258 .sdm_ctrl_reg = PLLDP_SS_CFG,
2259 .sdm_ctrl_en_mask = PLLDP_SDM_EN_MASK,
2260 .ssc_ctrl_reg = PLLDP_SS_CFG,
2261 .ssc_ctrl_en_mask = PLLDP_SSC_EN_MASK,
2262 .round_p_to_pdiv = pll_qlin_p_to_pdiv,
2263 .pdiv_tohw = pll_qlin_pdiv_to_hw,
2264 .div_nmp = &pllss_nmp,
2265 .ext_misc_reg[0] = PLLDP_MISC,
2266 .ext_misc_reg[1] = PLLDP_SS_CFG,
2267 .ext_misc_reg[2] = PLLDP_SS_CTRL1,
2268 .ext_misc_reg[3] = PLLDP_SS_CTRL2,
2269 .max_p = PLL_QLIN_PDIV_MAX,
2271 .freq_table = pll_dp_freq_table,
2272 .set_defaults = tegra210_plldp_set_defaults,
2273 .flags = TEGRA_PLL_USE_LOCK,
2274 .calc_rate = tegra210_pll_fixed_mdiv_cfg,
2275 .set_gain = tegra210_clk_pll_set_gain,
2276 .adjust_vco = tegra210_clk_adjust_vco_min,
2279 static struct div_nmp pllu_nmp = {
2288 static struct tegra_clk_pll_freq_table pll_u_freq_table[] = {
2289 { 12000000, 480000000, 40, 1, 1, 0 },
2290 { 13000000, 480000000, 36, 1, 1, 0 }, /* actual: 468.0 MHz */
2291 { 38400000, 480000000, 25, 2, 1, 0 },
2292 { 0, 0, 0, 0, 0, 0 },
2295 static struct tegra_clk_pll_params pll_u_vco_params = {
2296 .input_min = 9600000,
2297 .input_max = 800000000,
2300 .vco_min = 350000000,
2301 .vco_max = 700000000,
2302 .base_reg = PLLU_BASE,
2303 .misc_reg = PLLU_MISC0,
2304 .lock_mask = PLL_BASE_LOCK,
2306 .iddq_reg = PLLU_MISC0,
2307 .iddq_bit_idx = PLLU_IDDQ_BIT,
2308 .ext_misc_reg[0] = PLLU_MISC0,
2309 .ext_misc_reg[1] = PLLU_MISC1,
2310 .round_p_to_pdiv = pll_qlin_p_to_pdiv,
2311 .pdiv_tohw = pll_qlin_pdiv_to_hw,
2312 .div_nmp = &pllu_nmp,
2313 .freq_table = pll_u_freq_table,
2314 .flags = TEGRA_PLLU | TEGRA_PLL_USE_LOCK | TEGRA_PLL_VCO_OUT,
2317 struct utmi_clk_param {
2318 /* Oscillator Frequency in KHz */
2320 /* UTMIP PLL Enable Delay Count */
2321 u8 enable_delay_count;
2322 /* UTMIP PLL Stable count */
2324 /* UTMIP PLL Active delay count */
2325 u8 active_delay_count;
2326 /* UTMIP PLL Xtal frequency count */
2327 u16 xtal_freq_count;
2330 static const struct utmi_clk_param utmi_parameters[] = {
2332 .osc_frequency = 38400000, .enable_delay_count = 0x0,
2333 .stable_count = 0x0, .active_delay_count = 0x6,
2334 .xtal_freq_count = 0x80
2336 .osc_frequency = 13000000, .enable_delay_count = 0x02,
2337 .stable_count = 0x33, .active_delay_count = 0x05,
2338 .xtal_freq_count = 0x7f
2340 .osc_frequency = 19200000, .enable_delay_count = 0x03,
2341 .stable_count = 0x4b, .active_delay_count = 0x06,
2342 .xtal_freq_count = 0xbb
2344 .osc_frequency = 12000000, .enable_delay_count = 0x02,
2345 .stable_count = 0x2f, .active_delay_count = 0x08,
2346 .xtal_freq_count = 0x76
2348 .osc_frequency = 26000000, .enable_delay_count = 0x04,
2349 .stable_count = 0x66, .active_delay_count = 0x09,
2350 .xtal_freq_count = 0xfe
2352 .osc_frequency = 16800000, .enable_delay_count = 0x03,
2353 .stable_count = 0x41, .active_delay_count = 0x0a,
2354 .xtal_freq_count = 0xa4
2358 static struct tegra_clk tegra210_clks[tegra_clk_max] __initdata = {
2359 [tegra_clk_ispb] = { .dt_id = TEGRA210_CLK_ISPB, .present = true },
2360 [tegra_clk_rtc] = { .dt_id = TEGRA210_CLK_RTC, .present = true },
2361 [tegra_clk_timer] = { .dt_id = TEGRA210_CLK_TIMER, .present = true },
2362 [tegra_clk_uarta_8] = { .dt_id = TEGRA210_CLK_UARTA, .present = true },
2363 [tegra_clk_i2s1] = { .dt_id = TEGRA210_CLK_I2S1, .present = true },
2364 [tegra_clk_i2c1] = { .dt_id = TEGRA210_CLK_I2C1, .present = true },
2365 [tegra_clk_sdmmc1_9] = { .dt_id = TEGRA210_CLK_SDMMC1, .present = true },
2366 [tegra_clk_pwm] = { .dt_id = TEGRA210_CLK_PWM, .present = true },
2367 [tegra_clk_i2s2] = { .dt_id = TEGRA210_CLK_I2S2, .present = true },
2368 [tegra_clk_usbd] = { .dt_id = TEGRA210_CLK_USBD, .present = true },
2369 [tegra_clk_isp_9] = { .dt_id = TEGRA210_CLK_ISP, .present = true },
2370 [tegra_clk_disp2_8] = { .dt_id = TEGRA210_CLK_DISP2, .present = true },
2371 [tegra_clk_disp1_8] = { .dt_id = TEGRA210_CLK_DISP1, .present = true },
2372 [tegra_clk_host1x_9] = { .dt_id = TEGRA210_CLK_HOST1X, .present = true },
2373 [tegra_clk_i2s0] = { .dt_id = TEGRA210_CLK_I2S0, .present = true },
2374 [tegra_clk_apbdma] = { .dt_id = TEGRA210_CLK_APBDMA, .present = true },
2375 [tegra_clk_kfuse] = { .dt_id = TEGRA210_CLK_KFUSE, .present = true },
2376 [tegra_clk_sbc1_9] = { .dt_id = TEGRA210_CLK_SBC1, .present = true },
2377 [tegra_clk_sbc2_9] = { .dt_id = TEGRA210_CLK_SBC2, .present = true },
2378 [tegra_clk_sbc3_9] = { .dt_id = TEGRA210_CLK_SBC3, .present = true },
2379 [tegra_clk_i2c5] = { .dt_id = TEGRA210_CLK_I2C5, .present = true },
2380 [tegra_clk_csi] = { .dt_id = TEGRA210_CLK_CSI, .present = true },
2381 [tegra_clk_i2c2] = { .dt_id = TEGRA210_CLK_I2C2, .present = true },
2382 [tegra_clk_uartc_8] = { .dt_id = TEGRA210_CLK_UARTC, .present = true },
2383 [tegra_clk_mipi_cal] = { .dt_id = TEGRA210_CLK_MIPI_CAL, .present = true },
2384 [tegra_clk_usb2] = { .dt_id = TEGRA210_CLK_USB2, .present = true },
2385 [tegra_clk_bsev] = { .dt_id = TEGRA210_CLK_BSEV, .present = true },
2386 [tegra_clk_uartd_8] = { .dt_id = TEGRA210_CLK_UARTD, .present = true },
2387 [tegra_clk_i2c3] = { .dt_id = TEGRA210_CLK_I2C3, .present = true },
2388 [tegra_clk_sbc4_9] = { .dt_id = TEGRA210_CLK_SBC4, .present = true },
2389 [tegra_clk_sdmmc3_9] = { .dt_id = TEGRA210_CLK_SDMMC3, .present = true },
2390 [tegra_clk_pcie] = { .dt_id = TEGRA210_CLK_PCIE, .present = true },
2391 [tegra_clk_owr_8] = { .dt_id = TEGRA210_CLK_OWR, .present = true },
2392 [tegra_clk_afi] = { .dt_id = TEGRA210_CLK_AFI, .present = true },
2393 [tegra_clk_csite_8] = { .dt_id = TEGRA210_CLK_CSITE, .present = true },
2394 [tegra_clk_soc_therm_8] = { .dt_id = TEGRA210_CLK_SOC_THERM, .present = true },
2395 [tegra_clk_dtv] = { .dt_id = TEGRA210_CLK_DTV, .present = true },
2396 [tegra_clk_i2cslow] = { .dt_id = TEGRA210_CLK_I2CSLOW, .present = true },
2397 [tegra_clk_tsec_8] = { .dt_id = TEGRA210_CLK_TSEC, .present = true },
2398 [tegra_clk_xusb_host] = { .dt_id = TEGRA210_CLK_XUSB_HOST, .present = true },
2399 [tegra_clk_csus] = { .dt_id = TEGRA210_CLK_CSUS, .present = true },
2400 [tegra_clk_mselect] = { .dt_id = TEGRA210_CLK_MSELECT, .present = true },
2401 [tegra_clk_tsensor] = { .dt_id = TEGRA210_CLK_TSENSOR, .present = true },
2402 [tegra_clk_i2s3] = { .dt_id = TEGRA210_CLK_I2S3, .present = true },
2403 [tegra_clk_i2s4] = { .dt_id = TEGRA210_CLK_I2S4, .present = true },
2404 [tegra_clk_i2c4] = { .dt_id = TEGRA210_CLK_I2C4, .present = true },
2405 [tegra_clk_d_audio] = { .dt_id = TEGRA210_CLK_D_AUDIO, .present = true },
2406 [tegra_clk_hda2codec_2x_8] = { .dt_id = TEGRA210_CLK_HDA2CODEC_2X, .present = true },
2407 [tegra_clk_spdif_2x] = { .dt_id = TEGRA210_CLK_SPDIF_2X, .present = true },
2408 [tegra_clk_actmon] = { .dt_id = TEGRA210_CLK_ACTMON, .present = true },
2409 [tegra_clk_extern1] = { .dt_id = TEGRA210_CLK_EXTERN1, .present = true },
2410 [tegra_clk_extern2] = { .dt_id = TEGRA210_CLK_EXTERN2, .present = true },
2411 [tegra_clk_extern3] = { .dt_id = TEGRA210_CLK_EXTERN3, .present = true },
2412 [tegra_clk_sata_oob_8] = { .dt_id = TEGRA210_CLK_SATA_OOB, .present = true },
2413 [tegra_clk_sata_8] = { .dt_id = TEGRA210_CLK_SATA, .present = true },
2414 [tegra_clk_hda_8] = { .dt_id = TEGRA210_CLK_HDA, .present = true },
2415 [tegra_clk_hda2hdmi] = { .dt_id = TEGRA210_CLK_HDA2HDMI, .present = true },
2416 [tegra_clk_cilab] = { .dt_id = TEGRA210_CLK_CILAB, .present = true },
2417 [tegra_clk_cilcd] = { .dt_id = TEGRA210_CLK_CILCD, .present = true },
2418 [tegra_clk_cile] = { .dt_id = TEGRA210_CLK_CILE, .present = true },
2419 [tegra_clk_dsialp] = { .dt_id = TEGRA210_CLK_DSIALP, .present = true },
2420 [tegra_clk_dsiblp] = { .dt_id = TEGRA210_CLK_DSIBLP, .present = true },
2421 [tegra_clk_entropy_8] = { .dt_id = TEGRA210_CLK_ENTROPY, .present = true },
2422 [tegra_clk_xusb_ss] = { .dt_id = TEGRA210_CLK_XUSB_SS, .present = true },
2423 [tegra_clk_i2c6] = { .dt_id = TEGRA210_CLK_I2C6, .present = true },
2424 [tegra_clk_vim2_clk] = { .dt_id = TEGRA210_CLK_VIM2_CLK, .present = true },
2425 [tegra_clk_clk72Mhz_8] = { .dt_id = TEGRA210_CLK_CLK72MHZ, .present = true },
2426 [tegra_clk_vic03_8] = { .dt_id = TEGRA210_CLK_VIC03, .present = true },
2427 [tegra_clk_dpaux] = { .dt_id = TEGRA210_CLK_DPAUX, .present = true },
2428 [tegra_clk_dpaux1] = { .dt_id = TEGRA210_CLK_DPAUX1, .present = true },
2429 [tegra_clk_sor0] = { .dt_id = TEGRA210_CLK_SOR0, .present = true },
2430 [tegra_clk_sor0_out] = { .dt_id = TEGRA210_CLK_SOR0_OUT, .present = true },
2431 [tegra_clk_sor1] = { .dt_id = TEGRA210_CLK_SOR1, .present = true },
2432 [tegra_clk_sor1_out] = { .dt_id = TEGRA210_CLK_SOR1_OUT, .present = true },
2433 [tegra_clk_gpu] = { .dt_id = TEGRA210_CLK_GPU, .present = true },
2434 [tegra_clk_pll_g_ref] = { .dt_id = TEGRA210_CLK_PLL_G_REF, .present = true, },
2435 [tegra_clk_uartb_8] = { .dt_id = TEGRA210_CLK_UARTB, .present = true },
2436 [tegra_clk_spdif_in_8] = { .dt_id = TEGRA210_CLK_SPDIF_IN, .present = true },
2437 [tegra_clk_spdif_out] = { .dt_id = TEGRA210_CLK_SPDIF_OUT, .present = true },
2438 [tegra_clk_vi_10] = { .dt_id = TEGRA210_CLK_VI, .present = true },
2439 [tegra_clk_vi_sensor_8] = { .dt_id = TEGRA210_CLK_VI_SENSOR, .present = true },
2440 [tegra_clk_fuse] = { .dt_id = TEGRA210_CLK_FUSE, .present = true },
2441 [tegra_clk_fuse_burn] = { .dt_id = TEGRA210_CLK_FUSE_BURN, .present = true },
2442 [tegra_clk_clk_32k] = { .dt_id = TEGRA210_CLK_CLK_32K, .present = true },
2443 [tegra_clk_clk_m] = { .dt_id = TEGRA210_CLK_CLK_M, .present = true },
2444 [tegra_clk_osc] = { .dt_id = TEGRA210_CLK_OSC, .present = true },
2445 [tegra_clk_osc_div2] = { .dt_id = TEGRA210_CLK_OSC_DIV2, .present = true },
2446 [tegra_clk_osc_div4] = { .dt_id = TEGRA210_CLK_OSC_DIV4, .present = true },
2447 [tegra_clk_pll_ref] = { .dt_id = TEGRA210_CLK_PLL_REF, .present = true },
2448 [tegra_clk_pll_c] = { .dt_id = TEGRA210_CLK_PLL_C, .present = true },
2449 [tegra_clk_pll_c_out1] = { .dt_id = TEGRA210_CLK_PLL_C_OUT1, .present = true },
2450 [tegra_clk_pll_c2] = { .dt_id = TEGRA210_CLK_PLL_C2, .present = true },
2451 [tegra_clk_pll_c3] = { .dt_id = TEGRA210_CLK_PLL_C3, .present = true },
2452 [tegra_clk_pll_m] = { .dt_id = TEGRA210_CLK_PLL_M, .present = true },
2453 [tegra_clk_pll_p] = { .dt_id = TEGRA210_CLK_PLL_P, .present = true },
2454 [tegra_clk_pll_p_out1] = { .dt_id = TEGRA210_CLK_PLL_P_OUT1, .present = true },
2455 [tegra_clk_pll_p_out3] = { .dt_id = TEGRA210_CLK_PLL_P_OUT3, .present = true },
2456 [tegra_clk_pll_p_out4_cpu] = { .dt_id = TEGRA210_CLK_PLL_P_OUT4, .present = true },
2457 [tegra_clk_pll_p_out_hsio] = { .dt_id = TEGRA210_CLK_PLL_P_OUT_HSIO, .present = true },
2458 [tegra_clk_pll_p_out_xusb] = { .dt_id = TEGRA210_CLK_PLL_P_OUT_XUSB, .present = true },
2459 [tegra_clk_pll_p_out_cpu] = { .dt_id = TEGRA210_CLK_PLL_P_OUT_CPU, .present = true },
2460 [tegra_clk_pll_p_out_adsp] = { .dt_id = TEGRA210_CLK_PLL_P_OUT_ADSP, .present = true },
2461 [tegra_clk_pll_a] = { .dt_id = TEGRA210_CLK_PLL_A, .present = true },
2462 [tegra_clk_pll_a_out0] = { .dt_id = TEGRA210_CLK_PLL_A_OUT0, .present = true },
2463 [tegra_clk_pll_d] = { .dt_id = TEGRA210_CLK_PLL_D, .present = true },
2464 [tegra_clk_pll_d_out0] = { .dt_id = TEGRA210_CLK_PLL_D_OUT0, .present = true },
2465 [tegra_clk_pll_d2] = { .dt_id = TEGRA210_CLK_PLL_D2, .present = true },
2466 [tegra_clk_pll_d2_out0] = { .dt_id = TEGRA210_CLK_PLL_D2_OUT0, .present = true },
2467 [tegra_clk_pll_u] = { .dt_id = TEGRA210_CLK_PLL_U, .present = true },
2468 [tegra_clk_pll_u_out] = { .dt_id = TEGRA210_CLK_PLL_U_OUT, .present = true },
2469 [tegra_clk_pll_u_out1] = { .dt_id = TEGRA210_CLK_PLL_U_OUT1, .present = true },
2470 [tegra_clk_pll_u_out2] = { .dt_id = TEGRA210_CLK_PLL_U_OUT2, .present = true },
2471 [tegra_clk_pll_u_480m] = { .dt_id = TEGRA210_CLK_PLL_U_480M, .present = true },
2472 [tegra_clk_pll_u_60m] = { .dt_id = TEGRA210_CLK_PLL_U_60M, .present = true },
2473 [tegra_clk_pll_u_48m] = { .dt_id = TEGRA210_CLK_PLL_U_48M, .present = true },
2474 [tegra_clk_pll_x] = { .dt_id = TEGRA210_CLK_PLL_X, .present = true },
2475 [tegra_clk_pll_x_out0] = { .dt_id = TEGRA210_CLK_PLL_X_OUT0, .present = true },
2476 [tegra_clk_pll_re_vco] = { .dt_id = TEGRA210_CLK_PLL_RE_VCO, .present = true },
2477 [tegra_clk_pll_re_out] = { .dt_id = TEGRA210_CLK_PLL_RE_OUT, .present = true },
2478 [tegra_clk_spdif_in_sync] = { .dt_id = TEGRA210_CLK_SPDIF_IN_SYNC, .present = true },
2479 [tegra_clk_i2s0_sync] = { .dt_id = TEGRA210_CLK_I2S0_SYNC, .present = true },
2480 [tegra_clk_i2s1_sync] = { .dt_id = TEGRA210_CLK_I2S1_SYNC, .present = true },
2481 [tegra_clk_i2s2_sync] = { .dt_id = TEGRA210_CLK_I2S2_SYNC, .present = true },
2482 [tegra_clk_i2s3_sync] = { .dt_id = TEGRA210_CLK_I2S3_SYNC, .present = true },
2483 [tegra_clk_i2s4_sync] = { .dt_id = TEGRA210_CLK_I2S4_SYNC, .present = true },
2484 [tegra_clk_vimclk_sync] = { .dt_id = TEGRA210_CLK_VIMCLK_SYNC, .present = true },
2485 [tegra_clk_audio0] = { .dt_id = TEGRA210_CLK_AUDIO0, .present = true },
2486 [tegra_clk_audio1] = { .dt_id = TEGRA210_CLK_AUDIO1, .present = true },
2487 [tegra_clk_audio2] = { .dt_id = TEGRA210_CLK_AUDIO2, .present = true },
2488 [tegra_clk_audio3] = { .dt_id = TEGRA210_CLK_AUDIO3, .present = true },
2489 [tegra_clk_audio4] = { .dt_id = TEGRA210_CLK_AUDIO4, .present = true },
2490 [tegra_clk_spdif] = { .dt_id = TEGRA210_CLK_SPDIF, .present = true },
2491 [tegra_clk_xusb_gate] = { .dt_id = TEGRA210_CLK_XUSB_GATE, .present = true },
2492 [tegra_clk_xusb_host_src_8] = { .dt_id = TEGRA210_CLK_XUSB_HOST_SRC, .present = true },
2493 [tegra_clk_xusb_falcon_src_8] = { .dt_id = TEGRA210_CLK_XUSB_FALCON_SRC, .present = true },
2494 [tegra_clk_xusb_fs_src] = { .dt_id = TEGRA210_CLK_XUSB_FS_SRC, .present = true },
2495 [tegra_clk_xusb_ss_src_8] = { .dt_id = TEGRA210_CLK_XUSB_SS_SRC, .present = true },
2496 [tegra_clk_xusb_ss_div2] = { .dt_id = TEGRA210_CLK_XUSB_SS_DIV2, .present = true },
2497 [tegra_clk_xusb_dev_src_8] = { .dt_id = TEGRA210_CLK_XUSB_DEV_SRC, .present = true },
2498 [tegra_clk_xusb_dev] = { .dt_id = TEGRA210_CLK_XUSB_DEV, .present = true },
2499 [tegra_clk_xusb_hs_src_4] = { .dt_id = TEGRA210_CLK_XUSB_HS_SRC, .present = true },
2500 [tegra_clk_xusb_ssp_src] = { .dt_id = TEGRA210_CLK_XUSB_SSP_SRC, .present = true },
2501 [tegra_clk_usb2_hsic_trk] = { .dt_id = TEGRA210_CLK_USB2_HSIC_TRK, .present = true },
2502 [tegra_clk_hsic_trk] = { .dt_id = TEGRA210_CLK_HSIC_TRK, .present = true },
2503 [tegra_clk_usb2_trk] = { .dt_id = TEGRA210_CLK_USB2_TRK, .present = true },
2504 [tegra_clk_sclk] = { .dt_id = TEGRA210_CLK_SCLK, .present = true },
2505 [tegra_clk_sclk_mux] = { .dt_id = TEGRA210_CLK_SCLK_MUX, .present = true },
2506 [tegra_clk_hclk] = { .dt_id = TEGRA210_CLK_HCLK, .present = true },
2507 [tegra_clk_pclk] = { .dt_id = TEGRA210_CLK_PCLK, .present = true },
2508 [tegra_clk_cclk_g] = { .dt_id = TEGRA210_CLK_CCLK_G, .present = true },
2509 [tegra_clk_cclk_lp] = { .dt_id = TEGRA210_CLK_CCLK_LP, .present = true },
2510 [tegra_clk_dfll_ref] = { .dt_id = TEGRA210_CLK_DFLL_REF, .present = true },
2511 [tegra_clk_dfll_soc] = { .dt_id = TEGRA210_CLK_DFLL_SOC, .present = true },
2512 [tegra_clk_vi_sensor2_8] = { .dt_id = TEGRA210_CLK_VI_SENSOR2, .present = true },
2513 [tegra_clk_pll_p_out5] = { .dt_id = TEGRA210_CLK_PLL_P_OUT5, .present = true },
2514 [tegra_clk_pll_c4] = { .dt_id = TEGRA210_CLK_PLL_C4, .present = true },
2515 [tegra_clk_pll_dp] = { .dt_id = TEGRA210_CLK_PLL_DP, .present = true },
2516 [tegra_clk_audio0_mux] = { .dt_id = TEGRA210_CLK_AUDIO0_MUX, .present = true },
2517 [tegra_clk_audio1_mux] = { .dt_id = TEGRA210_CLK_AUDIO1_MUX, .present = true },
2518 [tegra_clk_audio2_mux] = { .dt_id = TEGRA210_CLK_AUDIO2_MUX, .present = true },
2519 [tegra_clk_audio3_mux] = { .dt_id = TEGRA210_CLK_AUDIO3_MUX, .present = true },
2520 [tegra_clk_audio4_mux] = { .dt_id = TEGRA210_CLK_AUDIO4_MUX, .present = true },
2521 [tegra_clk_spdif_mux] = { .dt_id = TEGRA210_CLK_SPDIF_MUX, .present = true },
2522 [tegra_clk_maud] = { .dt_id = TEGRA210_CLK_MAUD, .present = true },
2523 [tegra_clk_mipibif] = { .dt_id = TEGRA210_CLK_MIPIBIF, .present = true },
2524 [tegra_clk_qspi] = { .dt_id = TEGRA210_CLK_QSPI, .present = true },
2525 [tegra_clk_sdmmc_legacy] = { .dt_id = TEGRA210_CLK_SDMMC_LEGACY, .present = true },
2526 [tegra_clk_tsecb] = { .dt_id = TEGRA210_CLK_TSECB, .present = true },
2527 [tegra_clk_uartape] = { .dt_id = TEGRA210_CLK_UARTAPE, .present = true },
2528 [tegra_clk_vi_i2c] = { .dt_id = TEGRA210_CLK_VI_I2C, .present = true },
2529 [tegra_clk_ape] = { .dt_id = TEGRA210_CLK_APE, .present = true },
2530 [tegra_clk_dbgapb] = { .dt_id = TEGRA210_CLK_DBGAPB, .present = true },
2531 [tegra_clk_nvdec] = { .dt_id = TEGRA210_CLK_NVDEC, .present = true },
2532 [tegra_clk_nvenc] = { .dt_id = TEGRA210_CLK_NVENC, .present = true },
2533 [tegra_clk_nvjpg] = { .dt_id = TEGRA210_CLK_NVJPG, .present = true },
2534 [tegra_clk_pll_c4_out0] = { .dt_id = TEGRA210_CLK_PLL_C4_OUT0, .present = true },
2535 [tegra_clk_pll_c4_out1] = { .dt_id = TEGRA210_CLK_PLL_C4_OUT1, .present = true },
2536 [tegra_clk_pll_c4_out2] = { .dt_id = TEGRA210_CLK_PLL_C4_OUT2, .present = true },
2537 [tegra_clk_pll_c4_out3] = { .dt_id = TEGRA210_CLK_PLL_C4_OUT3, .present = true },
2538 [tegra_clk_apb2ape] = { .dt_id = TEGRA210_CLK_APB2APE, .present = true },
2539 [tegra_clk_pll_a1] = { .dt_id = TEGRA210_CLK_PLL_A1, .present = true },
2540 [tegra_clk_ispa] = { .dt_id = TEGRA210_CLK_ISPA, .present = true },
2541 [tegra_clk_cec] = { .dt_id = TEGRA210_CLK_CEC, .present = true },
2542 [tegra_clk_dmic1] = { .dt_id = TEGRA210_CLK_DMIC1, .present = true },
2543 [tegra_clk_dmic2] = { .dt_id = TEGRA210_CLK_DMIC2, .present = true },
2544 [tegra_clk_dmic3] = { .dt_id = TEGRA210_CLK_DMIC3, .present = true },
2545 [tegra_clk_dmic1_sync_clk] = { .dt_id = TEGRA210_CLK_DMIC1_SYNC_CLK, .present = true },
2546 [tegra_clk_dmic2_sync_clk] = { .dt_id = TEGRA210_CLK_DMIC2_SYNC_CLK, .present = true },
2547 [tegra_clk_dmic3_sync_clk] = { .dt_id = TEGRA210_CLK_DMIC3_SYNC_CLK, .present = true },
2548 [tegra_clk_dmic1_sync_clk_mux] = { .dt_id = TEGRA210_CLK_DMIC1_SYNC_CLK_MUX, .present = true },
2549 [tegra_clk_dmic2_sync_clk_mux] = { .dt_id = TEGRA210_CLK_DMIC2_SYNC_CLK_MUX, .present = true },
2550 [tegra_clk_dmic3_sync_clk_mux] = { .dt_id = TEGRA210_CLK_DMIC3_SYNC_CLK_MUX, .present = true },
2551 [tegra_clk_dp2] = { .dt_id = TEGRA210_CLK_DP2, .present = true },
2552 [tegra_clk_iqc1] = { .dt_id = TEGRA210_CLK_IQC1, .present = true },
2553 [tegra_clk_iqc2] = { .dt_id = TEGRA210_CLK_IQC2, .present = true },
2554 [tegra_clk_pll_a_out_adsp] = { .dt_id = TEGRA210_CLK_PLL_A_OUT_ADSP, .present = true },
2555 [tegra_clk_pll_a_out0_out_adsp] = { .dt_id = TEGRA210_CLK_PLL_A_OUT0_OUT_ADSP, .present = true },
2556 [tegra_clk_adsp] = { .dt_id = TEGRA210_CLK_ADSP, .present = true },
2557 [tegra_clk_adsp_neon] = { .dt_id = TEGRA210_CLK_ADSP_NEON, .present = true },
2560 static struct tegra_devclk devclks[] __initdata = {
2561 { .con_id = "clk_m", .dt_id = TEGRA210_CLK_CLK_M },
2562 { .con_id = "pll_ref", .dt_id = TEGRA210_CLK_PLL_REF },
2563 { .con_id = "clk_32k", .dt_id = TEGRA210_CLK_CLK_32K },
2564 { .con_id = "osc", .dt_id = TEGRA210_CLK_OSC },
2565 { .con_id = "osc_div2", .dt_id = TEGRA210_CLK_OSC_DIV2 },
2566 { .con_id = "osc_div4", .dt_id = TEGRA210_CLK_OSC_DIV4 },
2567 { .con_id = "pll_c", .dt_id = TEGRA210_CLK_PLL_C },
2568 { .con_id = "pll_c_out1", .dt_id = TEGRA210_CLK_PLL_C_OUT1 },
2569 { .con_id = "pll_c2", .dt_id = TEGRA210_CLK_PLL_C2 },
2570 { .con_id = "pll_c3", .dt_id = TEGRA210_CLK_PLL_C3 },
2571 { .con_id = "pll_p", .dt_id = TEGRA210_CLK_PLL_P },
2572 { .con_id = "pll_p_out1", .dt_id = TEGRA210_CLK_PLL_P_OUT1 },
2573 { .con_id = "pll_p_out2", .dt_id = TEGRA210_CLK_PLL_P_OUT2 },
2574 { .con_id = "pll_p_out3", .dt_id = TEGRA210_CLK_PLL_P_OUT3 },
2575 { .con_id = "pll_p_out4", .dt_id = TEGRA210_CLK_PLL_P_OUT4 },
2576 { .con_id = "pll_m", .dt_id = TEGRA210_CLK_PLL_M },
2577 { .con_id = "pll_x", .dt_id = TEGRA210_CLK_PLL_X },
2578 { .con_id = "pll_x_out0", .dt_id = TEGRA210_CLK_PLL_X_OUT0 },
2579 { .con_id = "pll_u", .dt_id = TEGRA210_CLK_PLL_U },
2580 { .con_id = "pll_u_out", .dt_id = TEGRA210_CLK_PLL_U_OUT },
2581 { .con_id = "pll_u_out1", .dt_id = TEGRA210_CLK_PLL_U_OUT1 },
2582 { .con_id = "pll_u_out2", .dt_id = TEGRA210_CLK_PLL_U_OUT2 },
2583 { .con_id = "pll_u_480M", .dt_id = TEGRA210_CLK_PLL_U_480M },
2584 { .con_id = "pll_u_60M", .dt_id = TEGRA210_CLK_PLL_U_60M },
2585 { .con_id = "pll_u_48M", .dt_id = TEGRA210_CLK_PLL_U_48M },
2586 { .con_id = "pll_d", .dt_id = TEGRA210_CLK_PLL_D },
2587 { .con_id = "pll_d_out0", .dt_id = TEGRA210_CLK_PLL_D_OUT0 },
2588 { .con_id = "pll_d2", .dt_id = TEGRA210_CLK_PLL_D2 },
2589 { .con_id = "pll_d2_out0", .dt_id = TEGRA210_CLK_PLL_D2_OUT0 },
2590 { .con_id = "pll_a", .dt_id = TEGRA210_CLK_PLL_A },
2591 { .con_id = "pll_a_out0", .dt_id = TEGRA210_CLK_PLL_A_OUT0 },
2592 { .con_id = "pll_re_vco", .dt_id = TEGRA210_CLK_PLL_RE_VCO },
2593 { .con_id = "pll_re_out", .dt_id = TEGRA210_CLK_PLL_RE_OUT },
2594 { .con_id = "spdif_in_sync", .dt_id = TEGRA210_CLK_SPDIF_IN_SYNC },
2595 { .con_id = "i2s0_sync", .dt_id = TEGRA210_CLK_I2S0_SYNC },
2596 { .con_id = "i2s1_sync", .dt_id = TEGRA210_CLK_I2S1_SYNC },
2597 { .con_id = "i2s2_sync", .dt_id = TEGRA210_CLK_I2S2_SYNC },
2598 { .con_id = "i2s3_sync", .dt_id = TEGRA210_CLK_I2S3_SYNC },
2599 { .con_id = "i2s4_sync", .dt_id = TEGRA210_CLK_I2S4_SYNC },
2600 { .con_id = "vimclk_sync", .dt_id = TEGRA210_CLK_VIMCLK_SYNC },
2601 { .con_id = "audio0", .dt_id = TEGRA210_CLK_AUDIO0 },
2602 { .con_id = "audio1", .dt_id = TEGRA210_CLK_AUDIO1 },
2603 { .con_id = "audio2", .dt_id = TEGRA210_CLK_AUDIO2 },
2604 { .con_id = "audio3", .dt_id = TEGRA210_CLK_AUDIO3 },
2605 { .con_id = "audio4", .dt_id = TEGRA210_CLK_AUDIO4 },
2606 { .con_id = "spdif", .dt_id = TEGRA210_CLK_SPDIF },
2607 { .con_id = "spdif_2x", .dt_id = TEGRA210_CLK_SPDIF_2X },
2608 { .con_id = "extern1", .dt_id = TEGRA210_CLK_EXTERN1 },
2609 { .con_id = "extern2", .dt_id = TEGRA210_CLK_EXTERN2 },
2610 { .con_id = "extern3", .dt_id = TEGRA210_CLK_EXTERN3 },
2611 { .con_id = "cclk_g", .dt_id = TEGRA210_CLK_CCLK_G },
2612 { .con_id = "cclk_lp", .dt_id = TEGRA210_CLK_CCLK_LP },
2613 { .con_id = "sclk", .dt_id = TEGRA210_CLK_SCLK },
2614 { .con_id = "hclk", .dt_id = TEGRA210_CLK_HCLK },
2615 { .con_id = "pclk", .dt_id = TEGRA210_CLK_PCLK },
2616 { .con_id = "fuse", .dt_id = TEGRA210_CLK_FUSE },
2617 { .dev_id = "rtc-tegra", .dt_id = TEGRA210_CLK_RTC },
2618 { .dev_id = "timer", .dt_id = TEGRA210_CLK_TIMER },
2619 { .con_id = "pll_c4_out0", .dt_id = TEGRA210_CLK_PLL_C4_OUT0 },
2620 { .con_id = "pll_c4_out1", .dt_id = TEGRA210_CLK_PLL_C4_OUT1 },
2621 { .con_id = "pll_c4_out2", .dt_id = TEGRA210_CLK_PLL_C4_OUT2 },
2622 { .con_id = "pll_c4_out3", .dt_id = TEGRA210_CLK_PLL_C4_OUT3 },
2623 { .con_id = "dpaux", .dt_id = TEGRA210_CLK_DPAUX },
2626 static struct tegra_audio_clk_info tegra210_audio_plls[] = {
2627 { "pll_a", &pll_a_params, tegra_clk_pll_a, "pll_ref" },
2628 { "pll_a1", &pll_a1_params, tegra_clk_pll_a1, "pll_ref" },
2631 static const char * const aclk_parents[] = {
2632 "pll_a1", "pll_c", "pll_p", "pll_a_out0", "pll_c2", "pll_c3",
2636 static const unsigned int nvjpg_slcg_clkids[] = { TEGRA210_CLK_NVDEC };
2637 static const unsigned int nvdec_slcg_clkids[] = { TEGRA210_CLK_NVJPG };
2638 static const unsigned int sor_slcg_clkids[] = { TEGRA210_CLK_HDA2CODEC_2X,
2639 TEGRA210_CLK_HDA2HDMI, TEGRA210_CLK_DISP1, TEGRA210_CLK_DISP2 };
2640 static const unsigned int disp_slcg_clkids[] = { TEGRA210_CLK_LA,
2641 TEGRA210_CLK_HOST1X};
2642 static const unsigned int xusba_slcg_clkids[] = { TEGRA210_CLK_XUSB_HOST,
2643 TEGRA210_CLK_XUSB_DEV };
2644 static const unsigned int xusbb_slcg_clkids[] = { TEGRA210_CLK_XUSB_HOST,
2645 TEGRA210_CLK_XUSB_SS };
2646 static const unsigned int xusbc_slcg_clkids[] = { TEGRA210_CLK_XUSB_DEV,
2647 TEGRA210_CLK_XUSB_SS };
2648 static const unsigned int venc_slcg_clkids[] = { TEGRA210_CLK_HOST1X,
2649 TEGRA210_CLK_PLL_D };
2650 static const unsigned int ape_slcg_clkids[] = { TEGRA210_CLK_ACLK,
2651 TEGRA210_CLK_I2S0, TEGRA210_CLK_I2S1, TEGRA210_CLK_I2S2,
2652 TEGRA210_CLK_I2S3, TEGRA210_CLK_I2S4, TEGRA210_CLK_SPDIF_OUT,
2653 TEGRA210_CLK_D_AUDIO };
2654 static const unsigned int vic_slcg_clkids[] = { TEGRA210_CLK_HOST1X };
2656 static struct tegra210_domain_mbist_war tegra210_pg_mbist_war[] = {
2657 [TEGRA_POWERGATE_VENC] = {
2658 .handle_lvl2_ovr = tegra210_venc_mbist_war,
2659 .num_clks = ARRAY_SIZE(venc_slcg_clkids),
2660 .clk_init_data = venc_slcg_clkids,
2662 [TEGRA_POWERGATE_SATA] = {
2663 .handle_lvl2_ovr = tegra210_generic_mbist_war,
2664 .lvl2_offset = LVL2_CLK_GATE_OVRC,
2665 .lvl2_mask = BIT(0) | BIT(17) | BIT(19),
2667 [TEGRA_POWERGATE_MPE] = {
2668 .handle_lvl2_ovr = tegra210_generic_mbist_war,
2669 .lvl2_offset = LVL2_CLK_GATE_OVRE,
2670 .lvl2_mask = BIT(29),
2672 [TEGRA_POWERGATE_SOR] = {
2673 .handle_lvl2_ovr = tegra210_generic_mbist_war,
2674 .num_clks = ARRAY_SIZE(sor_slcg_clkids),
2675 .clk_init_data = sor_slcg_clkids,
2676 .lvl2_offset = LVL2_CLK_GATE_OVRA,
2677 .lvl2_mask = BIT(1) | BIT(2),
2679 [TEGRA_POWERGATE_DIS] = {
2680 .handle_lvl2_ovr = tegra210_disp_mbist_war,
2681 .num_clks = ARRAY_SIZE(disp_slcg_clkids),
2682 .clk_init_data = disp_slcg_clkids,
2684 [TEGRA_POWERGATE_DISB] = {
2685 .num_clks = ARRAY_SIZE(disp_slcg_clkids),
2686 .clk_init_data = disp_slcg_clkids,
2687 .handle_lvl2_ovr = tegra210_generic_mbist_war,
2688 .lvl2_offset = LVL2_CLK_GATE_OVRA,
2689 .lvl2_mask = BIT(2),
2691 [TEGRA_POWERGATE_XUSBA] = {
2692 .num_clks = ARRAY_SIZE(xusba_slcg_clkids),
2693 .clk_init_data = xusba_slcg_clkids,
2694 .handle_lvl2_ovr = tegra210_generic_mbist_war,
2695 .lvl2_offset = LVL2_CLK_GATE_OVRC,
2696 .lvl2_mask = BIT(30) | BIT(31),
2698 [TEGRA_POWERGATE_XUSBB] = {
2699 .num_clks = ARRAY_SIZE(xusbb_slcg_clkids),
2700 .clk_init_data = xusbb_slcg_clkids,
2701 .handle_lvl2_ovr = tegra210_generic_mbist_war,
2702 .lvl2_offset = LVL2_CLK_GATE_OVRC,
2703 .lvl2_mask = BIT(30) | BIT(31),
2705 [TEGRA_POWERGATE_XUSBC] = {
2706 .num_clks = ARRAY_SIZE(xusbc_slcg_clkids),
2707 .clk_init_data = xusbc_slcg_clkids,
2708 .handle_lvl2_ovr = tegra210_generic_mbist_war,
2709 .lvl2_offset = LVL2_CLK_GATE_OVRC,
2710 .lvl2_mask = BIT(30) | BIT(31),
2712 [TEGRA_POWERGATE_VIC] = {
2713 .num_clks = ARRAY_SIZE(vic_slcg_clkids),
2714 .clk_init_data = vic_slcg_clkids,
2715 .handle_lvl2_ovr = tegra210_vic_mbist_war,
2717 [TEGRA_POWERGATE_NVDEC] = {
2718 .num_clks = ARRAY_SIZE(nvdec_slcg_clkids),
2719 .clk_init_data = nvdec_slcg_clkids,
2720 .handle_lvl2_ovr = tegra210_generic_mbist_war,
2721 .lvl2_offset = LVL2_CLK_GATE_OVRE,
2722 .lvl2_mask = BIT(9) | BIT(31),
2724 [TEGRA_POWERGATE_NVJPG] = {
2725 .num_clks = ARRAY_SIZE(nvjpg_slcg_clkids),
2726 .clk_init_data = nvjpg_slcg_clkids,
2727 .handle_lvl2_ovr = tegra210_generic_mbist_war,
2728 .lvl2_offset = LVL2_CLK_GATE_OVRE,
2729 .lvl2_mask = BIT(9) | BIT(31),
2731 [TEGRA_POWERGATE_AUD] = {
2732 .num_clks = ARRAY_SIZE(ape_slcg_clkids),
2733 .clk_init_data = ape_slcg_clkids,
2734 .handle_lvl2_ovr = tegra210_ape_mbist_war,
2736 [TEGRA_POWERGATE_VE2] = {
2737 .handle_lvl2_ovr = tegra210_generic_mbist_war,
2738 .lvl2_offset = LVL2_CLK_GATE_OVRD,
2739 .lvl2_mask = BIT(22),
2743 int tegra210_clk_handle_mbist_war(unsigned int id)
2746 struct tegra210_domain_mbist_war *mbist_war;
2748 if (id >= ARRAY_SIZE(tegra210_pg_mbist_war)) {
2749 WARN(1, "unknown domain id in MBIST WAR handler\n");
2753 mbist_war = &tegra210_pg_mbist_war[id];
2754 if (!mbist_war->handle_lvl2_ovr)
2757 if (mbist_war->num_clks && !mbist_war->clks)
2760 err = clk_bulk_prepare_enable(mbist_war->num_clks, mbist_war->clks);
2764 mutex_lock(&lvl2_ovr_lock);
2766 mbist_war->handle_lvl2_ovr(mbist_war);
2768 mutex_unlock(&lvl2_ovr_lock);
2770 clk_bulk_disable_unprepare(mbist_war->num_clks, mbist_war->clks);
2775 void tegra210_put_utmipll_in_iddq(void)
2779 reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0);
2781 if (reg & UTMIPLL_HW_PWRDN_CFG0_UTMIPLL_LOCK) {
2782 pr_err("trying to assert IDDQ while UTMIPLL is locked\n");
2786 reg |= UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE;
2787 writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0);
2789 EXPORT_SYMBOL_GPL(tegra210_put_utmipll_in_iddq);
2791 void tegra210_put_utmipll_out_iddq(void)
2795 reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0);
2796 reg &= ~UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE;
2797 writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0);
2799 EXPORT_SYMBOL_GPL(tegra210_put_utmipll_out_iddq);
2801 static void tegra210_utmi_param_configure(void)
2806 for (i = 0; i < ARRAY_SIZE(utmi_parameters); i++) {
2807 if (osc_freq == utmi_parameters[i].osc_frequency)
2811 if (i >= ARRAY_SIZE(utmi_parameters)) {
2812 pr_err("%s: Unexpected oscillator freq %lu\n", __func__,
2817 reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0);
2818 reg &= ~UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE;
2819 writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0);
2823 reg = readl_relaxed(clk_base + UTMIP_PLL_CFG2);
2825 /* Program UTMIP PLL stable and active counts */
2826 /* [FIXME] arclk_rst.h says WRONG! This should be 1ms -> 0x50 Check! */
2827 reg &= ~UTMIP_PLL_CFG2_STABLE_COUNT(~0);
2828 reg |= UTMIP_PLL_CFG2_STABLE_COUNT(utmi_parameters[i].stable_count);
2830 reg &= ~UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(~0);
2832 UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(utmi_parameters[i].active_delay_count);
2833 writel_relaxed(reg, clk_base + UTMIP_PLL_CFG2);
2835 /* Program UTMIP PLL delay and oscillator frequency counts */
2836 reg = readl_relaxed(clk_base + UTMIP_PLL_CFG1);
2838 reg &= ~UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(~0);
2840 UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(utmi_parameters[i].enable_delay_count);
2842 reg &= ~UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(~0);
2844 UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(utmi_parameters[i].xtal_freq_count);
2846 reg |= UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN;
2847 writel_relaxed(reg, clk_base + UTMIP_PLL_CFG1);
2849 /* Remove power downs from UTMIP PLL control bits */
2850 reg = readl_relaxed(clk_base + UTMIP_PLL_CFG1);
2851 reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN;
2852 reg |= UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP;
2853 writel_relaxed(reg, clk_base + UTMIP_PLL_CFG1);
2857 /* Enable samplers for SNPS, XUSB_HOST, XUSB_DEV */
2858 reg = readl_relaxed(clk_base + UTMIP_PLL_CFG2);
2859 reg |= UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERUP;
2860 reg |= UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERUP;
2861 reg |= UTMIP_PLL_CFG2_FORCE_PD_SAMP_D_POWERUP;
2862 reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN;
2863 reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN;
2864 reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_D_POWERDOWN;
2865 writel_relaxed(reg, clk_base + UTMIP_PLL_CFG2);
2867 /* Setup HW control of UTMIPLL */
2868 reg = readl_relaxed(clk_base + UTMIP_PLL_CFG1);
2869 reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN;
2870 reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP;
2871 writel_relaxed(reg, clk_base + UTMIP_PLL_CFG1);
2873 reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0);
2874 reg |= UTMIPLL_HW_PWRDN_CFG0_USE_LOCKDET;
2875 reg &= ~UTMIPLL_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL;
2876 writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0);
2880 reg = readl_relaxed(clk_base + XUSB_PLL_CFG0);
2881 reg &= ~XUSB_PLL_CFG0_UTMIPLL_LOCK_DLY;
2882 writel_relaxed(reg, clk_base + XUSB_PLL_CFG0);
2886 /* Enable HW control UTMIPLL */
2887 reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0);
2888 reg |= UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE;
2889 writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0);
2892 static int tegra210_enable_pllu(void)
2894 struct tegra_clk_pll_freq_table *fentry;
2895 struct tegra_clk_pll pllu;
2899 for (fentry = pll_u_freq_table; fentry->input_rate; fentry++) {
2900 if (fentry->input_rate == pll_ref_freq)
2904 if (!fentry->input_rate) {
2905 pr_err("Unknown PLL_U reference frequency %lu\n", pll_ref_freq);
2909 /* clear IDDQ bit */
2910 pllu.params = &pll_u_vco_params;
2911 reg = readl_relaxed(clk_base + pllu.params->ext_misc_reg[0]);
2912 reg &= ~BIT(pllu.params->iddq_bit_idx);
2913 writel_relaxed(reg, clk_base + pllu.params->ext_misc_reg[0]);
2914 fence_udelay(5, clk_base);
2916 reg = readl_relaxed(clk_base + PLLU_BASE);
2917 reg &= ~GENMASK(20, 0);
2919 reg |= fentry->n << 8;
2920 reg |= fentry->p << 16;
2921 writel(reg, clk_base + PLLU_BASE);
2922 fence_udelay(1, clk_base);
2924 writel(reg, clk_base + PLLU_BASE);
2927 * During clocks resume, same PLLU init and enable sequence get
2928 * executed. So, readx_poll_timeout_atomic can't be used here as it
2929 * uses ktime_get() and timekeeping resume doesn't happen by that
2930 * time. So, using tegra210_wait_for_mask for PLL LOCK.
2932 ret = tegra210_wait_for_mask(&pllu, PLLU_BASE, PLL_BASE_LOCK);
2934 pr_err("Timed out waiting for PLL_U to lock\n");
2941 static int tegra210_init_pllu(void)
2946 tegra210_pllu_set_defaults(&pll_u_vco_params);
2947 /* skip initialization when pllu is in hw controlled mode */
2948 reg = readl_relaxed(clk_base + PLLU_BASE);
2949 if (reg & PLLU_BASE_OVERRIDE) {
2950 if (!(reg & PLL_ENABLE)) {
2951 err = tegra210_enable_pllu();
2957 /* enable hw controlled mode */
2958 reg = readl_relaxed(clk_base + PLLU_BASE);
2959 reg &= ~PLLU_BASE_OVERRIDE;
2960 writel(reg, clk_base + PLLU_BASE);
2962 reg = readl_relaxed(clk_base + PLLU_HW_PWRDN_CFG0);
2963 reg |= PLLU_HW_PWRDN_CFG0_IDDQ_PD_INCLUDE |
2964 PLLU_HW_PWRDN_CFG0_USE_SWITCH_DETECT |
2965 PLLU_HW_PWRDN_CFG0_USE_LOCKDET;
2966 reg &= ~(PLLU_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL |
2967 PLLU_HW_PWRDN_CFG0_CLK_SWITCH_SWCTL);
2968 writel_relaxed(reg, clk_base + PLLU_HW_PWRDN_CFG0);
2970 reg = readl_relaxed(clk_base + XUSB_PLL_CFG0);
2971 reg &= ~XUSB_PLL_CFG0_PLLU_LOCK_DLY_MASK;
2972 writel_relaxed(reg, clk_base + XUSB_PLL_CFG0);
2973 fence_udelay(1, clk_base);
2975 reg = readl_relaxed(clk_base + PLLU_HW_PWRDN_CFG0);
2976 reg |= PLLU_HW_PWRDN_CFG0_SEQ_ENABLE;
2977 writel_relaxed(reg, clk_base + PLLU_HW_PWRDN_CFG0);
2978 fence_udelay(1, clk_base);
2980 reg = readl_relaxed(clk_base + PLLU_BASE);
2981 reg &= ~PLLU_BASE_CLKENABLE_USB;
2982 writel_relaxed(reg, clk_base + PLLU_BASE);
2985 /* enable UTMIPLL hw control if not yet done by the bootloader */
2986 reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0);
2987 if (!(reg & UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE))
2988 tegra210_utmi_param_configure();
2994 * The SOR hardware blocks are driven by two clocks: a module clock that is
2995 * used to access registers and a pixel clock that is sourced from the same
2996 * pixel clock that also drives the head attached to the SOR. The module
2997 * clock is typically called sorX (with X being the SOR instance) and the
2998 * pixel clock is called sorX_out. The source for the SOR pixel clock is
2999 * referred to as the "parent" clock.
3001 * On Tegra186 and newer, clocks are provided by the BPMP. Unfortunately the
3002 * BPMP implementation for the SOR clocks doesn't exactly match the above in
3003 * some aspects. For example, the SOR module is really clocked by the pad or
3004 * sor_safe clocks, but BPMP models the sorX clock as being sourced by the
3005 * pixel clocks. Conversely the sorX_out clock is sourced by the sor_safe or
3006 * pad clocks on BPMP.
3008 * In order to allow the display driver to deal with all SoC generations in
3009 * a unified way, implement the BPMP semantics in this driver.
3012 static const char * const sor0_parents[] = {
3016 static const char * const sor0_out_parents[] = {
3017 "sor_safe", "sor0_pad_clkout",
3020 static const char * const sor1_parents[] = {
3021 "pll_p", "pll_d_out0", "pll_d2_out0", "clk_m",
3024 static u32 sor1_parents_idx[] = { 0, 2, 5, 6 };
3026 static const struct clk_div_table mc_div_table_tegra210[] = {
3027 { .val = 0, .div = 2 },
3028 { .val = 1, .div = 4 },
3029 { .val = 2, .div = 1 },
3030 { .val = 3, .div = 2 },
3031 { .val = 0, .div = 0 },
3034 static void tegra210_clk_register_mc(const char *name,
3035 const char *parent_name)
3039 clk = clk_register_divider_table(NULL, name, parent_name,
3041 clk_base + CLK_SOURCE_EMC,
3042 15, 2, CLK_DIVIDER_READ_ONLY,
3043 mc_div_table_tegra210, &emc_lock);
3044 clks[TEGRA210_CLK_MC] = clk;
3047 static const char * const sor1_out_parents[] = {
3049 * Bit 0 of the mux selects sor1_pad_clkout, irrespective of bit 1, so
3050 * the sor1_pad_clkout parent appears twice in the list below. This is
3051 * merely to support clk_get_parent() if firmware happened to set
3052 * these bits to 0b11. While not an invalid setting, code should
3053 * always set the bits to 0b01 to select sor1_pad_clkout.
3055 "sor_safe", "sor1_pad_clkout", "sor1_out", "sor1_pad_clkout",
3058 static struct tegra_periph_init_data tegra210_periph[] = {
3060 * On Tegra210, the sor0 clock doesn't have a mux it bitfield 31:29,
3061 * but it is hardwired to the pll_d_out0 clock.
3063 TEGRA_INIT_DATA_TABLE("sor0", NULL, NULL, sor0_parents,
3064 CLK_SOURCE_SOR0, 29, 0x0, 0, 0, 0, 0,
3065 0, 182, 0, tegra_clk_sor0, NULL, 0,
3067 TEGRA_INIT_DATA_TABLE("sor0_out", NULL, NULL, sor0_out_parents,
3068 CLK_SOURCE_SOR0, 14, 0x1, 0, 0, 0, 0,
3069 0, 0, TEGRA_PERIPH_NO_GATE, tegra_clk_sor0_out,
3070 NULL, 0, &sor0_lock),
3071 TEGRA_INIT_DATA_TABLE("sor1", NULL, NULL, sor1_parents,
3072 CLK_SOURCE_SOR1, 29, 0x7, 0, 0, 8, 1,
3073 TEGRA_DIVIDER_ROUND_UP, 183, 0,
3074 tegra_clk_sor1, sor1_parents_idx, 0,
3076 TEGRA_INIT_DATA_TABLE("sor1_out", NULL, NULL, sor1_out_parents,
3077 CLK_SOURCE_SOR1, 14, 0x3, 0, 0, 0, 0,
3078 0, 0, TEGRA_PERIPH_NO_GATE,
3079 tegra_clk_sor1_out, NULL, 0, &sor1_lock),
3082 static const char * const la_parents[] = {
3083 "pll_p", "pll_c2", "pll_c", "pll_c3", "pll_re_out1", "pll_a1", "clk_m", "pll_c4_out0"
3086 static struct tegra_clk_periph tegra210_la =
3087 TEGRA_CLK_PERIPH(29, 7, 9, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP, 76, 0, NULL, NULL);
3089 static __init void tegra210_periph_clk_init(struct device_node *np,
3090 void __iomem *clk_base,
3091 void __iomem *pmc_base)
3097 clk = clk_register_fixed_factor(NULL, "xusb_ss_div2", "xusb_ss_src", 0,
3099 clks[TEGRA210_CLK_XUSB_SS_DIV2] = clk;
3101 clk = tegra_clk_register_periph_fixed("sor_safe", "pll_p", 0, clk_base,
3103 clks[TEGRA210_CLK_SOR_SAFE] = clk;
3105 clk = tegra_clk_register_periph_fixed("dpaux", "sor_safe", 0, clk_base,
3107 clks[TEGRA210_CLK_DPAUX] = clk;
3109 clk = tegra_clk_register_periph_fixed("dpaux1", "sor_safe", 0, clk_base,
3111 clks[TEGRA210_CLK_DPAUX1] = clk;
3114 clk = clk_register_gate(NULL, "pll_d_dsi_out", "pll_d_out0", 0,
3115 clk_base + PLLD_MISC0, 21, 0, &pll_d_lock);
3116 clks[TEGRA210_CLK_PLL_D_DSI_OUT] = clk;
3119 clk = tegra_clk_register_periph_gate("dsia", "pll_d_dsi_out", 0,
3121 periph_clk_enb_refcnt);
3122 clks[TEGRA210_CLK_DSIA] = clk;
3125 clk = tegra_clk_register_periph_gate("dsib", "pll_d_dsi_out", 0,
3127 periph_clk_enb_refcnt);
3128 clks[TEGRA210_CLK_DSIB] = clk;
3131 clk = clk_register_gate(NULL, "csi_tpg", "pll_d",
3132 CLK_SET_RATE_PARENT, clk_base + PLLD_BASE,
3133 23, 0, &pll_d_lock);
3134 clk_register_clkdev(clk, "csi_tpg", NULL);
3135 clks[TEGRA210_CLK_CSI_TPG] = clk;
3138 clk = tegra_clk_register_periph("la", la_parents,
3139 ARRAY_SIZE(la_parents), &tegra210_la, clk_base,
3141 clks[TEGRA210_CLK_LA] = clk;
3144 clk = clk_register_gate(NULL, "cml0", "pll_e", 0, clk_base + PLLE_AUX,
3146 clk_register_clkdev(clk, "cml0", NULL);
3147 clks[TEGRA210_CLK_CML0] = clk;
3150 clk = clk_register_gate(NULL, "cml1", "pll_e", 0, clk_base + PLLE_AUX,
3152 clk_register_clkdev(clk, "cml1", NULL);
3153 clks[TEGRA210_CLK_CML1] = clk;
3155 clk = tegra_clk_register_super_clk("aclk", aclk_parents,
3156 ARRAY_SIZE(aclk_parents), 0, clk_base + 0x6e0,
3158 clks[TEGRA210_CLK_ACLK] = clk;
3160 clk = tegra_clk_register_sdmmc_mux_div("sdmmc2", clk_base,
3161 CLK_SOURCE_SDMMC2, 9,
3162 TEGRA_DIVIDER_ROUND_UP, 0, NULL);
3163 clks[TEGRA210_CLK_SDMMC2] = clk;
3165 clk = tegra_clk_register_sdmmc_mux_div("sdmmc4", clk_base,
3166 CLK_SOURCE_SDMMC4, 15,
3167 TEGRA_DIVIDER_ROUND_UP, 0, NULL);
3168 clks[TEGRA210_CLK_SDMMC4] = clk;
3170 for (i = 0; i < ARRAY_SIZE(tegra210_periph); i++) {
3171 struct tegra_periph_init_data *init = &tegra210_periph[i];
3174 clkp = tegra_lookup_dt_id(init->clk_id, tegra210_clks);
3176 pr_warn("clock %u not found\n", init->clk_id);
3180 clk = tegra_clk_register_periph_data(clk_base, init);
3184 tegra_periph_clk_init(clk_base, pmc_base, tegra210_clks, &pll_p_params);
3187 clk = tegra210_clk_register_emc(np, clk_base);
3188 clks[TEGRA210_CLK_EMC] = clk;
3191 tegra210_clk_register_mc("mc", "emc");
3194 static void __init tegra210_pll_init(void __iomem *clk_base,
3200 clk = tegra_clk_register_pllc_tegra210("pll_c", "pll_ref", clk_base,
3201 pmc, 0, &pll_c_params, NULL);
3202 if (!WARN_ON(IS_ERR(clk)))
3203 clk_register_clkdev(clk, "pll_c", NULL);
3204 clks[TEGRA210_CLK_PLL_C] = clk;
3207 clk = tegra_clk_register_divider("pll_c_out1_div", "pll_c",
3208 clk_base + PLLC_OUT, 0, TEGRA_DIVIDER_ROUND_UP,
3210 clk = tegra_clk_register_pll_out("pll_c_out1", "pll_c_out1_div",
3211 clk_base + PLLC_OUT, 1, 0,
3212 CLK_SET_RATE_PARENT, 0, NULL);
3213 clk_register_clkdev(clk, "pll_c_out1", NULL);
3214 clks[TEGRA210_CLK_PLL_C_OUT1] = clk;
3217 clk = clk_register_fixed_factor(NULL, "pll_c_ud", "pll_c",
3218 CLK_SET_RATE_PARENT, 1, 1);
3219 clk_register_clkdev(clk, "pll_c_ud", NULL);
3220 clks[TEGRA210_CLK_PLL_C_UD] = clk;
3223 clk = tegra_clk_register_pllc_tegra210("pll_c2", "pll_ref", clk_base,
3224 pmc, 0, &pll_c2_params, NULL);
3225 clk_register_clkdev(clk, "pll_c2", NULL);
3226 clks[TEGRA210_CLK_PLL_C2] = clk;
3229 clk = tegra_clk_register_pllc_tegra210("pll_c3", "pll_ref", clk_base,
3230 pmc, 0, &pll_c3_params, NULL);
3231 clk_register_clkdev(clk, "pll_c3", NULL);
3232 clks[TEGRA210_CLK_PLL_C3] = clk;
3235 clk = tegra_clk_register_pllm("pll_m", "osc", clk_base, pmc,
3236 CLK_SET_RATE_GATE, &pll_m_params, NULL);
3237 clk_register_clkdev(clk, "pll_m", NULL);
3238 clks[TEGRA210_CLK_PLL_M] = clk;
3241 clk = tegra_clk_register_pllmb("pll_mb", "osc", clk_base, pmc,
3242 CLK_SET_RATE_GATE, &pll_mb_params, NULL);
3243 clk_register_clkdev(clk, "pll_mb", NULL);
3244 clks[TEGRA210_CLK_PLL_MB] = clk;
3247 clk = clk_register_fixed_factor(NULL, "pll_m_ud", "pll_m",
3248 CLK_SET_RATE_PARENT, 1, 1);
3249 clk_register_clkdev(clk, "pll_m_ud", NULL);
3250 clks[TEGRA210_CLK_PLL_M_UD] = clk;
3253 clk = clk_register_fixed_factor(NULL, "pll_mb_ud", "pll_mb",
3254 CLK_SET_RATE_PARENT, 1, 1);
3255 clk_register_clkdev(clk, "pll_mb_ud", NULL);
3256 clks[TEGRA210_CLK_PLL_MB_UD] = clk;
3259 clk = clk_register_fixed_factor(NULL, "pll_p_ud", "pll_p",
3261 clks[TEGRA210_CLK_PLL_P_UD] = clk;
3264 if (!tegra210_init_pllu()) {
3265 clk = clk_register_fixed_rate(NULL, "pll_u_vco", "pll_ref", 0,
3267 clk_register_clkdev(clk, "pll_u_vco", NULL);
3268 clks[TEGRA210_CLK_PLL_U] = clk;
3272 clk = clk_register_divider_table(NULL, "pll_u_out", "pll_u_vco", 0,
3273 clk_base + PLLU_BASE, 16, 4, 0,
3274 pll_vco_post_div_table, NULL);
3275 clk_register_clkdev(clk, "pll_u_out", NULL);
3276 clks[TEGRA210_CLK_PLL_U_OUT] = clk;
3279 clk = tegra_clk_register_divider("pll_u_out1_div", "pll_u_out",
3280 clk_base + PLLU_OUTA, 0,
3281 TEGRA_DIVIDER_ROUND_UP,
3282 8, 8, 1, &pll_u_lock);
3283 clk = tegra_clk_register_pll_out("pll_u_out1", "pll_u_out1_div",
3284 clk_base + PLLU_OUTA, 1, 0,
3285 CLK_SET_RATE_PARENT, 0, &pll_u_lock);
3286 clk_register_clkdev(clk, "pll_u_out1", NULL);
3287 clks[TEGRA210_CLK_PLL_U_OUT1] = clk;
3290 clk = tegra_clk_register_divider("pll_u_out2_div", "pll_u_out",
3291 clk_base + PLLU_OUTA, 0,
3292 TEGRA_DIVIDER_ROUND_UP,
3293 24, 8, 1, &pll_u_lock);
3294 clk = tegra_clk_register_pll_out("pll_u_out2", "pll_u_out2_div",
3295 clk_base + PLLU_OUTA, 17, 16,
3296 CLK_SET_RATE_PARENT, 0, &pll_u_lock);
3297 clk_register_clkdev(clk, "pll_u_out2", NULL);
3298 clks[TEGRA210_CLK_PLL_U_OUT2] = clk;
3301 clk = clk_register_gate(NULL, "pll_u_480M", "pll_u_vco",
3302 CLK_SET_RATE_PARENT, clk_base + PLLU_BASE,
3303 22, 0, &pll_u_lock);
3304 clk_register_clkdev(clk, "pll_u_480M", NULL);
3305 clks[TEGRA210_CLK_PLL_U_480M] = clk;
3308 clk = clk_register_gate(NULL, "pll_u_60M", "pll_u_out2",
3309 CLK_SET_RATE_PARENT, clk_base + PLLU_BASE,
3310 23, 0, &pll_u_lock);
3311 clk_register_clkdev(clk, "pll_u_60M", NULL);
3312 clks[TEGRA210_CLK_PLL_U_60M] = clk;
3315 clk = clk_register_gate(NULL, "pll_u_48M", "pll_u_out1",
3316 CLK_SET_RATE_PARENT, clk_base + PLLU_BASE,
3317 25, 0, &pll_u_lock);
3318 clk_register_clkdev(clk, "pll_u_48M", NULL);
3319 clks[TEGRA210_CLK_PLL_U_48M] = clk;
3322 clk = tegra_clk_register_pll("pll_d", "pll_ref", clk_base, pmc, 0,
3323 &pll_d_params, &pll_d_lock);
3324 clk_register_clkdev(clk, "pll_d", NULL);
3325 clks[TEGRA210_CLK_PLL_D] = clk;
3328 clk = clk_register_fixed_factor(NULL, "pll_d_out0", "pll_d",
3329 CLK_SET_RATE_PARENT, 1, 2);
3330 clk_register_clkdev(clk, "pll_d_out0", NULL);
3331 clks[TEGRA210_CLK_PLL_D_OUT0] = clk;
3334 clk = tegra_clk_register_pllre_tegra210("pll_re_vco", "pll_ref",
3337 &pll_re_lock, pll_ref_freq);
3338 clk_register_clkdev(clk, "pll_re_vco", NULL);
3339 clks[TEGRA210_CLK_PLL_RE_VCO] = clk;
3341 clk = clk_register_divider_table(NULL, "pll_re_out", "pll_re_vco", 0,
3342 clk_base + PLLRE_BASE, 16, 5, 0,
3343 pll_vco_post_div_table, &pll_re_lock);
3344 clk_register_clkdev(clk, "pll_re_out", NULL);
3345 clks[TEGRA210_CLK_PLL_RE_OUT] = clk;
3347 clk = tegra_clk_register_divider("pll_re_out1_div", "pll_re_vco",
3348 clk_base + PLLRE_OUT1, 0,
3349 TEGRA_DIVIDER_ROUND_UP,
3351 clk = tegra_clk_register_pll_out("pll_re_out1", "pll_re_out1_div",
3352 clk_base + PLLRE_OUT1, 1, 0,
3353 CLK_SET_RATE_PARENT, 0, NULL);
3354 clks[TEGRA210_CLK_PLL_RE_OUT1] = clk;
3357 clk = tegra_clk_register_plle_tegra210("pll_e", "pll_ref",
3358 clk_base, 0, &pll_e_params, NULL);
3359 clk_register_clkdev(clk, "pll_e", NULL);
3360 clks[TEGRA210_CLK_PLL_E] = clk;
3363 clk = tegra_clk_register_pllre("pll_c4_vco", "pll_ref", clk_base, pmc,
3364 0, &pll_c4_vco_params, NULL, pll_ref_freq);
3365 clk_register_clkdev(clk, "pll_c4_vco", NULL);
3366 clks[TEGRA210_CLK_PLL_C4] = clk;
3369 clk = clk_register_divider_table(NULL, "pll_c4_out0", "pll_c4_vco", 0,
3370 clk_base + PLLC4_BASE, 19, 4, 0,
3371 pll_vco_post_div_table, NULL);
3372 clk_register_clkdev(clk, "pll_c4_out0", NULL);
3373 clks[TEGRA210_CLK_PLL_C4_OUT0] = clk;
3376 clk = clk_register_fixed_factor(NULL, "pll_c4_out1", "pll_c4_vco",
3377 CLK_SET_RATE_PARENT, 1, 3);
3378 clk_register_clkdev(clk, "pll_c4_out1", NULL);
3379 clks[TEGRA210_CLK_PLL_C4_OUT1] = clk;
3382 clk = clk_register_fixed_factor(NULL, "pll_c4_out2", "pll_c4_vco",
3383 CLK_SET_RATE_PARENT, 1, 5);
3384 clk_register_clkdev(clk, "pll_c4_out2", NULL);
3385 clks[TEGRA210_CLK_PLL_C4_OUT2] = clk;
3388 clk = tegra_clk_register_divider("pll_c4_out3_div", "pll_c4_out0",
3389 clk_base + PLLC4_OUT, 0, TEGRA_DIVIDER_ROUND_UP,
3391 clk = tegra_clk_register_pll_out("pll_c4_out3", "pll_c4_out3_div",
3392 clk_base + PLLC4_OUT, 1, 0,
3393 CLK_SET_RATE_PARENT, 0, NULL);
3394 clk_register_clkdev(clk, "pll_c4_out3", NULL);
3395 clks[TEGRA210_CLK_PLL_C4_OUT3] = clk;
3398 clk = tegra_clk_register_pllss_tegra210("pll_dp", "pll_ref", clk_base,
3399 0, &pll_dp_params, NULL);
3400 clk_register_clkdev(clk, "pll_dp", NULL);
3401 clks[TEGRA210_CLK_PLL_DP] = clk;
3404 clk = tegra_clk_register_pllss_tegra210("pll_d2", "pll_ref", clk_base,
3405 0, &pll_d2_params, NULL);
3406 clk_register_clkdev(clk, "pll_d2", NULL);
3407 clks[TEGRA210_CLK_PLL_D2] = clk;
3410 clk = clk_register_fixed_factor(NULL, "pll_d2_out0", "pll_d2",
3411 CLK_SET_RATE_PARENT, 1, 1);
3412 clk_register_clkdev(clk, "pll_d2_out0", NULL);
3413 clks[TEGRA210_CLK_PLL_D2_OUT0] = clk;
3416 clk = clk_register_fixed_factor(NULL, "pll_p_out2", "pll_p",
3417 CLK_SET_RATE_PARENT, 1, 2);
3418 clk_register_clkdev(clk, "pll_p_out2", NULL);
3419 clks[TEGRA210_CLK_PLL_P_OUT2] = clk;
3423 /* Tegra210 CPU clock and reset control functions */
3424 static void tegra210_wait_cpu_in_reset(u32 cpu)
3429 reg = readl(clk_base + CLK_RST_CONTROLLER_CPU_CMPLX_STATUS);
3431 } while (!(reg & (1 << cpu))); /* check CPU been reset or not */
3434 static void tegra210_disable_cpu_clock(u32 cpu)
3436 /* flow controller would take care in the power sequence. */
3439 #ifdef CONFIG_PM_SLEEP
3440 #define car_readl(_base, _off) readl_relaxed(clk_base + (_base) + ((_off) * 4))
3441 #define car_writel(_val, _base, _off) \
3442 writel_relaxed(_val, clk_base + (_base) + ((_off) * 4))
3444 static u32 spare_reg_ctx, misc_clk_enb_ctx, clk_msk_arm_ctx;
3445 static u32 cpu_softrst_ctx[3];
3447 static int tegra210_clk_suspend(void)
3454 * Save the bootloader configured clock registers SPARE_REG0,
3455 * MISC_CLK_ENB, CLK_MASK_ARM, CPU_SOFTRST_CTRL.
3457 spare_reg_ctx = readl_relaxed(clk_base + SPARE_REG0);
3458 misc_clk_enb_ctx = readl_relaxed(clk_base + MISC_CLK_ENB);
3459 clk_msk_arm_ctx = readl_relaxed(clk_base + CLK_MASK_ARM);
3461 for (i = 0; i < ARRAY_SIZE(cpu_softrst_ctx); i++)
3462 cpu_softrst_ctx[i] = car_readl(CPU_SOFTRST_CTRL, i);
3464 tegra_clk_periph_suspend();
3468 static void tegra210_clk_resume(void)
3472 tegra_clk_osc_resume(clk_base);
3475 * Restore the bootloader configured clock registers SPARE_REG0,
3476 * MISC_CLK_ENB, CLK_MASK_ARM, CPU_SOFTRST_CTRL from saved context.
3478 writel_relaxed(spare_reg_ctx, clk_base + SPARE_REG0);
3479 writel_relaxed(misc_clk_enb_ctx, clk_base + MISC_CLK_ENB);
3480 writel_relaxed(clk_msk_arm_ctx, clk_base + CLK_MASK_ARM);
3482 for (i = 0; i < ARRAY_SIZE(cpu_softrst_ctx); i++)
3483 car_writel(cpu_softrst_ctx[i], CPU_SOFTRST_CTRL, i);
3486 * Tegra clock programming sequence recommends peripheral clock to
3487 * be enabled prior to changing its clock source and divider to
3488 * prevent glitchless frequency switch.
3489 * So, enable all peripheral clocks before restoring their source
3492 writel_relaxed(TEGRA210_CLK_ENB_VLD_MSK_L, clk_base + CLK_OUT_ENB_L);
3493 writel_relaxed(TEGRA210_CLK_ENB_VLD_MSK_H, clk_base + CLK_OUT_ENB_H);
3494 writel_relaxed(TEGRA210_CLK_ENB_VLD_MSK_U, clk_base + CLK_OUT_ENB_U);
3495 writel_relaxed(TEGRA210_CLK_ENB_VLD_MSK_V, clk_base + CLK_OUT_ENB_V);
3496 writel_relaxed(TEGRA210_CLK_ENB_VLD_MSK_W, clk_base + CLK_OUT_ENB_W);
3497 writel_relaxed(TEGRA210_CLK_ENB_VLD_MSK_X, clk_base + CLK_OUT_ENB_X);
3498 writel_relaxed(TEGRA210_CLK_ENB_VLD_MSK_Y, clk_base + CLK_OUT_ENB_Y);
3500 /* wait for all writes to happen to have all the clocks enabled */
3501 fence_udelay(2, clk_base);
3503 /* restore PLLs and all peripheral clock rates */
3504 tegra210_init_pllu();
3505 clk_restore_context();
3507 /* restore saved context of peripheral clocks and reset state */
3508 tegra_clk_periph_resume();
3511 static void tegra210_cpu_clock_suspend(void)
3513 /* switch coresite to clk_m, save off original source */
3514 tegra210_cpu_clk_sctx.clk_csite_src =
3515 readl(clk_base + CLK_SOURCE_CSITE);
3516 writel(3 << 30, clk_base + CLK_SOURCE_CSITE);
3519 static void tegra210_cpu_clock_resume(void)
3521 writel(tegra210_cpu_clk_sctx.clk_csite_src,
3522 clk_base + CLK_SOURCE_CSITE);
3526 static struct syscore_ops tegra_clk_syscore_ops = {
3527 #ifdef CONFIG_PM_SLEEP
3528 .suspend = tegra210_clk_suspend,
3529 .resume = tegra210_clk_resume,
3533 static struct tegra_cpu_car_ops tegra210_cpu_car_ops = {
3534 .wait_for_reset = tegra210_wait_cpu_in_reset,
3535 .disable_clock = tegra210_disable_cpu_clock,
3536 #ifdef CONFIG_PM_SLEEP
3537 .suspend = tegra210_cpu_clock_suspend,
3538 .resume = tegra210_cpu_clock_resume,
3542 static const struct of_device_id pmc_match[] __initconst = {
3543 { .compatible = "nvidia,tegra210-pmc" },
3547 static struct tegra_clk_init_table init_table[] __initdata = {
3548 { TEGRA210_CLK_UARTA, TEGRA210_CLK_PLL_P, 408000000, 0 },
3549 { TEGRA210_CLK_UARTB, TEGRA210_CLK_PLL_P, 408000000, 0 },
3550 { TEGRA210_CLK_UARTC, TEGRA210_CLK_PLL_P, 408000000, 0 },
3551 { TEGRA210_CLK_UARTD, TEGRA210_CLK_PLL_P, 408000000, 0 },
3552 { TEGRA210_CLK_PLL_A, TEGRA210_CLK_CLK_MAX, 564480000, 0 },
3553 { TEGRA210_CLK_PLL_A_OUT0, TEGRA210_CLK_CLK_MAX, 11289600, 0 },
3554 { TEGRA210_CLK_I2S0, TEGRA210_CLK_PLL_A_OUT0, 11289600, 0 },
3555 { TEGRA210_CLK_I2S1, TEGRA210_CLK_PLL_A_OUT0, 11289600, 0 },
3556 { TEGRA210_CLK_I2S2, TEGRA210_CLK_PLL_A_OUT0, 11289600, 0 },
3557 { TEGRA210_CLK_I2S3, TEGRA210_CLK_PLL_A_OUT0, 11289600, 0 },
3558 { TEGRA210_CLK_I2S4, TEGRA210_CLK_PLL_A_OUT0, 11289600, 0 },
3559 { TEGRA210_CLK_HOST1X, TEGRA210_CLK_PLL_P, 136000000, 1 },
3560 { TEGRA210_CLK_SCLK_MUX, TEGRA210_CLK_PLL_P, 0, 1 },
3561 { TEGRA210_CLK_SCLK, TEGRA210_CLK_CLK_MAX, 102000000, 0 },
3562 { TEGRA210_CLK_DFLL_SOC, TEGRA210_CLK_PLL_P, 51000000, 1 },
3563 { TEGRA210_CLK_DFLL_REF, TEGRA210_CLK_PLL_P, 51000000, 1 },
3564 { TEGRA210_CLK_SBC4, TEGRA210_CLK_PLL_P, 12000000, 1 },
3565 { TEGRA210_CLK_PLL_U_OUT1, TEGRA210_CLK_CLK_MAX, 48000000, 1 },
3566 { TEGRA210_CLK_XUSB_GATE, TEGRA210_CLK_CLK_MAX, 0, 1 },
3567 { TEGRA210_CLK_XUSB_SS_SRC, TEGRA210_CLK_PLL_U_480M, 120000000, 0 },
3568 { TEGRA210_CLK_XUSB_FS_SRC, TEGRA210_CLK_PLL_U_48M, 48000000, 0 },
3569 { TEGRA210_CLK_XUSB_HS_SRC, TEGRA210_CLK_XUSB_SS_SRC, 120000000, 0 },
3570 { TEGRA210_CLK_XUSB_SSP_SRC, TEGRA210_CLK_XUSB_SS_SRC, 120000000, 0 },
3571 { TEGRA210_CLK_XUSB_FALCON_SRC, TEGRA210_CLK_PLL_P_OUT_XUSB, 204000000, 0 },
3572 { TEGRA210_CLK_XUSB_HOST_SRC, TEGRA210_CLK_PLL_P_OUT_XUSB, 102000000, 0 },
3573 { TEGRA210_CLK_XUSB_DEV_SRC, TEGRA210_CLK_PLL_P_OUT_XUSB, 102000000, 0 },
3574 { TEGRA210_CLK_SATA, TEGRA210_CLK_PLL_P, 104000000, 0 },
3575 { TEGRA210_CLK_SATA_OOB, TEGRA210_CLK_PLL_P, 204000000, 0 },
3576 { TEGRA210_CLK_MSELECT, TEGRA210_CLK_CLK_MAX, 0, 1 },
3577 { TEGRA210_CLK_CSITE, TEGRA210_CLK_CLK_MAX, 0, 1 },
3578 /* TODO find a way to enable this on-demand */
3579 { TEGRA210_CLK_DBGAPB, TEGRA210_CLK_CLK_MAX, 0, 1 },
3580 { TEGRA210_CLK_TSENSOR, TEGRA210_CLK_CLK_M, 400000, 0 },
3581 { TEGRA210_CLK_I2C1, TEGRA210_CLK_PLL_P, 0, 0 },
3582 { TEGRA210_CLK_I2C2, TEGRA210_CLK_PLL_P, 0, 0 },
3583 { TEGRA210_CLK_I2C3, TEGRA210_CLK_PLL_P, 0, 0 },
3584 { TEGRA210_CLK_I2C4, TEGRA210_CLK_PLL_P, 0, 0 },
3585 { TEGRA210_CLK_I2C5, TEGRA210_CLK_PLL_P, 0, 0 },
3586 { TEGRA210_CLK_I2C6, TEGRA210_CLK_PLL_P, 0, 0 },
3587 { TEGRA210_CLK_PLL_DP, TEGRA210_CLK_CLK_MAX, 270000000, 0 },
3588 { TEGRA210_CLK_SOC_THERM, TEGRA210_CLK_PLL_P, 51000000, 0 },
3589 { TEGRA210_CLK_CCLK_G, TEGRA210_CLK_CLK_MAX, 0, 1 },
3590 { TEGRA210_CLK_PLL_U_OUT2, TEGRA210_CLK_CLK_MAX, 60000000, 1 },
3591 { TEGRA210_CLK_SPDIF_IN_SYNC, TEGRA210_CLK_CLK_MAX, 24576000, 0 },
3592 { TEGRA210_CLK_I2S0_SYNC, TEGRA210_CLK_CLK_MAX, 24576000, 0 },
3593 { TEGRA210_CLK_I2S1_SYNC, TEGRA210_CLK_CLK_MAX, 24576000, 0 },
3594 { TEGRA210_CLK_I2S2_SYNC, TEGRA210_CLK_CLK_MAX, 24576000, 0 },
3595 { TEGRA210_CLK_I2S3_SYNC, TEGRA210_CLK_CLK_MAX, 24576000, 0 },
3596 { TEGRA210_CLK_I2S4_SYNC, TEGRA210_CLK_CLK_MAX, 24576000, 0 },
3597 { TEGRA210_CLK_VIMCLK_SYNC, TEGRA210_CLK_CLK_MAX, 24576000, 0 },
3598 { TEGRA210_CLK_HDA, TEGRA210_CLK_PLL_P, 51000000, 0 },
3599 { TEGRA210_CLK_HDA2CODEC_2X, TEGRA210_CLK_PLL_P, 48000000, 0 },
3600 /* This MUST be the last entry. */
3601 { TEGRA210_CLK_CLK_MAX, TEGRA210_CLK_CLK_MAX, 0, 0 },
3605 * tegra210_clock_apply_init_table - initialize clocks on Tegra210 SoCs
3607 * Program an initial clock rate and enable or disable clocks needed
3608 * by the rest of the kernel, for Tegra210 SoCs. It is intended to be
3609 * called by assigning a pointer to it to tegra_clk_apply_init_table -
3610 * this will be called as an arch_initcall. No return value.
3612 static void __init tegra210_clock_apply_init_table(void)
3614 tegra_init_from_table(init_table, clks, TEGRA210_CLK_CLK_MAX);
3618 * tegra210_car_barrier - wait for pending writes to the CAR to complete
3620 * Wait for any outstanding writes to the CAR MMIO space from this CPU
3621 * to complete before continuing execution. No return value.
3623 static void tegra210_car_barrier(void)
3625 readl_relaxed(clk_base + RST_DFLL_DVCO);
3629 * tegra210_clock_assert_dfll_dvco_reset - assert the DFLL's DVCO reset
3631 * Assert the reset line of the DFLL's DVCO. No return value.
3633 static void tegra210_clock_assert_dfll_dvco_reset(void)
3637 v = readl_relaxed(clk_base + RST_DFLL_DVCO);
3638 v |= (1 << DVFS_DFLL_RESET_SHIFT);
3639 writel_relaxed(v, clk_base + RST_DFLL_DVCO);
3640 tegra210_car_barrier();
3644 * tegra210_clock_deassert_dfll_dvco_reset - deassert the DFLL's DVCO reset
3646 * Deassert the reset line of the DFLL's DVCO, allowing the DVCO to
3647 * operate. No return value.
3649 static void tegra210_clock_deassert_dfll_dvco_reset(void)
3653 v = readl_relaxed(clk_base + RST_DFLL_DVCO);
3654 v &= ~(1 << DVFS_DFLL_RESET_SHIFT);
3655 writel_relaxed(v, clk_base + RST_DFLL_DVCO);
3656 tegra210_car_barrier();
3659 static int tegra210_reset_assert(unsigned long id)
3661 if (id == TEGRA210_RST_DFLL_DVCO)
3662 tegra210_clock_assert_dfll_dvco_reset();
3663 else if (id == TEGRA210_RST_ADSP)
3664 writel(GENMASK(26, 21) | BIT(7),
3665 clk_base + CLK_RST_CONTROLLER_RST_DEV_Y_SET);
3672 static int tegra210_reset_deassert(unsigned long id)
3674 if (id == TEGRA210_RST_DFLL_DVCO)
3675 tegra210_clock_deassert_dfll_dvco_reset();
3676 else if (id == TEGRA210_RST_ADSP) {
3677 writel(BIT(21), clk_base + CLK_RST_CONTROLLER_RST_DEV_Y_CLR);
3679 * Considering adsp cpu clock (min: 12.5MHZ, max: 1GHz)
3680 * a delay of 5us ensures that it's at least
3681 * 6 * adsp_cpu_cycle_period long.
3684 writel(GENMASK(26, 22) | BIT(7),
3685 clk_base + CLK_RST_CONTROLLER_RST_DEV_Y_CLR);
3692 static void tegra210_mbist_clk_init(void)
3696 for (i = 0; i < ARRAY_SIZE(tegra210_pg_mbist_war); i++) {
3697 unsigned int num_clks = tegra210_pg_mbist_war[i].num_clks;
3698 struct clk_bulk_data *clk_data;
3703 clk_data = kmalloc_array(num_clks, sizeof(*clk_data),
3705 if (WARN_ON(!clk_data))
3708 tegra210_pg_mbist_war[i].clks = clk_data;
3709 for (j = 0; j < num_clks; j++) {
3710 int clk_id = tegra210_pg_mbist_war[i].clk_init_data[j];
3711 struct clk *clk = clks[clk_id];
3713 if (WARN(IS_ERR(clk), "clk_id: %d\n", clk_id)) {
3715 tegra210_pg_mbist_war[i].clks = NULL;
3718 clk_data[j].clk = clk;
3724 * tegra210_clock_init - Tegra210-specific clock initialization
3725 * @np: struct device_node * of the DT node for the SoC CAR IP block
3727 * Register most SoC clocks for the Tegra210 system-on-chip. Intended
3728 * to be called by the OF init code when a DT node with the
3729 * "nvidia,tegra210-car" string is encountered, and declared with
3730 * CLK_OF_DECLARE. No return value.
3732 static void __init tegra210_clock_init(struct device_node *np)
3734 struct device_node *node;
3735 u32 value, clk_m_div;
3737 clk_base = of_iomap(np, 0);
3739 pr_err("ioremap tegra210 CAR failed\n");
3743 node = of_find_matching_node(NULL, pmc_match);
3745 pr_err("Failed to find pmc node\n");
3750 pmc_base = of_iomap(node, 0);
3753 pr_err("Can't map pmc registers\n");
3758 ahub_base = ioremap(TEGRA210_AHUB_BASE, SZ_64K);
3760 pr_err("ioremap tegra210 APE failed\n");
3764 dispa_base = ioremap(TEGRA210_DISPA_BASE, SZ_256K);
3766 pr_err("ioremap tegra210 DISPA failed\n");
3770 vic_base = ioremap(TEGRA210_VIC_BASE, SZ_256K);
3772 pr_err("ioremap tegra210 VIC failed\n");
3776 clks = tegra_clk_init(clk_base, TEGRA210_CLK_CLK_MAX,
3777 TEGRA210_CAR_BANK_COUNT);
3781 value = readl(clk_base + SPARE_REG0) >> CLK_M_DIVISOR_SHIFT;
3782 clk_m_div = (value & CLK_M_DIVISOR_MASK) + 1;
3784 if (tegra_osc_clk_init(clk_base, tegra210_clks, tegra210_input_freq,
3785 ARRAY_SIZE(tegra210_input_freq), clk_m_div,
3786 &osc_freq, &pll_ref_freq) < 0)
3789 tegra_fixed_clk_init(tegra210_clks);
3790 tegra210_pll_init(clk_base, pmc_base);
3791 tegra210_periph_clk_init(np, clk_base, pmc_base);
3792 tegra_audio_clk_init(clk_base, pmc_base, tegra210_clks,
3793 tegra210_audio_plls,
3794 ARRAY_SIZE(tegra210_audio_plls), 24576000);
3796 /* For Tegra210, PLLD is the only source for DSIA & DSIB */
3797 value = readl(clk_base + PLLD_BASE);
3799 writel(value, clk_base + PLLD_BASE);
3801 tegra_clk_apply_init_table = tegra210_clock_apply_init_table;
3803 tegra_super_clk_gen5_init(clk_base, pmc_base, tegra210_clks,
3805 tegra_init_special_resets(2, tegra210_reset_assert,
3806 tegra210_reset_deassert);
3808 tegra_add_of_provider(np, of_clk_src_onecell_get);
3809 tegra_register_devclks(devclks, ARRAY_SIZE(devclks));
3811 tegra210_mbist_clk_init();
3813 tegra_cpu_car_ops = &tegra210_cpu_car_ops;
3815 register_syscore_ops(&tegra_clk_syscore_ops);
3817 CLK_OF_DECLARE(tegra210, "nvidia,tegra210-car", tegra210_clock_init);