1 // SPDX-License-Identifier: GPL-2.0-only
3 * drivers/clk/tegra/clk-emc.c
5 * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved.
8 * Mikko Perttunen <mperttunen@nvidia.com>
11 #include <linux/clk-provider.h>
12 #include <linux/clk.h>
13 #include <linux/clkdev.h>
14 #include <linux/clk/tegra.h>
15 #include <linux/delay.h>
16 #include <linux/export.h>
18 #include <linux/module.h>
19 #include <linux/of_address.h>
20 #include <linux/of_platform.h>
21 #include <linux/platform_device.h>
22 #include <linux/sort.h>
23 #include <linux/string.h>
25 #include <soc/tegra/fuse.h>
29 #define CLK_SOURCE_EMC 0x19c
31 #define CLK_SOURCE_EMC_EMC_2X_CLK_DIVISOR_SHIFT 0
32 #define CLK_SOURCE_EMC_EMC_2X_CLK_DIVISOR_MASK 0xff
33 #define CLK_SOURCE_EMC_EMC_2X_CLK_DIVISOR(x) (((x) & CLK_SOURCE_EMC_EMC_2X_CLK_DIVISOR_MASK) << \
34 CLK_SOURCE_EMC_EMC_2X_CLK_DIVISOR_SHIFT)
36 #define CLK_SOURCE_EMC_EMC_2X_CLK_SRC_SHIFT 29
37 #define CLK_SOURCE_EMC_EMC_2X_CLK_SRC_MASK 0x7
38 #define CLK_SOURCE_EMC_EMC_2X_CLK_SRC(x) (((x) & CLK_SOURCE_EMC_EMC_2X_CLK_SRC_MASK) << \
39 CLK_SOURCE_EMC_EMC_2X_CLK_SRC_SHIFT)
41 static const char * const emc_parent_clk_names[] = {
42 "pll_m", "pll_c", "pll_p", "clk_m", "pll_m_ud",
43 "pll_c2", "pll_c3", "pll_c_ud"
47 * List of clock sources for various parents the EMC clock can have.
48 * When we change the timing to a timing with a parent that has the same
49 * clock source as the current parent, we must first change to a backup
50 * timing that has a different clock source.
53 #define EMC_SRC_PLL_M 0
54 #define EMC_SRC_PLL_C 1
55 #define EMC_SRC_PLL_P 2
56 #define EMC_SRC_CLK_M 3
57 #define EMC_SRC_PLL_C2 4
58 #define EMC_SRC_PLL_C3 5
60 static const char emc_parent_clk_sources[] = {
61 EMC_SRC_PLL_M, EMC_SRC_PLL_C, EMC_SRC_PLL_P, EMC_SRC_CLK_M,
62 EMC_SRC_PLL_M, EMC_SRC_PLL_C2, EMC_SRC_PLL_C3, EMC_SRC_PLL_C
66 unsigned long rate, parent_rate;
72 struct tegra_clk_emc {
74 void __iomem *clk_regs;
75 struct clk *prev_parent;
78 struct device_node *emc_node;
79 struct tegra_emc *emc;
82 struct emc_timing *timings;
85 tegra124_emc_prepare_timing_change_cb *prepare_timing_change;
86 tegra124_emc_complete_timing_change_cb *complete_timing_change;
89 /* Common clock framework callback implementations */
91 static unsigned long emc_recalc_rate(struct clk_hw *hw,
92 unsigned long parent_rate)
94 struct tegra_clk_emc *tegra;
97 tegra = container_of(hw, struct tegra_clk_emc, hw);
100 * CCF wrongly assumes that the parent won't change during set_rate,
101 * so get the parent rate explicitly.
103 parent_rate = clk_hw_get_rate(clk_hw_get_parent(hw));
105 val = readl(tegra->clk_regs + CLK_SOURCE_EMC);
106 div = val & CLK_SOURCE_EMC_EMC_2X_CLK_DIVISOR_MASK;
108 return parent_rate / (div + 2) * 2;
112 * Rounds up unless no higher rate exists, in which case down. This way is
113 * safer since things have EMC rate floors. Also don't touch parent_rate
114 * since we don't want the CCF to play with our parent clocks.
116 static int emc_determine_rate(struct clk_hw *hw, struct clk_rate_request *req)
118 struct tegra_clk_emc *tegra;
119 u8 ram_code = tegra_read_ram_code();
120 struct emc_timing *timing = NULL;
123 tegra = container_of(hw, struct tegra_clk_emc, hw);
125 for (k = 0; k < tegra->num_timings; k++) {
126 if (tegra->timings[k].ram_code == ram_code)
130 for (t = k; t < tegra->num_timings; t++) {
131 if (tegra->timings[t].ram_code != ram_code)
135 for (i = k; i < t; i++) {
136 timing = tegra->timings + i;
138 if (timing->rate < req->rate && i != t - 1)
141 if (timing->rate > req->max_rate) {
143 req->rate = tegra->timings[i - 1].rate;
147 if (timing->rate < req->min_rate)
150 req->rate = timing->rate;
155 req->rate = timing->rate;
159 req->rate = clk_hw_get_rate(hw);
163 static u8 emc_get_parent(struct clk_hw *hw)
165 struct tegra_clk_emc *tegra;
168 tegra = container_of(hw, struct tegra_clk_emc, hw);
170 val = readl(tegra->clk_regs + CLK_SOURCE_EMC);
172 return (val >> CLK_SOURCE_EMC_EMC_2X_CLK_SRC_SHIFT)
173 & CLK_SOURCE_EMC_EMC_2X_CLK_SRC_MASK;
176 static struct tegra_emc *emc_ensure_emc_driver(struct tegra_clk_emc *tegra)
178 struct platform_device *pdev;
183 if (!tegra->prepare_timing_change || !tegra->complete_timing_change)
186 if (!tegra->emc_node)
189 pdev = of_find_device_by_node(tegra->emc_node);
191 pr_err("%s: could not get external memory controller\n",
196 of_node_put(tegra->emc_node);
197 tegra->emc_node = NULL;
199 tegra->emc = platform_get_drvdata(pdev);
201 pr_err("%s: cannot find EMC driver\n", __func__);
208 static int emc_set_timing(struct tegra_clk_emc *tegra,
209 struct emc_timing *timing)
214 unsigned long flags = 0;
215 struct tegra_emc *emc = emc_ensure_emc_driver(tegra);
220 pr_debug("going to rate %ld prate %ld p %s\n", timing->rate,
221 timing->parent_rate, __clk_get_name(timing->parent));
223 if (emc_get_parent(&tegra->hw) == timing->parent_index &&
224 clk_get_rate(timing->parent) != timing->parent_rate) {
225 WARN_ONCE(1, "parent %s rate mismatch %lu %lu\n",
226 __clk_get_name(timing->parent),
227 clk_get_rate(timing->parent),
228 timing->parent_rate);
232 tegra->changing_timing = true;
234 err = clk_set_rate(timing->parent, timing->parent_rate);
236 pr_err("cannot change parent %s rate to %ld: %d\n",
237 __clk_get_name(timing->parent), timing->parent_rate,
243 err = clk_prepare_enable(timing->parent);
245 pr_err("cannot enable parent clock: %d\n", err);
249 div = timing->parent_rate / (timing->rate / 2) - 2;
251 err = tegra->prepare_timing_change(emc, timing->rate);
253 clk_disable_unprepare(timing->parent);
257 spin_lock_irqsave(tegra->lock, flags);
259 car_value = readl(tegra->clk_regs + CLK_SOURCE_EMC);
261 car_value &= ~CLK_SOURCE_EMC_EMC_2X_CLK_SRC(~0);
262 car_value |= CLK_SOURCE_EMC_EMC_2X_CLK_SRC(timing->parent_index);
264 car_value &= ~CLK_SOURCE_EMC_EMC_2X_CLK_DIVISOR(~0);
265 car_value |= CLK_SOURCE_EMC_EMC_2X_CLK_DIVISOR(div);
267 writel(car_value, tegra->clk_regs + CLK_SOURCE_EMC);
269 spin_unlock_irqrestore(tegra->lock, flags);
271 tegra->complete_timing_change(emc, timing->rate);
273 clk_hw_reparent(&tegra->hw, __clk_get_hw(timing->parent));
274 clk_disable_unprepare(tegra->prev_parent);
276 tegra->prev_parent = timing->parent;
277 tegra->changing_timing = false;
283 * Get backup timing to use as an intermediate step when a change between
284 * two timings with the same clock source has been requested. First try to
285 * find a timing with a higher clock rate to avoid a rate below any set rate
286 * floors. If that is not possible, find a lower rate.
288 static struct emc_timing *get_backup_timing(struct tegra_clk_emc *tegra,
292 u32 ram_code = tegra_read_ram_code();
293 struct emc_timing *timing;
295 for (i = timing_index+1; i < tegra->num_timings; i++) {
296 timing = tegra->timings + i;
297 if (timing->ram_code != ram_code)
300 if (emc_parent_clk_sources[timing->parent_index] !=
301 emc_parent_clk_sources[
302 tegra->timings[timing_index].parent_index])
306 for (i = timing_index-1; i >= 0; --i) {
307 timing = tegra->timings + i;
308 if (timing->ram_code != ram_code)
311 if (emc_parent_clk_sources[timing->parent_index] !=
312 emc_parent_clk_sources[
313 tegra->timings[timing_index].parent_index])
320 static int emc_set_rate(struct clk_hw *hw, unsigned long rate,
321 unsigned long parent_rate)
323 struct tegra_clk_emc *tegra;
324 struct emc_timing *timing = NULL;
326 u32 ram_code = tegra_read_ram_code();
328 tegra = container_of(hw, struct tegra_clk_emc, hw);
330 if (clk_hw_get_rate(hw) == rate)
334 * When emc_set_timing changes the parent rate, CCF will propagate
335 * that downward to us, so ignore any set_rate calls while a rate
336 * change is already going on.
338 if (tegra->changing_timing)
341 for (i = 0; i < tegra->num_timings; i++) {
342 if (tegra->timings[i].rate == rate &&
343 tegra->timings[i].ram_code == ram_code) {
344 timing = tegra->timings + i;
350 pr_err("cannot switch to rate %ld without emc table\n", rate);
354 if (emc_parent_clk_sources[emc_get_parent(hw)] ==
355 emc_parent_clk_sources[timing->parent_index] &&
356 clk_get_rate(timing->parent) != timing->parent_rate) {
358 * Parent clock source not changed but parent rate has changed,
359 * need to temporarily switch to another parent
362 struct emc_timing *backup_timing;
364 backup_timing = get_backup_timing(tegra, i);
365 if (!backup_timing) {
366 pr_err("cannot find backup timing\n");
370 pr_debug("using %ld as backup rate when going to %ld\n",
371 backup_timing->rate, rate);
373 err = emc_set_timing(tegra, backup_timing);
375 pr_err("cannot set backup timing: %d\n", err);
380 return emc_set_timing(tegra, timing);
383 /* Initialization and deinitialization */
385 static int load_one_timing_from_dt(struct tegra_clk_emc *tegra,
386 struct emc_timing *timing,
387 struct device_node *node)
392 err = of_property_read_u32(node, "clock-frequency", &tmp);
394 pr_err("timing %pOF: failed to read rate\n", node);
400 err = of_property_read_u32(node, "nvidia,parent-clock-frequency", &tmp);
402 pr_err("timing %pOF: failed to read parent rate\n", node);
406 timing->parent_rate = tmp;
408 timing->parent = of_clk_get_by_name(node, "emc-parent");
409 if (IS_ERR(timing->parent)) {
410 pr_err("timing %pOF: failed to get parent clock\n", node);
411 return PTR_ERR(timing->parent);
414 timing->parent_index = 0xff;
415 i = match_string(emc_parent_clk_names, ARRAY_SIZE(emc_parent_clk_names),
416 __clk_get_name(timing->parent));
418 pr_err("timing %pOF: %s is not a valid parent\n",
419 node, __clk_get_name(timing->parent));
420 clk_put(timing->parent);
424 timing->parent_index = i;
428 static int cmp_timings(const void *_a, const void *_b)
430 const struct emc_timing *a = _a;
431 const struct emc_timing *b = _b;
433 if (a->rate < b->rate)
435 else if (a->rate == b->rate)
441 static int load_timings_from_dt(struct tegra_clk_emc *tegra,
442 struct device_node *node,
445 struct emc_timing *timings_ptr;
446 struct device_node *child;
447 int child_count = of_get_child_count(node);
451 size = (tegra->num_timings + child_count) * sizeof(struct emc_timing);
453 tegra->timings = krealloc(tegra->timings, size, GFP_KERNEL);
457 timings_ptr = tegra->timings + tegra->num_timings;
458 tegra->num_timings += child_count;
460 for_each_child_of_node(node, child) {
461 struct emc_timing *timing = timings_ptr + (i++);
463 err = load_one_timing_from_dt(tegra, timing, child);
469 timing->ram_code = ram_code;
472 sort(timings_ptr, child_count, sizeof(struct emc_timing),
478 static const struct clk_ops tegra_clk_emc_ops = {
479 .recalc_rate = emc_recalc_rate,
480 .determine_rate = emc_determine_rate,
481 .set_rate = emc_set_rate,
482 .get_parent = emc_get_parent,
485 struct clk *tegra124_clk_register_emc(void __iomem *base, struct device_node *np,
488 struct tegra_clk_emc *tegra;
489 struct clk_init_data init;
490 struct device_node *node;
495 tegra = kcalloc(1, sizeof(*tegra), GFP_KERNEL);
497 return ERR_PTR(-ENOMEM);
499 tegra->clk_regs = base;
502 tegra->num_timings = 0;
504 for_each_child_of_node(np, node) {
505 err = of_property_read_u32(node, "nvidia,ram-code",
511 * Store timings for all ram codes as we cannot read the
512 * fuses until the apbmisc driver is loaded.
514 err = load_timings_from_dt(tegra, node, node_ram_code);
521 if (tegra->num_timings == 0)
522 pr_warn("%s: no memory timings registered\n", __func__);
524 tegra->emc_node = of_parse_phandle(np,
525 "nvidia,external-memory-controller", 0);
526 if (!tegra->emc_node)
527 pr_warn("%s: couldn't find node for EMC driver\n", __func__);
530 init.ops = &tegra_clk_emc_ops;
531 init.flags = CLK_IS_CRITICAL;
532 init.parent_names = emc_parent_clk_names;
533 init.num_parents = ARRAY_SIZE(emc_parent_clk_names);
535 tegra->hw.init = &init;
537 clk = clk_register(NULL, &tegra->hw);
541 tegra->prev_parent = clk_hw_get_parent_by_index(
542 &tegra->hw, emc_get_parent(&tegra->hw))->clk;
543 tegra->changing_timing = false;
545 /* Allow debugging tools to see the EMC clock */
546 clk_register_clkdev(clk, "emc", "tegra-clk-debug");
551 void tegra124_clk_set_emc_callbacks(tegra124_emc_prepare_timing_change_cb *prep_cb,
552 tegra124_emc_complete_timing_change_cb *complete_cb)
554 struct clk *clk = __clk_lookup("emc");
555 struct tegra_clk_emc *tegra;
559 hw = __clk_get_hw(clk);
560 tegra = container_of(hw, struct tegra_clk_emc, hw);
562 tegra->prepare_timing_change = prep_cb;
563 tegra->complete_timing_change = complete_cb;
566 EXPORT_SYMBOL_GPL(tegra124_clk_set_emc_callbacks);
568 bool tegra124_clk_emc_driver_available(struct clk_hw *hw)
570 struct tegra_clk_emc *tegra = container_of(hw, struct tegra_clk_emc, hw);
572 return tegra->prepare_timing_change && tegra->complete_timing_change;