drivers/clk/tegra/clk-pll.c

   1 /*
   2  * Copyright (c) 2012, 2013, NVIDIA CORPORATION.  All rights reserved.
   3  *
   4  * This program is free software; you can redistribute it and/or modify it
   5  * under the terms and conditions of the GNU General Public License,
   6  * version 2, as published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope it will be useful, but WITHOUT
   9  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  10  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  11  * more details.
  12  *
  13  * You should have received a copy of the GNU General Public License
  14  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  15  */
  16
  17 #include <linux/slab.h>
  18 #include <linux/io.h>
  19 #include <linux/delay.h>
  20 #include <linux/err.h>
  21 #include <linux/clk-provider.h>
  22 #include <linux/clk.h>
  23
  24 #include "clk.h"
  25
  26 #define PLL_BASE_BYPASS BIT(31)
  27 #define PLL_BASE_ENABLE BIT(30)
  28 #define PLL_BASE_REF_ENABLE BIT(29)
  29 #define PLL_BASE_OVERRIDE BIT(28)
  30
  31 #define PLL_BASE_DIVP_SHIFT 20
  32 #define PLL_BASE_DIVP_WIDTH 3
  33 #define PLL_BASE_DIVN_SHIFT 8
  34 #define PLL_BASE_DIVN_WIDTH 10
  35 #define PLL_BASE_DIVM_SHIFT 0
  36 #define PLL_BASE_DIVM_WIDTH 5
  37 #define PLLU_POST_DIVP_MASK 0x1
  38
  39 #define PLL_MISC_DCCON_SHIFT 20
  40 #define PLL_MISC_CPCON_SHIFT 8
  41 #define PLL_MISC_CPCON_WIDTH 4
  42 #define PLL_MISC_CPCON_MASK ((1 << PLL_MISC_CPCON_WIDTH) - 1)
  43 #define PLL_MISC_LFCON_SHIFT 4
  44 #define PLL_MISC_LFCON_WIDTH 4
  45 #define PLL_MISC_LFCON_MASK ((1 << PLL_MISC_LFCON_WIDTH) - 1)
  46 #define PLL_MISC_VCOCON_SHIFT 0
  47 #define PLL_MISC_VCOCON_WIDTH 4
  48 #define PLL_MISC_VCOCON_MASK ((1 << PLL_MISC_VCOCON_WIDTH) - 1)
  49
  50 #define OUT_OF_TABLE_CPCON 8
  51
  52 #define PMC_PLLP_WB0_OVERRIDE 0xf8
  53 #define PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE BIT(12)
  54 #define PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE BIT(11)
  55
  56 #define PLL_POST_LOCK_DELAY 50
  57
  58 #define PLLDU_LFCON_SET_DIVN 600
  59
  60 #define PLLE_BASE_DIVCML_SHIFT 24
  61 #define PLLE_BASE_DIVCML_WIDTH 4
  62 #define PLLE_BASE_DIVP_SHIFT 16
  63 #define PLLE_BASE_DIVP_WIDTH 7
  64 #define PLLE_BASE_DIVN_SHIFT 8
  65 #define PLLE_BASE_DIVN_WIDTH 8
  66 #define PLLE_BASE_DIVM_SHIFT 0
  67 #define PLLE_BASE_DIVM_WIDTH 8
  68
  69 #define PLLE_MISC_SETUP_BASE_SHIFT 16
  70 #define PLLE_MISC_SETUP_BASE_MASK (0xffff << PLLE_MISC_SETUP_BASE_SHIFT)
  71 #define PLLE_MISC_LOCK_ENABLE BIT(9)
  72 #define PLLE_MISC_READY BIT(15)
  73 #define PLLE_MISC_SETUP_EX_SHIFT 2
  74 #define PLLE_MISC_SETUP_EX_MASK (3 << PLLE_MISC_SETUP_EX_SHIFT)
  75 #define PLLE_MISC_SETUP_MASK (PLLE_MISC_SETUP_BASE_MASK |       \
  76                               PLLE_MISC_SETUP_EX_MASK)
  77 #define PLLE_MISC_SETUP_VALUE (7 << PLLE_MISC_SETUP_BASE_SHIFT)
  78
  79 #define PLLE_SS_CTRL 0x68
  80 #define PLLE_SS_CNTL_BYPASS_SS BIT(10)
  81 #define PLLE_SS_CNTL_INTERP_RESET BIT(11)
  82 #define PLLE_SS_CNTL_SSC_BYP BIT(12)
  83 #define PLLE_SS_CNTL_CENTER BIT(14)
  84 #define PLLE_SS_CNTL_INVERT BIT(15)
  85 #define PLLE_SS_DISABLE (PLLE_SS_CNTL_BYPASS_SS | PLLE_SS_CNTL_INTERP_RESET |\
  86                                 PLLE_SS_CNTL_SSC_BYP)
  87 #define PLLE_SS_MAX_MASK 0x1ff
  88 #define PLLE_SS_MAX_VAL 0x25
  89 #define PLLE_SS_INC_MASK (0xff << 16)
  90 #define PLLE_SS_INC_VAL (0x1 << 16)
  91 #define PLLE_SS_INCINTRV_MASK (0x3f << 24)
  92 #define PLLE_SS_INCINTRV_VAL (0x20 << 24)
  93 #define PLLE_SS_COEFFICIENTS_MASK \
  94         (PLLE_SS_MAX_MASK | PLLE_SS_INC_MASK | PLLE_SS_INCINTRV_MASK)
  95 #define PLLE_SS_COEFFICIENTS_VAL \
  96         (PLLE_SS_MAX_VAL | PLLE_SS_INC_VAL | PLLE_SS_INCINTRV_VAL)
  97
  98 #define PLLE_AUX_PLLP_SEL       BIT(2)
  99 #define PLLE_AUX_ENABLE_SWCTL   BIT(4)
 100 #define PLLE_AUX_SEQ_ENABLE     BIT(24)
 101 #define PLLE_AUX_PLLRE_SEL      BIT(28)
 102
 103 #define PLLE_MISC_PLLE_PTS      BIT(8)
 104 #define PLLE_MISC_IDDQ_SW_VALUE BIT(13)
 105 #define PLLE_MISC_IDDQ_SW_CTRL  BIT(14)
 106 #define PLLE_MISC_VREG_BG_CTRL_SHIFT    4
 107 #define PLLE_MISC_VREG_BG_CTRL_MASK     (3 << PLLE_MISC_VREG_BG_CTRL_SHIFT)
 108 #define PLLE_MISC_VREG_CTRL_SHIFT       2
 109 #define PLLE_MISC_VREG_CTRL_MASK        (2 << PLLE_MISC_VREG_CTRL_SHIFT)
 110
 111 #define PLLCX_MISC_STROBE       BIT(31)
 112 #define PLLCX_MISC_RESET        BIT(30)
 113 #define PLLCX_MISC_SDM_DIV_SHIFT 28
 114 #define PLLCX_MISC_SDM_DIV_MASK (0x3 << PLLCX_MISC_SDM_DIV_SHIFT)
 115 #define PLLCX_MISC_FILT_DIV_SHIFT 26
 116 #define PLLCX_MISC_FILT_DIV_MASK (0x3 << PLLCX_MISC_FILT_DIV_SHIFT)
 117 #define PLLCX_MISC_ALPHA_SHIFT 18
 118 #define PLLCX_MISC_DIV_LOW_RANGE \
 119                 ((0x1 << PLLCX_MISC_SDM_DIV_SHIFT) | \
 120                 (0x1 << PLLCX_MISC_FILT_DIV_SHIFT))
 121 #define PLLCX_MISC_DIV_HIGH_RANGE \
 122                 ((0x2 << PLLCX_MISC_SDM_DIV_SHIFT) | \
 123                 (0x2 << PLLCX_MISC_FILT_DIV_SHIFT))
 124 #define PLLCX_MISC_COEF_LOW_RANGE \
 125                 ((0x14 << PLLCX_MISC_KA_SHIFT) | (0x38 << PLLCX_MISC_KB_SHIFT))
 126 #define PLLCX_MISC_KA_SHIFT 2
 127 #define PLLCX_MISC_KB_SHIFT 9
 128 #define PLLCX_MISC_DEFAULT (PLLCX_MISC_COEF_LOW_RANGE | \
 129                             (0x19 << PLLCX_MISC_ALPHA_SHIFT) | \
 130                             PLLCX_MISC_DIV_LOW_RANGE | \
 131                             PLLCX_MISC_RESET)
 132 #define PLLCX_MISC1_DEFAULT 0x000d2308
 133 #define PLLCX_MISC2_DEFAULT 0x30211200
 134 #define PLLCX_MISC3_DEFAULT 0x200
 135
 136 #define PMC_SATA_PWRGT 0x1ac
 137 #define PMC_SATA_PWRGT_PLLE_IDDQ_VALUE BIT(5)
 138 #define PMC_SATA_PWRGT_PLLE_IDDQ_SWCTL BIT(4)
 139
 140 #define pll_readl(offset, p) readl_relaxed(p->clk_base + offset)
 141 #define pll_readl_base(p) pll_readl(p->params->base_reg, p)
 142 #define pll_readl_misc(p) pll_readl(p->params->misc_reg, p)
 143 #define pll_override_readl(offset, p) readl_relaxed(p->pmc + offset)
 144
 145 #define pll_writel(val, offset, p) writel_relaxed(val, p->clk_base + offset)
 146 #define pll_writel_base(val, p) pll_writel(val, p->params->base_reg, p)
 147 #define pll_writel_misc(val, p) pll_writel(val, p->params->misc_reg, p)
 148 #define pll_override_writel(val, offset, p) writel(val, p->pmc + offset)
 149
 150 #define mask(w) ((1 << (w)) - 1)
 151 #define divm_mask(p) mask(p->params->div_nmp->divm_width)
 152 #define divn_mask(p) mask(p->params->div_nmp->divn_width)
 153 #define divp_mask(p) (p->flags & TEGRA_PLLU ? PLLU_POST_DIVP_MASK :     \
 154                       mask(p->params->div_nmp->divp_width))
 155
 156 #define divm_max(p) (divm_mask(p))
 157 #define divn_max(p) (divn_mask(p))
 158 #define divp_max(p) (1 << (divp_mask(p)))
 159
 160 static struct div_nmp default_nmp = {
 161         .divn_shift = PLL_BASE_DIVN_SHIFT,
 162         .divn_width = PLL_BASE_DIVN_WIDTH,
 163         .divm_shift = PLL_BASE_DIVM_SHIFT,
 164         .divm_width = PLL_BASE_DIVM_WIDTH,
 165         .divp_shift = PLL_BASE_DIVP_SHIFT,
 166         .divp_width = PLL_BASE_DIVP_WIDTH,
 167 };
 168
 169 static void clk_pll_enable_lock(struct tegra_clk_pll *pll)
 170 {
 171         u32 val;
 172
 173         if (!(pll->flags & TEGRA_PLL_USE_LOCK))
 174                 return;
 175
 176         if (!(pll->flags & TEGRA_PLL_HAS_LOCK_ENABLE))
 177                 return;
 178
 179         val = pll_readl_misc(pll);
 180         val |= BIT(pll->params->lock_enable_bit_idx);
 181         pll_writel_misc(val, pll);
 182 }
 183
 184 static int clk_pll_wait_for_lock(struct tegra_clk_pll *pll)
 185 {
 186         int i;
 187         u32 val, lock_mask;
 188         void __iomem *lock_addr;
 189
 190         if (!(pll->flags & TEGRA_PLL_USE_LOCK)) {
 191                 udelay(pll->params->lock_delay);
 192                 return 0;
 193         }
 194
 195         lock_addr = pll->clk_base;
 196         if (pll->flags & TEGRA_PLL_LOCK_MISC)
 197                 lock_addr += pll->params->misc_reg;
 198         else
 199                 lock_addr += pll->params->base_reg;
 200
 201         lock_mask = pll->params->lock_mask;
 202
 203         for (i = 0; i < pll->params->lock_delay; i++) {
 204                 val = readl_relaxed(lock_addr);
 205                 if ((val & lock_mask) == lock_mask) {
 206                         udelay(PLL_POST_LOCK_DELAY);
 207                         return 0;
 208                 }
 209                 udelay(2); /* timeout = 2 * lock time */
 210         }
 211
 212         pr_err("%s: Timed out waiting for pll %s lock\n", __func__,
 213                __clk_get_name(pll->hw.clk));
 214
 215         return -1;
 216 }
 217
 218 static int clk_pll_is_enabled(struct clk_hw *hw)
 219 {
 220         struct tegra_clk_pll *pll = to_clk_pll(hw);
 221         u32 val;
 222
 223         if (pll->flags & TEGRA_PLLM) {
 224                 val = readl_relaxed(pll->pmc + PMC_PLLP_WB0_OVERRIDE);
 225                 if (val & PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE)
 226                         return val & PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE ? 1 : 0;
 227         }
 228
 229         val = pll_readl_base(pll);
 230
 231         return val & PLL_BASE_ENABLE ? 1 : 0;
 232 }
 233
 234 static void _clk_pll_enable(struct clk_hw *hw)
 235 {
 236         struct tegra_clk_pll *pll = to_clk_pll(hw);
 237         u32 val;
 238
 239         clk_pll_enable_lock(pll);
 240
 241         val = pll_readl_base(pll);
 242         if (pll->flags & TEGRA_PLL_BYPASS)
 243                 val &= ~PLL_BASE_BYPASS;
 244         val |= PLL_BASE_ENABLE;
 245         pll_writel_base(val, pll);
 246
 247         if (pll->flags & TEGRA_PLLM) {
 248                 val = readl_relaxed(pll->pmc + PMC_PLLP_WB0_OVERRIDE);
 249                 val |= PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE;
 250                 writel_relaxed(val, pll->pmc + PMC_PLLP_WB0_OVERRIDE);
 251         }
 252 }
 253
 254 static void _clk_pll_disable(struct clk_hw *hw)
 255 {
 256         struct tegra_clk_pll *pll = to_clk_pll(hw);
 257         u32 val;
 258
 259         val = pll_readl_base(pll);
 260         if (pll->flags & TEGRA_PLL_BYPASS)
 261                 val &= ~PLL_BASE_BYPASS;
 262         val &= ~PLL_BASE_ENABLE;
 263         pll_writel_base(val, pll);
 264
 265         if (pll->flags & TEGRA_PLLM) {
 266                 val = readl_relaxed(pll->pmc + PMC_PLLP_WB0_OVERRIDE);
 267                 val &= ~PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE;
 268                 writel_relaxed(val, pll->pmc + PMC_PLLP_WB0_OVERRIDE);
 269         }
 270 }
 271
 272 static int clk_pll_enable(struct clk_hw *hw)
 273 {
 274         struct tegra_clk_pll *pll = to_clk_pll(hw);
 275         unsigned long flags = 0;
 276         int ret;
 277
 278         if (pll->lock)
 279                 spin_lock_irqsave(pll->lock, flags);
 280
 281         _clk_pll_enable(hw);
 282
 283         ret = clk_pll_wait_for_lock(pll);
 284
 285         if (pll->lock)
 286                 spin_unlock_irqrestore(pll->lock, flags);
 287
 288         return ret;
 289 }
 290
 291 static void clk_pll_disable(struct clk_hw *hw)
 292 {
 293         struct tegra_clk_pll *pll = to_clk_pll(hw);
 294         unsigned long flags = 0;
 295
 296         if (pll->lock)
 297                 spin_lock_irqsave(pll->lock, flags);
 298
 299         _clk_pll_disable(hw);
 300
 301         if (pll->lock)
 302                 spin_unlock_irqrestore(pll->lock, flags);
 303 }
 304
 305 static int _p_div_to_hw(struct clk_hw *hw, u8 p_div)
 306 {
 307         struct tegra_clk_pll *pll = to_clk_pll(hw);
 308         struct pdiv_map *p_tohw = pll->params->pdiv_tohw;
 309
 310         if (p_tohw) {
 311                 while (p_tohw->pdiv) {
 312                         if (p_div <= p_tohw->pdiv)
 313                                 return p_tohw->hw_val;
 314                         p_tohw++;
 315                 }
 316                 return -EINVAL;
 317         }
 318         return -EINVAL;
 319 }
 320
 321 static int _hw_to_p_div(struct clk_hw *hw, u8 p_div_hw)
 322 {
 323         struct tegra_clk_pll *pll = to_clk_pll(hw);
 324         struct pdiv_map *p_tohw = pll->params->pdiv_tohw;
 325
 326         if (p_tohw) {
 327                 while (p_tohw->pdiv) {
 328                         if (p_div_hw == p_tohw->hw_val)
 329                                 return p_tohw->pdiv;
 330                         p_tohw++;
 331                 }
 332                 return -EINVAL;
 333         }
 334
 335         return 1 << p_div_hw;
 336 }
 337
 338 static int _get_table_rate(struct clk_hw *hw,
 339                            struct tegra_clk_pll_freq_table *cfg,
 340                            unsigned long rate, unsigned long parent_rate)
 341 {
 342         struct tegra_clk_pll *pll = to_clk_pll(hw);
 343         struct tegra_clk_pll_freq_table *sel;
 344
 345         for (sel = pll->freq_table; sel->input_rate != 0; sel++)
 346                 if (sel->input_rate == parent_rate &&
 347                     sel->output_rate == rate)
 348                         break;
 349
 350         if (sel->input_rate == 0)
 351                 return -EINVAL;
 352
 353         cfg->input_rate = sel->input_rate;
 354         cfg->output_rate = sel->output_rate;
 355         cfg->m = sel->m;
 356         cfg->n = sel->n;
 357         cfg->p = sel->p;
 358         cfg->cpcon = sel->cpcon;
 359
 360         return 0;
 361 }
 362
 363 static int _calc_rate(struct clk_hw *hw, struct tegra_clk_pll_freq_table *cfg,
 364                       unsigned long rate, unsigned long parent_rate)
 365 {
 366         struct tegra_clk_pll *pll = to_clk_pll(hw);
 367         unsigned long cfreq;
 368         u32 p_div = 0;
 369         int ret;
 370
 371         switch (parent_rate) {
 372         case 12000000:
 373         case 26000000:
 374                 cfreq = (rate <= 1000000 * 1000) ? 1000000 : 2000000;
 375                 break;
 376         case 13000000:
 377                 cfreq = (rate <= 1000000 * 1000) ? 1000000 : 2600000;
 378                 break;
 379         case 16800000:
 380         case 19200000:
 381                 cfreq = (rate <= 1200000 * 1000) ? 1200000 : 2400000;
 382                 break;
 383         case 9600000:
 384         case 28800000:
 385                 /*
 386                  * PLL_P_OUT1 rate is not listed in PLLA table
 387                  */
 388                 cfreq = parent_rate/(parent_rate/1000000);
 389                 break;
 390         default:
 391                 pr_err("%s Unexpected reference rate %lu\n",
 392                        __func__, parent_rate);
 393                 BUG();
 394         }
 395
 396         /* Raise VCO to guarantee 0.5% accuracy */
 397         for (cfg->output_rate = rate; cfg->output_rate < 200 * cfreq;
 398              cfg->output_rate <<= 1)
 399                 p_div++;
 400
 401         cfg->m = parent_rate / cfreq;
 402         cfg->n = cfg->output_rate / cfreq;
 403         cfg->cpcon = OUT_OF_TABLE_CPCON;
 404
 405         if (cfg->m > divm_max(pll) || cfg->n > divn_max(pll) ||
 406             (1 << p_div) > divp_max(pll)
 407             || cfg->output_rate > pll->params->vco_max) {
 408                 pr_err("%s: Failed to set %s rate %lu\n",
 409                        __func__, __clk_get_name(hw->clk), rate);
 410                 WARN_ON(1);
 411                 return -EINVAL;
 412         }
 413
 414         cfg->output_rate >>= p_div;
 415
 416         if (pll->params->pdiv_tohw) {
 417                 ret = _p_div_to_hw(hw, 1 << p_div);
 418                 if (ret < 0)
 419                         return ret;
 420                 else
 421                         cfg->p = ret;
 422         } else
 423                 cfg->p = p_div;
 424
 425         return 0;
 426 }
 427
 428 static void _update_pll_mnp(struct tegra_clk_pll *pll,
 429                             struct tegra_clk_pll_freq_table *cfg)
 430 {
 431         u32 val;
 432         struct tegra_clk_pll_params *params = pll->params;
 433         struct div_nmp *div_nmp = params->div_nmp;
 434
 435         if ((pll->flags & TEGRA_PLLM) &&
 436                 (pll_override_readl(PMC_PLLP_WB0_OVERRIDE, pll) &
 437                         PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE)) {
 438                 val = pll_override_readl(params->pmc_divp_reg, pll);
 439                 val &= ~(divp_mask(pll) << div_nmp->override_divp_shift);
 440                 val |= cfg->p << div_nmp->override_divp_shift;
 441                 pll_override_writel(val, params->pmc_divp_reg, pll);
 442
 443                 val = pll_override_readl(params->pmc_divnm_reg, pll);
 444                 val &= ~(divm_mask(pll) << div_nmp->override_divm_shift) |
 445                         ~(divn_mask(pll) << div_nmp->override_divn_shift);
 446                 val |= (cfg->m << div_nmp->override_divm_shift) |
 447                         (cfg->n << div_nmp->override_divn_shift);
 448                 pll_override_writel(val, params->pmc_divnm_reg, pll);
 449         } else {
 450                 val = pll_readl_base(pll);
 451
 452                 val &= ~((divm_mask(pll) << div_nmp->divm_shift) |
 453                  (divn_mask(pll) << div_nmp->divn_shift) |
 454                  (divp_mask(pll) << div_nmp->divp_shift));
 455
 456                 val |= ((cfg->m << div_nmp->divm_shift) |
 457                         (cfg->n << div_nmp->divn_shift) |
 458                         (cfg->p << div_nmp->divp_shift));
 459
 460                 pll_writel_base(val, pll);
 461         }
 462 }
 463
 464 static void _get_pll_mnp(struct tegra_clk_pll *pll,
 465                          struct tegra_clk_pll_freq_table *cfg)
 466 {
 467         u32 val;
 468         struct tegra_clk_pll_params *params = pll->params;
 469         struct div_nmp *div_nmp = params->div_nmp;
 470
 471         if ((pll->flags & TEGRA_PLLM) &&
 472                 (pll_override_readl(PMC_PLLP_WB0_OVERRIDE, pll) &
 473                         PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE)) {
 474                 val = pll_override_readl(params->pmc_divp_reg, pll);
 475                 cfg->p = (val >> div_nmp->override_divp_shift) & divp_mask(pll);
 476
 477                 val = pll_override_readl(params->pmc_divnm_reg, pll);
 478                 cfg->m = (val >> div_nmp->override_divm_shift) & divm_mask(pll);
 479                 cfg->n = (val >> div_nmp->override_divn_shift) & divn_mask(pll);
 480         }  else {
 481                 val = pll_readl_base(pll);
 482
 483                 cfg->m = (val >> div_nmp->divm_shift) & divm_mask(pll);
 484                 cfg->n = (val >> div_nmp->divn_shift) & divn_mask(pll);
 485                 cfg->p = (val >> div_nmp->divp_shift) & divp_mask(pll);
 486         }
 487 }
 488
 489 static void _update_pll_cpcon(struct tegra_clk_pll *pll,
 490                               struct tegra_clk_pll_freq_table *cfg,
 491                               unsigned long rate)
 492 {
 493         u32 val;
 494
 495         val = pll_readl_misc(pll);
 496
 497         val &= ~(PLL_MISC_CPCON_MASK << PLL_MISC_CPCON_SHIFT);
 498         val |= cfg->cpcon << PLL_MISC_CPCON_SHIFT;
 499
 500         if (pll->flags & TEGRA_PLL_SET_LFCON) {
 501                 val &= ~(PLL_MISC_LFCON_MASK << PLL_MISC_LFCON_SHIFT);
 502                 if (cfg->n >= PLLDU_LFCON_SET_DIVN)
 503                         val |= 1 << PLL_MISC_LFCON_SHIFT;
 504         } else if (pll->flags & TEGRA_PLL_SET_DCCON) {
 505                 val &= ~(1 << PLL_MISC_DCCON_SHIFT);
 506                 if (rate >= (pll->params->vco_max >> 1))
 507                         val |= 1 << PLL_MISC_DCCON_SHIFT;
 508         }
 509
 510         pll_writel_misc(val, pll);
 511 }
 512
 513 static int _program_pll(struct clk_hw *hw, struct tegra_clk_pll_freq_table *cfg,
 514                         unsigned long rate)
 515 {
 516         struct tegra_clk_pll *pll = to_clk_pll(hw);
 517         int state, ret = 0;
 518
 519         state = clk_pll_is_enabled(hw);
 520
 521         if (state)
 522                 _clk_pll_disable(hw);
 523
 524         _update_pll_mnp(pll, cfg);
 525
 526         if (pll->flags & TEGRA_PLL_HAS_CPCON)
 527                 _update_pll_cpcon(pll, cfg, rate);
 528
 529         if (state) {
 530                 _clk_pll_enable(hw);
 531                 ret = clk_pll_wait_for_lock(pll);
 532         }
 533
 534         return ret;
 535 }
 536
 537 static int clk_pll_set_rate(struct clk_hw *hw, unsigned long rate,
 538                         unsigned long parent_rate)
 539 {
 540         struct tegra_clk_pll *pll = to_clk_pll(hw);
 541         struct tegra_clk_pll_freq_table cfg, old_cfg;
 542         unsigned long flags = 0;
 543         int ret = 0;
 544
 545         if (pll->flags & TEGRA_PLL_FIXED) {
 546                 if (rate != pll->fixed_rate) {
 547                         pr_err("%s: Can not change %s fixed rate %lu to %lu\n",
 548                                 __func__, __clk_get_name(hw->clk),
 549                                 pll->fixed_rate, rate);
 550                         return -EINVAL;
 551                 }
 552                 return 0;
 553         }
 554
 555         if (_get_table_rate(hw, &cfg, rate, parent_rate) &&
 556             _calc_rate(hw, &cfg, rate, parent_rate)) {
 557                 WARN_ON(1);
 558                 return -EINVAL;
 559         }
 560         if (pll->lock)
 561                 spin_lock_irqsave(pll->lock, flags);
 562
 563         _get_pll_mnp(pll, &old_cfg);
 564
 565         if (old_cfg.m != cfg.m || old_cfg.n != cfg.n || old_cfg.p != cfg.p)
 566                 ret = _program_pll(hw, &cfg, rate);
 567
 568         if (pll->lock)
 569                 spin_unlock_irqrestore(pll->lock, flags);
 570
 571         return ret;
 572 }
 573
 574 static long clk_pll_round_rate(struct clk_hw *hw, unsigned long rate,
 575                         unsigned long *prate)
 576 {
 577         struct tegra_clk_pll *pll = to_clk_pll(hw);
 578         struct tegra_clk_pll_freq_table cfg;
 579
 580         if (pll->flags & TEGRA_PLL_FIXED)
 581                 return pll->fixed_rate;
 582
 583         /* PLLM is used for memory; we do not change rate */
 584         if (pll->flags & TEGRA_PLLM)
 585                 return __clk_get_rate(hw->clk);
 586
 587         if (_get_table_rate(hw, &cfg, rate, *prate) &&
 588             _calc_rate(hw, &cfg, rate, *prate)) {
 589                 WARN_ON(1);
 590                 return -EINVAL;
 591         }
 592
 593         return cfg.output_rate;
 594 }
 595
 596 static unsigned long clk_pll_recalc_rate(struct clk_hw *hw,
 597                                          unsigned long parent_rate)
 598 {
 599         struct tegra_clk_pll *pll = to_clk_pll(hw);
 600         struct tegra_clk_pll_freq_table cfg;
 601         u32 val;
 602         u64 rate = parent_rate;
 603         int pdiv;
 604
 605         val = pll_readl_base(pll);
 606
 607         if ((pll->flags & TEGRA_PLL_BYPASS) && (val & PLL_BASE_BYPASS))
 608                 return parent_rate;
 609
 610         if ((pll->flags & TEGRA_PLL_FIXED) && !(val & PLL_BASE_OVERRIDE)) {
 611                 struct tegra_clk_pll_freq_table sel;
 612                 if (_get_table_rate(hw, &sel, pll->fixed_rate, parent_rate)) {
 613                         pr_err("Clock %s has unknown fixed frequency\n",
 614                                __clk_get_name(hw->clk));
 615                         BUG();
 616                 }
 617                 return pll->fixed_rate;
 618         }
 619
 620         _get_pll_mnp(pll, &cfg);
 621
 622         pdiv = _hw_to_p_div(hw, cfg.p);
 623         if (pdiv < 0) {
 624                 WARN_ON(1);
 625                 pdiv = 1;
 626         }
 627
 628         cfg.m *= pdiv;
 629
 630         rate *= cfg.n;
 631         do_div(rate, cfg.m);
 632
 633         return rate;
 634 }
 635
 636 static int clk_plle_training(struct tegra_clk_pll *pll)
 637 {
 638         u32 val;
 639         unsigned long timeout;
 640
 641         if (!pll->pmc)
 642                 return -ENOSYS;
 643
 644         /*
 645          * PLLE is already disabled, and setup cleared;
 646          * create falling edge on PLLE IDDQ input.
 647          */
 648         val = readl(pll->pmc + PMC_SATA_PWRGT);
 649         val |= PMC_SATA_PWRGT_PLLE_IDDQ_VALUE;
 650         writel(val, pll->pmc + PMC_SATA_PWRGT);
 651
 652         val = readl(pll->pmc + PMC_SATA_PWRGT);
 653         val |= PMC_SATA_PWRGT_PLLE_IDDQ_SWCTL;
 654         writel(val, pll->pmc + PMC_SATA_PWRGT);
 655
 656         val = readl(pll->pmc + PMC_SATA_PWRGT);
 657         val &= ~PMC_SATA_PWRGT_PLLE_IDDQ_VALUE;
 658         writel(val, pll->pmc + PMC_SATA_PWRGT);
 659
 660         val = pll_readl_misc(pll);
 661
 662         timeout = jiffies + msecs_to_jiffies(100);
 663         while (1) {
 664                 val = pll_readl_misc(pll);
 665                 if (val & PLLE_MISC_READY)
 666                         break;
 667                 if (time_after(jiffies, timeout)) {
 668                         pr_err("%s: timeout waiting for PLLE\n", __func__);
 669                         return -EBUSY;
 670                 }
 671                 udelay(300);
 672         }
 673
 674         return 0;
 675 }
 676
 677 static int clk_plle_enable(struct clk_hw *hw)
 678 {
 679         struct tegra_clk_pll *pll = to_clk_pll(hw);
 680         unsigned long input_rate = clk_get_rate(clk_get_parent(hw->clk));
 681         struct tegra_clk_pll_freq_table sel;
 682         u32 val;
 683         int err;
 684
 685         if (_get_table_rate(hw, &sel, pll->fixed_rate, input_rate))
 686                 return -EINVAL;
 687
 688         clk_pll_disable(hw);
 689
 690         val = pll_readl_misc(pll);
 691         val &= ~(PLLE_MISC_LOCK_ENABLE | PLLE_MISC_SETUP_MASK);
 692         pll_writel_misc(val, pll);
 693
 694         val = pll_readl_misc(pll);
 695         if (!(val & PLLE_MISC_READY)) {
 696                 err = clk_plle_training(pll);
 697                 if (err)
 698                         return err;
 699         }
 700
 701         if (pll->flags & TEGRA_PLLE_CONFIGURE) {
 702                 /* configure dividers */
 703                 val = pll_readl_base(pll);
 704                 val &= ~(divm_mask(pll) | divn_mask(pll) | divp_mask(pll));
 705                 val &= ~(PLLE_BASE_DIVCML_WIDTH << PLLE_BASE_DIVCML_SHIFT);
 706                 val |= sel.m << pll->params->div_nmp->divm_shift;
 707                 val |= sel.n << pll->params->div_nmp->divn_shift;
 708                 val |= sel.p << pll->params->div_nmp->divp_shift;
 709                 val |= sel.cpcon << PLLE_BASE_DIVCML_SHIFT;
 710                 pll_writel_base(val, pll);
 711         }
 712
 713         val = pll_readl_misc(pll);
 714         val |= PLLE_MISC_SETUP_VALUE;
 715         val |= PLLE_MISC_LOCK_ENABLE;
 716         pll_writel_misc(val, pll);
 717
 718         val = readl(pll->clk_base + PLLE_SS_CTRL);
 719         val |= PLLE_SS_DISABLE;
 720         writel(val, pll->clk_base + PLLE_SS_CTRL);
 721
 722         val |= pll_readl_base(pll);
 723         val |= (PLL_BASE_BYPASS | PLL_BASE_ENABLE);
 724         pll_writel_base(val, pll);
 725
 726         clk_pll_wait_for_lock(pll);
 727
 728         return 0;
 729 }
 730
 731 static unsigned long clk_plle_recalc_rate(struct clk_hw *hw,
 732                                          unsigned long parent_rate)
 733 {
 734         struct tegra_clk_pll *pll = to_clk_pll(hw);
 735         u32 val = pll_readl_base(pll);
 736         u32 divn = 0, divm = 0, divp = 0;
 737         u64 rate = parent_rate;
 738
 739         divp = (val >> pll->params->div_nmp->divp_shift) & (divp_mask(pll));
 740         divn = (val >> pll->params->div_nmp->divn_shift) & (divn_mask(pll));
 741         divm = (val >> pll->params->div_nmp->divm_shift) & (divm_mask(pll));
 742         divm *= divp;
 743
 744         rate *= divn;
 745         do_div(rate, divm);
 746         return rate;
 747 }
 748
 749 const struct clk_ops tegra_clk_pll_ops = {
 750         .is_enabled = clk_pll_is_enabled,
 751         .enable = clk_pll_enable,
 752         .disable = clk_pll_disable,
 753         .recalc_rate = clk_pll_recalc_rate,
 754         .round_rate = clk_pll_round_rate,
 755         .set_rate = clk_pll_set_rate,
 756 };
 757
 758 const struct clk_ops tegra_clk_plle_ops = {
 759         .recalc_rate = clk_plle_recalc_rate,
 760         .is_enabled = clk_pll_is_enabled,
 761         .disable = clk_pll_disable,
 762         .enable = clk_plle_enable,
 763 };
 764
 765 #ifdef CONFIG_ARCH_TEGRA_114_SOC
 766
 767 static int _pll_fixed_mdiv(struct tegra_clk_pll_params *pll_params,
 768                            unsigned long parent_rate)
 769 {
 770         if (parent_rate > pll_params->cf_max)
 771                 return 2;
 772         else
 773                 return 1;
 774 }
 775
 776 static int clk_pll_iddq_enable(struct clk_hw *hw)
 777 {
 778         struct tegra_clk_pll *pll = to_clk_pll(hw);
 779         unsigned long flags = 0;
 780
 781         u32 val;
 782         int ret;
 783
 784         if (pll->lock)
 785                 spin_lock_irqsave(pll->lock, flags);
 786
 787         val = pll_readl(pll->params->iddq_reg, pll);
 788         val &= ~BIT(pll->params->iddq_bit_idx);
 789         pll_writel(val, pll->params->iddq_reg, pll);
 790         udelay(2);
 791
 792         _clk_pll_enable(hw);
 793
 794         ret = clk_pll_wait_for_lock(pll);
 795
 796         if (pll->lock)
 797                 spin_unlock_irqrestore(pll->lock, flags);
 798
 799         return 0;
 800 }
 801
 802 static void clk_pll_iddq_disable(struct clk_hw *hw)
 803 {
 804         struct tegra_clk_pll *pll = to_clk_pll(hw);
 805         unsigned long flags = 0;
 806         u32 val;
 807
 808         if (pll->lock)
 809                 spin_lock_irqsave(pll->lock, flags);
 810
 811         _clk_pll_disable(hw);
 812
 813         val = pll_readl(pll->params->iddq_reg, pll);
 814         val |= BIT(pll->params->iddq_bit_idx);
 815         pll_writel(val, pll->params->iddq_reg, pll);
 816         udelay(2);
 817
 818         if (pll->lock)
 819                 spin_unlock_irqrestore(pll->lock, flags);
 820 }
 821
 822 static int _calc_dynamic_ramp_rate(struct clk_hw *hw,
 823                                 struct tegra_clk_pll_freq_table *cfg,
 824                                 unsigned long rate, unsigned long parent_rate)
 825 {
 826         struct tegra_clk_pll *pll = to_clk_pll(hw);
 827         unsigned int p;
 828         int p_div;
 829
 830         if (!rate)
 831                 return -EINVAL;
 832
 833         p = DIV_ROUND_UP(pll->params->vco_min, rate);
 834         cfg->m = _pll_fixed_mdiv(pll->params, parent_rate);
 835         cfg->output_rate = rate * p;
 836         cfg->n = cfg->output_rate * cfg->m / parent_rate;
 837
 838         p_div = _p_div_to_hw(hw, p);
 839         if (p_div < 0)
 840                 return p_div;
 841         else
 842                 cfg->p = p_div;
 843
 844         if (cfg->n > divn_max(pll) || cfg->output_rate > pll->params->vco_max)
 845                 return -EINVAL;
 846
 847         return 0;
 848 }
 849
 850 static int _pll_ramp_calc_pll(struct clk_hw *hw,
 851                               struct tegra_clk_pll_freq_table *cfg,
 852                               unsigned long rate, unsigned long parent_rate)
 853 {
 854         struct tegra_clk_pll *pll = to_clk_pll(hw);
 855         int err = 0, p_div;
 856
 857         err = _get_table_rate(hw, cfg, rate, parent_rate);
 858         if (err < 0)
 859                 err = _calc_dynamic_ramp_rate(hw, cfg, rate, parent_rate);
 860         else {
 861                 if (cfg->m != _pll_fixed_mdiv(pll->params, parent_rate)) {
 862                         WARN_ON(1);
 863                         err = -EINVAL;
 864                         goto out;
 865                 }
 866                 p_div = _p_div_to_hw(hw, cfg->p);
 867                 if (p_div < 0)
 868                         return p_div;
 869                 else
 870                         cfg->p = p_div;
 871         }
 872
 873         if (cfg->p >  pll->params->max_p)
 874                 err = -EINVAL;
 875
 876 out:
 877         return err;
 878 }
 879
 880 static int clk_pllxc_set_rate(struct clk_hw *hw, unsigned long rate,
 881                                 unsigned long parent_rate)
 882 {
 883         struct tegra_clk_pll *pll = to_clk_pll(hw);
 884         struct tegra_clk_pll_freq_table cfg, old_cfg;
 885         unsigned long flags = 0;
 886         int ret = 0;
 887
 888         ret = _pll_ramp_calc_pll(hw, &cfg, rate, parent_rate);
 889         if (ret < 0)
 890                 return ret;
 891
 892         if (pll->lock)
 893                 spin_lock_irqsave(pll->lock, flags);
 894
 895         _get_pll_mnp(pll, &old_cfg);
 896
 897         if (old_cfg.m != cfg.m || old_cfg.n != cfg.n || old_cfg.p != cfg.p)
 898                 ret = _program_pll(hw, &cfg, rate);
 899
 900         if (pll->lock)
 901                 spin_unlock_irqrestore(pll->lock, flags);
 902
 903         return ret;
 904 }
 905
 906 static long clk_pll_ramp_round_rate(struct clk_hw *hw, unsigned long rate,
 907                                 unsigned long *prate)
 908 {
 909         struct tegra_clk_pll_freq_table cfg;
 910         int ret = 0, p_div;
 911         u64 output_rate = *prate;
 912
 913         ret = _pll_ramp_calc_pll(hw, &cfg, rate, *prate);
 914         if (ret < 0)
 915                 return ret;
 916
 917         p_div = _hw_to_p_div(hw, cfg.p);
 918         if (p_div < 0)
 919                 return p_div;
 920
 921         output_rate *= cfg.n;
 922         do_div(output_rate, cfg.m * p_div);
 923
 924         return output_rate;
 925 }
 926
 927 static int clk_pllm_set_rate(struct clk_hw *hw, unsigned long rate,
 928                                 unsigned long parent_rate)
 929 {
 930         struct tegra_clk_pll_freq_table cfg;
 931         struct tegra_clk_pll *pll = to_clk_pll(hw);
 932         unsigned long flags = 0;
 933         int state, ret = 0;
 934
 935         if (pll->lock)
 936                 spin_lock_irqsave(pll->lock, flags);
 937
 938         state = clk_pll_is_enabled(hw);
 939         if (state) {
 940                 if (rate != clk_get_rate(hw->clk)) {
 941                         pr_err("%s: Cannot change active PLLM\n", __func__);
 942                         ret = -EINVAL;
 943                         goto out;
 944                 }
 945                 goto out;
 946         }
 947
 948         ret = _pll_ramp_calc_pll(hw, &cfg, rate, parent_rate);
 949         if (ret < 0)
 950                 goto out;
 951
 952         _update_pll_mnp(pll, &cfg);
 953
 954 out:
 955         if (pll->lock)
 956                 spin_unlock_irqrestore(pll->lock, flags);
 957
 958         return ret;
 959 }
 960
 961 static void _pllcx_strobe(struct tegra_clk_pll *pll)
 962 {
 963         u32 val;
 964
 965         val = pll_readl_misc(pll);
 966         val |= PLLCX_MISC_STROBE;
 967         pll_writel_misc(val, pll);
 968         udelay(2);
 969
 970         val &= ~PLLCX_MISC_STROBE;
 971         pll_writel_misc(val, pll);
 972 }
 973
 974 static int clk_pllc_enable(struct clk_hw *hw)
 975 {
 976         struct tegra_clk_pll *pll = to_clk_pll(hw);
 977         u32 val;
 978         int ret = 0;
 979         unsigned long flags = 0;
 980
 981         if (pll->lock)
 982                 spin_lock_irqsave(pll->lock, flags);
 983
 984         _clk_pll_enable(hw);
 985         udelay(2);
 986
 987         val = pll_readl_misc(pll);
 988         val &= ~PLLCX_MISC_RESET;
 989         pll_writel_misc(val, pll);
 990         udelay(2);
 991
 992         _pllcx_strobe(pll);
 993
 994         ret = clk_pll_wait_for_lock(pll);
 995
 996         if (pll->lock)
 997                 spin_unlock_irqrestore(pll->lock, flags);
 998
 999         return ret;
1000 }
1001
1002 static void _clk_pllc_disable(struct clk_hw *hw)
1003 {
1004         struct tegra_clk_pll *pll = to_clk_pll(hw);
1005         u32 val;
1006
1007         _clk_pll_disable(hw);
1008
1009         val = pll_readl_misc(pll);
1010         val |= PLLCX_MISC_RESET;
1011         pll_writel_misc(val, pll);
1012         udelay(2);
1013 }
1014
1015 static void clk_pllc_disable(struct clk_hw *hw)
1016 {
1017         struct tegra_clk_pll *pll = to_clk_pll(hw);
1018         unsigned long flags = 0;
1019
1020         if (pll->lock)
1021                 spin_lock_irqsave(pll->lock, flags);
1022
1023         _clk_pllc_disable(hw);
1024
1025         if (pll->lock)
1026                 spin_unlock_irqrestore(pll->lock, flags);
1027 }
1028
1029 static int _pllcx_update_dynamic_coef(struct tegra_clk_pll *pll,
1030                                         unsigned long input_rate, u32 n)
1031 {
1032         u32 val, n_threshold;
1033
1034         switch (input_rate) {
1035         case 12000000:
1036                 n_threshold = 70;
1037                 break;
1038         case 13000000:
1039         case 26000000:
1040                 n_threshold = 71;
1041                 break;
1042         case 16800000:
1043                 n_threshold = 55;
1044                 break;
1045         case 19200000:
1046                 n_threshold = 48;
1047                 break;
1048         default:
1049                 pr_err("%s: Unexpected reference rate %lu\n",
1050                         __func__, input_rate);
1051                 return -EINVAL;
1052         }
1053
1054         val = pll_readl_misc(pll);
1055         val &= ~(PLLCX_MISC_SDM_DIV_MASK | PLLCX_MISC_FILT_DIV_MASK);
1056         val |= n <= n_threshold ?
1057                 PLLCX_MISC_DIV_LOW_RANGE : PLLCX_MISC_DIV_HIGH_RANGE;
1058         pll_writel_misc(val, pll);
1059
1060         return 0;
1061 }
1062
1063 static int clk_pllc_set_rate(struct clk_hw *hw, unsigned long rate,
1064                                 unsigned long parent_rate)
1065 {
1066         struct tegra_clk_pll_freq_table cfg, old_cfg;
1067         struct tegra_clk_pll *pll = to_clk_pll(hw);
1068         unsigned long flags = 0;
1069         int state, ret = 0;
1070
1071         if (pll->lock)
1072                 spin_lock_irqsave(pll->lock, flags);
1073
1074         ret = _pll_ramp_calc_pll(hw, &cfg, rate, parent_rate);
1075         if (ret < 0)
1076                 goto out;
1077
1078         _get_pll_mnp(pll, &old_cfg);
1079
1080         if (cfg.m != old_cfg.m) {
1081                 WARN_ON(1);
1082                 goto out;
1083         }
1084
1085         if (old_cfg.n == cfg.n && old_cfg.p == cfg.p)
1086                 goto out;
1087
1088         state = clk_pll_is_enabled(hw);
1089         if (state)
1090                 _clk_pllc_disable(hw);
1091
1092         ret = _pllcx_update_dynamic_coef(pll, parent_rate, cfg.n);
1093         if (ret < 0)
1094                 goto out;
1095
1096         _update_pll_mnp(pll, &cfg);
1097
1098         if (state)
1099                 ret = clk_pllc_enable(hw);
1100
1101 out:
1102         if (pll->lock)
1103                 spin_unlock_irqrestore(pll->lock, flags);
1104
1105         return ret;
1106 }
1107
1108 static long _pllre_calc_rate(struct tegra_clk_pll *pll,
1109                              struct tegra_clk_pll_freq_table *cfg,
1110                              unsigned long rate, unsigned long parent_rate)
1111 {
1112         u16 m, n;
1113         u64 output_rate = parent_rate;
1114
1115         m = _pll_fixed_mdiv(pll->params, parent_rate);
1116         n = rate * m / parent_rate;
1117
1118         output_rate *= n;
1119         do_div(output_rate, m);
1120
1121         if (cfg) {
1122                 cfg->m = m;
1123                 cfg->n = n;
1124         }
1125
1126         return output_rate;
1127 }
1128 static int clk_pllre_set_rate(struct clk_hw *hw, unsigned long rate,
1129                                 unsigned long parent_rate)
1130 {
1131         struct tegra_clk_pll_freq_table cfg, old_cfg;
1132         struct tegra_clk_pll *pll = to_clk_pll(hw);
1133         unsigned long flags = 0;
1134         int state, ret = 0;
1135
1136         if (pll->lock)
1137                 spin_lock_irqsave(pll->lock, flags);
1138
1139         _pllre_calc_rate(pll, &cfg, rate, parent_rate);
1140         _get_pll_mnp(pll, &old_cfg);
1141         cfg.p = old_cfg.p;
1142
1143         if (cfg.m != old_cfg.m || cfg.n != old_cfg.n) {
1144                 state = clk_pll_is_enabled(hw);
1145                 if (state)
1146                         _clk_pll_disable(hw);
1147
1148                 _update_pll_mnp(pll, &cfg);
1149
1150                 if (state) {
1151                         _clk_pll_enable(hw);
1152                         ret = clk_pll_wait_for_lock(pll);
1153                 }
1154         }
1155
1156         if (pll->lock)
1157                 spin_unlock_irqrestore(pll->lock, flags);
1158
1159         return ret;
1160 }
1161
1162 static unsigned long clk_pllre_recalc_rate(struct clk_hw *hw,
1163                                          unsigned long parent_rate)
1164 {
1165         struct tegra_clk_pll_freq_table cfg;
1166         struct tegra_clk_pll *pll = to_clk_pll(hw);
1167         u64 rate = parent_rate;
1168
1169         _get_pll_mnp(pll, &cfg);
1170
1171         rate *= cfg.n;
1172         do_div(rate, cfg.m);
1173
1174         return rate;
1175 }
1176
1177 static long clk_pllre_round_rate(struct clk_hw *hw, unsigned long rate,
1178                                  unsigned long *prate)
1179 {
1180         struct tegra_clk_pll *pll = to_clk_pll(hw);
1181
1182         return _pllre_calc_rate(pll, NULL, rate, *prate);
1183 }
1184
1185 static int clk_plle_tegra114_enable(struct clk_hw *hw)
1186 {
1187         struct tegra_clk_pll *pll = to_clk_pll(hw);
1188         struct tegra_clk_pll_freq_table sel;
1189         u32 val;
1190         int ret;
1191         unsigned long flags = 0;
1192         unsigned long input_rate = clk_get_rate(clk_get_parent(hw->clk));
1193
1194         if (_get_table_rate(hw, &sel, pll->fixed_rate, input_rate))
1195                 return -EINVAL;
1196
1197         if (pll->lock)
1198                 spin_lock_irqsave(pll->lock, flags);
1199
1200         val = pll_readl_base(pll);
1201         val &= ~BIT(29); /* Disable lock override */
1202         pll_writel_base(val, pll);
1203
1204         val = pll_readl(pll->params->aux_reg, pll);
1205         val |= PLLE_AUX_ENABLE_SWCTL;
1206         val &= ~PLLE_AUX_SEQ_ENABLE;
1207         pll_writel(val, pll->params->aux_reg, pll);
1208         udelay(1);
1209
1210         val = pll_readl_misc(pll);
1211         val |= PLLE_MISC_LOCK_ENABLE;
1212         val |= PLLE_MISC_IDDQ_SW_CTRL;
1213         val &= ~PLLE_MISC_IDDQ_SW_VALUE;
1214         val |= PLLE_MISC_PLLE_PTS;
1215         val |= PLLE_MISC_VREG_BG_CTRL_MASK | PLLE_MISC_VREG_CTRL_MASK;
1216         pll_writel_misc(val, pll);
1217         udelay(5);
1218
1219         val = pll_readl(PLLE_SS_CTRL, pll);
1220         val |= PLLE_SS_DISABLE;
1221         pll_writel(val, PLLE_SS_CTRL, pll);
1222
1223         val = pll_readl_base(pll);
1224         val &= ~(divm_mask(pll) | divn_mask(pll) | divp_mask(pll));
1225         val &= ~(PLLE_BASE_DIVCML_WIDTH << PLLE_BASE_DIVCML_SHIFT);
1226         val |= sel.m << pll->params->div_nmp->divm_shift;
1227         val |= sel.n << pll->params->div_nmp->divn_shift;
1228         val |= sel.cpcon << PLLE_BASE_DIVCML_SHIFT;
1229         pll_writel_base(val, pll);
1230         udelay(1);
1231
1232         _clk_pll_enable(hw);
1233         ret = clk_pll_wait_for_lock(pll);
1234
1235         if (ret < 0)
1236                 goto out;
1237
1238         val = pll_readl(PLLE_SS_CTRL, pll);
1239         val &= ~(PLLE_SS_CNTL_CENTER | PLLE_SS_CNTL_INVERT);
1240         val &= ~PLLE_SS_COEFFICIENTS_MASK;
1241         val |= PLLE_SS_COEFFICIENTS_VAL;
1242         pll_writel(val, PLLE_SS_CTRL, pll);
1243         val &= ~(PLLE_SS_CNTL_SSC_BYP | PLLE_SS_CNTL_BYPASS_SS);
1244         pll_writel(val, PLLE_SS_CTRL, pll);
1245         udelay(1);
1246         val &= ~PLLE_SS_CNTL_INTERP_RESET;
1247         pll_writel(val, PLLE_SS_CTRL, pll);
1248         udelay(1);
1249
1250         /* TODO: enable hw control of xusb brick pll */
1251
1252 out:
1253         if (pll->lock)
1254                 spin_unlock_irqrestore(pll->lock, flags);
1255
1256         return ret;
1257 }
1258
1259 static void clk_plle_tegra114_disable(struct clk_hw *hw)
1260 {
1261         struct tegra_clk_pll *pll = to_clk_pll(hw);
1262         unsigned long flags = 0;
1263         u32 val;
1264
1265         if (pll->lock)
1266                 spin_lock_irqsave(pll->lock, flags);
1267
1268         _clk_pll_disable(hw);
1269
1270         val = pll_readl_misc(pll);
1271         val |= PLLE_MISC_IDDQ_SW_CTRL | PLLE_MISC_IDDQ_SW_VALUE;
1272         pll_writel_misc(val, pll);
1273         udelay(1);
1274
1275         if (pll->lock)
1276                 spin_unlock_irqrestore(pll->lock, flags);
1277 }
1278 #endif
1279
1280 static struct tegra_clk_pll *_tegra_init_pll(void __iomem *clk_base,
1281                 void __iomem *pmc, unsigned long fixed_rate,
1282                 struct tegra_clk_pll_params *pll_params, u32 pll_flags,
1283                 struct tegra_clk_pll_freq_table *freq_table, spinlock_t *lock)
1284 {
1285         struct tegra_clk_pll *pll;
1286
1287         pll = kzalloc(sizeof(*pll), GFP_KERNEL);
1288         if (!pll)
1289                 return ERR_PTR(-ENOMEM);
1290
1291         pll->clk_base = clk_base;
1292         pll->pmc = pmc;
1293
1294         pll->freq_table = freq_table;
1295         pll->params = pll_params;
1296         pll->fixed_rate = fixed_rate;
1297         pll->flags = pll_flags;
1298         pll->lock = lock;
1299
1300         if (!pll_params->div_nmp)
1301                 pll_params->div_nmp = &default_nmp;
1302
1303         return pll;
1304 }
1305
1306 static struct clk *_tegra_clk_register_pll(struct tegra_clk_pll *pll,
1307                 const char *name, const char *parent_name, unsigned long flags,
1308                 const struct clk_ops *ops)
1309 {
1310         struct clk_init_data init;
1311
1312         init.name = name;
1313         init.ops = ops;
1314         init.flags = flags;
1315         init.parent_names = (parent_name ? &parent_name : NULL);
1316         init.num_parents = (parent_name ? 1 : 0);
1317
1318         /* Data in .init is copied by clk_register(), so stack variable OK */
1319         pll->hw.init = &init;
1320
1321         return clk_register(NULL, &pll->hw);
1322 }
1323
1324 struct clk *tegra_clk_register_pll(const char *name, const char *parent_name,
1325                 void __iomem *clk_base, void __iomem *pmc,
1326                 unsigned long flags, unsigned long fixed_rate,
1327                 struct tegra_clk_pll_params *pll_params, u32 pll_flags,
1328                 struct tegra_clk_pll_freq_table *freq_table, spinlock_t *lock)
1329 {
1330         struct tegra_clk_pll *pll;
1331         struct clk *clk;
1332
1333         pll_flags |= TEGRA_PLL_BYPASS;
1334         pll_flags |= TEGRA_PLL_HAS_LOCK_ENABLE;
1335         pll = _tegra_init_pll(clk_base, pmc, fixed_rate, pll_params, pll_flags,
1336                               freq_table, lock);
1337         if (IS_ERR(pll))
1338                 return ERR_CAST(pll);
1339
1340         clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
1341                                       &tegra_clk_pll_ops);
1342         if (IS_ERR(clk))
1343                 kfree(pll);
1344
1345         return clk;
1346 }
1347
1348 struct clk *tegra_clk_register_plle(const char *name, const char *parent_name,
1349                 void __iomem *clk_base, void __iomem *pmc,
1350                 unsigned long flags, unsigned long fixed_rate,
1351                 struct tegra_clk_pll_params *pll_params, u32 pll_flags,
1352                 struct tegra_clk_pll_freq_table *freq_table, spinlock_t *lock)
1353 {
1354         struct tegra_clk_pll *pll;
1355         struct clk *clk;
1356
1357         pll_flags |= TEGRA_PLL_LOCK_MISC | TEGRA_PLL_BYPASS;
1358         pll_flags |= TEGRA_PLL_HAS_LOCK_ENABLE;
1359         pll = _tegra_init_pll(clk_base, pmc, fixed_rate, pll_params, pll_flags,
1360                               freq_table, lock);
1361         if (IS_ERR(pll))
1362                 return ERR_CAST(pll);
1363
1364         clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
1365                                       &tegra_clk_plle_ops);
1366         if (IS_ERR(clk))
1367                 kfree(pll);
1368
1369         return clk;
1370 }
1371
1372 #ifdef CONFIG_ARCH_TEGRA_114_SOC
1373 const struct clk_ops tegra_clk_pllxc_ops = {
1374         .is_enabled = clk_pll_is_enabled,
1375         .enable = clk_pll_iddq_enable,
1376         .disable = clk_pll_iddq_disable,
1377         .recalc_rate = clk_pll_recalc_rate,
1378         .round_rate = clk_pll_ramp_round_rate,
1379         .set_rate = clk_pllxc_set_rate,
1380 };
1381
1382 const struct clk_ops tegra_clk_pllm_ops = {
1383         .is_enabled = clk_pll_is_enabled,
1384         .enable = clk_pll_iddq_enable,
1385         .disable = clk_pll_iddq_disable,
1386         .recalc_rate = clk_pll_recalc_rate,
1387         .round_rate = clk_pll_ramp_round_rate,
1388         .set_rate = clk_pllm_set_rate,
1389 };
1390
1391 const struct clk_ops tegra_clk_pllc_ops = {
1392         .is_enabled = clk_pll_is_enabled,
1393         .enable = clk_pllc_enable,
1394         .disable = clk_pllc_disable,
1395         .recalc_rate = clk_pll_recalc_rate,
1396         .round_rate = clk_pll_ramp_round_rate,
1397         .set_rate = clk_pllc_set_rate,
1398 };
1399
1400 const struct clk_ops tegra_clk_pllre_ops = {
1401         .is_enabled = clk_pll_is_enabled,
1402         .enable = clk_pll_iddq_enable,
1403         .disable = clk_pll_iddq_disable,
1404         .recalc_rate = clk_pllre_recalc_rate,
1405         .round_rate = clk_pllre_round_rate,
1406         .set_rate = clk_pllre_set_rate,
1407 };
1408
1409 const struct clk_ops tegra_clk_plle_tegra114_ops = {
1410         .is_enabled =  clk_pll_is_enabled,
1411         .enable = clk_plle_tegra114_enable,
1412         .disable = clk_plle_tegra114_disable,
1413         .recalc_rate = clk_pll_recalc_rate,
1414 };
1415
1416
1417 struct clk *tegra_clk_register_pllxc(const char *name, const char *parent_name,
1418                           void __iomem *clk_base, void __iomem *pmc,
1419                           unsigned long flags, unsigned long fixed_rate,
1420                           struct tegra_clk_pll_params *pll_params,
1421                           u32 pll_flags,
1422                           struct tegra_clk_pll_freq_table *freq_table,
1423                           spinlock_t *lock)
1424 {
1425         struct tegra_clk_pll *pll;
1426         struct clk *clk;
1427
1428         if (!pll_params->pdiv_tohw)
1429                 return ERR_PTR(-EINVAL);
1430
1431         pll_flags |= TEGRA_PLL_HAS_LOCK_ENABLE;
1432         pll = _tegra_init_pll(clk_base, pmc, fixed_rate, pll_params, pll_flags,
1433                               freq_table, lock);
1434         if (IS_ERR(pll))
1435                 return ERR_CAST(pll);
1436
1437         clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
1438                                       &tegra_clk_pllxc_ops);
1439         if (IS_ERR(clk))
1440                 kfree(pll);
1441
1442         return clk;
1443 }
1444
1445 struct clk *tegra_clk_register_pllre(const char *name, const char *parent_name,
1446                           void __iomem *clk_base, void __iomem *pmc,
1447                           unsigned long flags, unsigned long fixed_rate,
1448                           struct tegra_clk_pll_params *pll_params,
1449                           u32 pll_flags,
1450                           struct tegra_clk_pll_freq_table *freq_table,
1451                           spinlock_t *lock, unsigned long parent_rate)
1452 {
1453         u32 val;
1454         struct tegra_clk_pll *pll;
1455         struct clk *clk;
1456
1457         pll_flags |= TEGRA_PLL_HAS_LOCK_ENABLE | TEGRA_PLL_LOCK_MISC;
1458         pll = _tegra_init_pll(clk_base, pmc, fixed_rate, pll_params, pll_flags,
1459                               freq_table, lock);
1460         if (IS_ERR(pll))
1461                 return ERR_CAST(pll);
1462
1463         /* program minimum rate by default */
1464
1465         val = pll_readl_base(pll);
1466         if (val & PLL_BASE_ENABLE)
1467                 WARN_ON(val & pll_params->iddq_bit_idx);
1468         else {
1469                 int m;
1470
1471                 m = _pll_fixed_mdiv(pll_params, parent_rate);
1472                 val = m << PLL_BASE_DIVM_SHIFT;
1473                 val |= (pll_params->vco_min / parent_rate)
1474                                 << PLL_BASE_DIVN_SHIFT;
1475                 pll_writel_base(val, pll);
1476         }
1477
1478         /* disable lock override */
1479
1480         val = pll_readl_misc(pll);
1481         val &= ~BIT(29);
1482         pll_writel_misc(val, pll);
1483
1484         clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
1485                                       &tegra_clk_pllre_ops);
1486         if (IS_ERR(clk))
1487                 kfree(pll);
1488
1489         return clk;
1490 }
1491
1492 struct clk *tegra_clk_register_pllm(const char *name, const char *parent_name,
1493                           void __iomem *clk_base, void __iomem *pmc,
1494                           unsigned long flags, unsigned long fixed_rate,
1495                           struct tegra_clk_pll_params *pll_params,
1496                           u32 pll_flags,
1497                           struct tegra_clk_pll_freq_table *freq_table,
1498                           spinlock_t *lock)
1499 {
1500         struct tegra_clk_pll *pll;
1501         struct clk *clk;
1502
1503         if (!pll_params->pdiv_tohw)
1504                 return ERR_PTR(-EINVAL);
1505
1506         pll_flags |= TEGRA_PLL_BYPASS;
1507         pll_flags |= TEGRA_PLL_HAS_LOCK_ENABLE;
1508         pll_flags |= TEGRA_PLLM;
1509         pll = _tegra_init_pll(clk_base, pmc, fixed_rate, pll_params, pll_flags,
1510                               freq_table, lock);
1511         if (IS_ERR(pll))
1512                 return ERR_CAST(pll);
1513
1514         clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
1515                                       &tegra_clk_pllm_ops);
1516         if (IS_ERR(clk))
1517                 kfree(pll);
1518
1519         return clk;
1520 }
1521
1522 struct clk *tegra_clk_register_pllc(const char *name, const char *parent_name,
1523                           void __iomem *clk_base, void __iomem *pmc,
1524                           unsigned long flags, unsigned long fixed_rate,
1525                           struct tegra_clk_pll_params *pll_params,
1526                           u32 pll_flags,
1527                           struct tegra_clk_pll_freq_table *freq_table,
1528                           spinlock_t *lock)
1529 {
1530         struct clk *parent, *clk;
1531         struct pdiv_map *p_tohw = pll_params->pdiv_tohw;
1532         struct tegra_clk_pll *pll;
1533         struct tegra_clk_pll_freq_table cfg;
1534         unsigned long parent_rate;
1535
1536         if (!p_tohw)
1537                 return ERR_PTR(-EINVAL);
1538
1539         parent = __clk_lookup(parent_name);
1540         if (IS_ERR(parent)) {
1541                 WARN(1, "parent clk %s of %s must be registered first\n",
1542                         name, parent_name);
1543                 return ERR_PTR(-EINVAL);
1544         }
1545
1546         pll_flags |= TEGRA_PLL_BYPASS;
1547         pll = _tegra_init_pll(clk_base, pmc, fixed_rate, pll_params, pll_flags,
1548                               freq_table, lock);
1549         if (IS_ERR(pll))
1550                 return ERR_CAST(pll);
1551
1552         parent_rate = __clk_get_rate(parent);
1553
1554         /*
1555          * Most of PLLC register fields are shadowed, and can not be read
1556          * directly from PLL h/w. Hence, actual PLLC boot state is unknown.
1557          * Initialize PLL to default state: disabled, reset; shadow registers
1558          * loaded with default parameters; dividers are preset for half of
1559          * minimum VCO rate (the latter assured that shadowed divider settings
1560          * are within supported range).
1561          */
1562
1563         cfg.m = _pll_fixed_mdiv(pll_params, parent_rate);
1564         cfg.n = cfg.m * pll_params->vco_min / parent_rate;
1565
1566         while (p_tohw->pdiv) {
1567                 if (p_tohw->pdiv == 2) {
1568                         cfg.p = p_tohw->hw_val;
1569                         break;
1570                 }
1571                 p_tohw++;
1572         }
1573
1574         if (!p_tohw->pdiv) {
1575                 WARN_ON(1);
1576                 return ERR_PTR(-EINVAL);
1577         }
1578
1579         pll_writel_base(0, pll);
1580         _update_pll_mnp(pll, &cfg);
1581
1582         pll_writel_misc(PLLCX_MISC_DEFAULT, pll);
1583         pll_writel(PLLCX_MISC1_DEFAULT, pll_params->ext_misc_reg[0], pll);
1584         pll_writel(PLLCX_MISC2_DEFAULT, pll_params->ext_misc_reg[1], pll);
1585         pll_writel(PLLCX_MISC3_DEFAULT, pll_params->ext_misc_reg[2], pll);
1586
1587         _pllcx_update_dynamic_coef(pll, parent_rate, cfg.n);
1588
1589         clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
1590                                       &tegra_clk_pllc_ops);
1591         if (IS_ERR(clk))
1592                 kfree(pll);
1593
1594         return clk;
1595 }
1596
1597 struct clk *tegra_clk_register_plle_tegra114(const char *name,
1598                                 const char *parent_name,
1599                                 void __iomem *clk_base, unsigned long flags,
1600                                 unsigned long fixed_rate,
1601                                 struct tegra_clk_pll_params *pll_params,
1602                                 struct tegra_clk_pll_freq_table *freq_table,
1603                                 spinlock_t *lock)
1604 {
1605         struct tegra_clk_pll *pll;
1606         struct clk *clk;
1607         u32 val, val_aux;
1608
1609         pll = _tegra_init_pll(clk_base, NULL, fixed_rate, pll_params,
1610                               TEGRA_PLL_HAS_LOCK_ENABLE, freq_table, lock);
1611         if (IS_ERR(pll))
1612                 return ERR_CAST(pll);
1613
1614         /* ensure parent is set to pll_re_vco */
1615
1616         val = pll_readl_base(pll);
1617         val_aux = pll_readl(pll_params->aux_reg, pll);
1618
1619         if (val & PLL_BASE_ENABLE) {
1620                 if (!(val_aux & PLLE_AUX_PLLRE_SEL))
1621                         WARN(1, "pll_e enabled with unsupported parent %s\n",
1622                           (val & PLLE_AUX_PLLP_SEL) ? "pllp_out0" : "pll_ref");
1623         } else {
1624                 val_aux |= PLLE_AUX_PLLRE_SEL;
1625                 pll_writel(val, pll_params->aux_reg, pll);
1626         }
1627
1628         clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
1629                                       &tegra_clk_plle_tegra114_ops);
1630         if (IS_ERR(clk))
1631                 kfree(pll);
1632
1633         return clk;
1634 }
1635 #endif