drivers/clk/tegra/clk-pll.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (c) 2012, 2013, NVIDIA CORPORATION.  All rights reserved.
   4  */
   5
   6 #include <linux/slab.h>
   7 #include <linux/io.h>
   8 #include <linux/delay.h>
   9 #include <linux/err.h>
  10 #include <linux/clk.h>
  11 #include <linux/clk-provider.h>
  12
  13 #include "clk.h"
  14
  15 #define PLL_BASE_BYPASS BIT(31)
  16 #define PLL_BASE_ENABLE BIT(30)
  17 #define PLL_BASE_REF_ENABLE BIT(29)
  18 #define PLL_BASE_OVERRIDE BIT(28)
  19
  20 #define PLL_BASE_DIVP_SHIFT 20
  21 #define PLL_BASE_DIVP_WIDTH 3
  22 #define PLL_BASE_DIVN_SHIFT 8
  23 #define PLL_BASE_DIVN_WIDTH 10
  24 #define PLL_BASE_DIVM_SHIFT 0
  25 #define PLL_BASE_DIVM_WIDTH 5
  26 #define PLLU_POST_DIVP_MASK 0x1
  27
  28 #define PLL_MISC_DCCON_SHIFT 20
  29 #define PLL_MISC_CPCON_SHIFT 8
  30 #define PLL_MISC_CPCON_WIDTH 4
  31 #define PLL_MISC_CPCON_MASK ((1 << PLL_MISC_CPCON_WIDTH) - 1)
  32 #define PLL_MISC_LFCON_SHIFT 4
  33 #define PLL_MISC_LFCON_WIDTH 4
  34 #define PLL_MISC_LFCON_MASK ((1 << PLL_MISC_LFCON_WIDTH) - 1)
  35 #define PLL_MISC_VCOCON_SHIFT 0
  36 #define PLL_MISC_VCOCON_WIDTH 4
  37 #define PLL_MISC_VCOCON_MASK ((1 << PLL_MISC_VCOCON_WIDTH) - 1)
  38
  39 #define OUT_OF_TABLE_CPCON 8
  40
  41 #define PMC_PLLP_WB0_OVERRIDE 0xf8
  42 #define PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE BIT(12)
  43 #define PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE BIT(11)
  44
  45 #define PLL_POST_LOCK_DELAY 50
  46
  47 #define PLLDU_LFCON_SET_DIVN 600
  48
  49 #define PLLE_BASE_DIVCML_SHIFT 24
  50 #define PLLE_BASE_DIVCML_MASK 0xf
  51 #define PLLE_BASE_DIVP_SHIFT 16
  52 #define PLLE_BASE_DIVP_WIDTH 6
  53 #define PLLE_BASE_DIVN_SHIFT 8
  54 #define PLLE_BASE_DIVN_WIDTH 8
  55 #define PLLE_BASE_DIVM_SHIFT 0
  56 #define PLLE_BASE_DIVM_WIDTH 8
  57 #define PLLE_BASE_ENABLE BIT(31)
  58
  59 #define PLLE_MISC_SETUP_BASE_SHIFT 16
  60 #define PLLE_MISC_SETUP_BASE_MASK (0xffff << PLLE_MISC_SETUP_BASE_SHIFT)
  61 #define PLLE_MISC_LOCK_ENABLE BIT(9)
  62 #define PLLE_MISC_READY BIT(15)
  63 #define PLLE_MISC_SETUP_EX_SHIFT 2
  64 #define PLLE_MISC_SETUP_EX_MASK (3 << PLLE_MISC_SETUP_EX_SHIFT)
  65 #define PLLE_MISC_SETUP_MASK (PLLE_MISC_SETUP_BASE_MASK |       \
  66                               PLLE_MISC_SETUP_EX_MASK)
  67 #define PLLE_MISC_SETUP_VALUE (7 << PLLE_MISC_SETUP_BASE_SHIFT)
  68
  69 #define PLLE_SS_CTRL 0x68
  70 #define PLLE_SS_CNTL_BYPASS_SS BIT(10)
  71 #define PLLE_SS_CNTL_INTERP_RESET BIT(11)
  72 #define PLLE_SS_CNTL_SSC_BYP BIT(12)
  73 #define PLLE_SS_CNTL_CENTER BIT(14)
  74 #define PLLE_SS_CNTL_INVERT BIT(15)
  75 #define PLLE_SS_DISABLE (PLLE_SS_CNTL_BYPASS_SS | PLLE_SS_CNTL_INTERP_RESET |\
  76                                 PLLE_SS_CNTL_SSC_BYP)
  77 #define PLLE_SS_MAX_MASK 0x1ff
  78 #define PLLE_SS_MAX_VAL_TEGRA114 0x25
  79 #define PLLE_SS_MAX_VAL_TEGRA210 0x21
  80 #define PLLE_SS_INC_MASK (0xff << 16)
  81 #define PLLE_SS_INC_VAL (0x1 << 16)
  82 #define PLLE_SS_INCINTRV_MASK (0x3f << 24)
  83 #define PLLE_SS_INCINTRV_VAL_TEGRA114 (0x20 << 24)
  84 #define PLLE_SS_INCINTRV_VAL_TEGRA210 (0x23 << 24)
  85 #define PLLE_SS_COEFFICIENTS_MASK \
  86         (PLLE_SS_MAX_MASK | PLLE_SS_INC_MASK | PLLE_SS_INCINTRV_MASK)
  87 #define PLLE_SS_COEFFICIENTS_VAL_TEGRA114 \
  88         (PLLE_SS_MAX_VAL_TEGRA114 | PLLE_SS_INC_VAL |\
  89          PLLE_SS_INCINTRV_VAL_TEGRA114)
  90 #define PLLE_SS_COEFFICIENTS_VAL_TEGRA210 \
  91         (PLLE_SS_MAX_VAL_TEGRA210 | PLLE_SS_INC_VAL |\
  92          PLLE_SS_INCINTRV_VAL_TEGRA210)
  93
  94 #define PLLE_AUX_PLLP_SEL       BIT(2)
  95 #define PLLE_AUX_USE_LOCKDET    BIT(3)
  96 #define PLLE_AUX_ENABLE_SWCTL   BIT(4)
  97 #define PLLE_AUX_SS_SWCTL       BIT(6)
  98 #define PLLE_AUX_SEQ_ENABLE     BIT(24)
  99 #define PLLE_AUX_SEQ_START_STATE BIT(25)
 100 #define PLLE_AUX_PLLRE_SEL      BIT(28)
 101 #define PLLE_AUX_SS_SEQ_INCLUDE BIT(31)
 102
 103 #define XUSBIO_PLL_CFG0         0x51c
 104 #define XUSBIO_PLL_CFG0_PADPLL_RESET_SWCTL      BIT(0)
 105 #define XUSBIO_PLL_CFG0_CLK_ENABLE_SWCTL        BIT(2)
 106 #define XUSBIO_PLL_CFG0_PADPLL_USE_LOCKDET      BIT(6)
 107 #define XUSBIO_PLL_CFG0_SEQ_ENABLE              BIT(24)
 108 #define XUSBIO_PLL_CFG0_SEQ_START_STATE         BIT(25)
 109
 110 #define SATA_PLL_CFG0           0x490
 111 #define SATA_PLL_CFG0_PADPLL_RESET_SWCTL        BIT(0)
 112 #define SATA_PLL_CFG0_PADPLL_USE_LOCKDET        BIT(2)
 113 #define SATA_PLL_CFG0_SEQ_ENABLE                BIT(24)
 114 #define SATA_PLL_CFG0_SEQ_START_STATE           BIT(25)
 115
 116 #define PLLE_MISC_PLLE_PTS      BIT(8)
 117 #define PLLE_MISC_IDDQ_SW_VALUE BIT(13)
 118 #define PLLE_MISC_IDDQ_SW_CTRL  BIT(14)
 119 #define PLLE_MISC_VREG_BG_CTRL_SHIFT    4
 120 #define PLLE_MISC_VREG_BG_CTRL_MASK     (3 << PLLE_MISC_VREG_BG_CTRL_SHIFT)
 121 #define PLLE_MISC_VREG_CTRL_SHIFT       2
 122 #define PLLE_MISC_VREG_CTRL_MASK        (2 << PLLE_MISC_VREG_CTRL_SHIFT)
 123
 124 #define PLLCX_MISC_STROBE       BIT(31)
 125 #define PLLCX_MISC_RESET        BIT(30)
 126 #define PLLCX_MISC_SDM_DIV_SHIFT 28
 127 #define PLLCX_MISC_SDM_DIV_MASK (0x3 << PLLCX_MISC_SDM_DIV_SHIFT)
 128 #define PLLCX_MISC_FILT_DIV_SHIFT 26
 129 #define PLLCX_MISC_FILT_DIV_MASK (0x3 << PLLCX_MISC_FILT_DIV_SHIFT)
 130 #define PLLCX_MISC_ALPHA_SHIFT 18
 131 #define PLLCX_MISC_DIV_LOW_RANGE \
 132                 ((0x1 << PLLCX_MISC_SDM_DIV_SHIFT) | \
 133                 (0x1 << PLLCX_MISC_FILT_DIV_SHIFT))
 134 #define PLLCX_MISC_DIV_HIGH_RANGE \
 135                 ((0x2 << PLLCX_MISC_SDM_DIV_SHIFT) | \
 136                 (0x2 << PLLCX_MISC_FILT_DIV_SHIFT))
 137 #define PLLCX_MISC_COEF_LOW_RANGE \
 138                 ((0x14 << PLLCX_MISC_KA_SHIFT) | (0x38 << PLLCX_MISC_KB_SHIFT))
 139 #define PLLCX_MISC_KA_SHIFT 2
 140 #define PLLCX_MISC_KB_SHIFT 9
 141 #define PLLCX_MISC_DEFAULT (PLLCX_MISC_COEF_LOW_RANGE | \
 142                             (0x19 << PLLCX_MISC_ALPHA_SHIFT) | \
 143                             PLLCX_MISC_DIV_LOW_RANGE | \
 144                             PLLCX_MISC_RESET)
 145 #define PLLCX_MISC1_DEFAULT 0x000d2308
 146 #define PLLCX_MISC2_DEFAULT 0x30211200
 147 #define PLLCX_MISC3_DEFAULT 0x200
 148
 149 #define PMC_SATA_PWRGT 0x1ac
 150 #define PMC_SATA_PWRGT_PLLE_IDDQ_VALUE BIT(5)
 151 #define PMC_SATA_PWRGT_PLLE_IDDQ_SWCTL BIT(4)
 152
 153 #define PLLSS_MISC_KCP          0
 154 #define PLLSS_MISC_KVCO         0
 155 #define PLLSS_MISC_SETUP        0
 156 #define PLLSS_EN_SDM            0
 157 #define PLLSS_EN_SSC            0
 158 #define PLLSS_EN_DITHER2        0
 159 #define PLLSS_EN_DITHER         1
 160 #define PLLSS_SDM_RESET         0
 161 #define PLLSS_CLAMP             0
 162 #define PLLSS_SDM_SSC_MAX       0
 163 #define PLLSS_SDM_SSC_MIN       0
 164 #define PLLSS_SDM_SSC_STEP      0
 165 #define PLLSS_SDM_DIN           0
 166 #define PLLSS_MISC_DEFAULT ((PLLSS_MISC_KCP << 25) | \
 167                             (PLLSS_MISC_KVCO << 24) | \
 168                             PLLSS_MISC_SETUP)
 169 #define PLLSS_CFG_DEFAULT ((PLLSS_EN_SDM << 31) | \
 170                            (PLLSS_EN_SSC << 30) | \
 171                            (PLLSS_EN_DITHER2 << 29) | \
 172                            (PLLSS_EN_DITHER << 28) | \
 173                            (PLLSS_SDM_RESET) << 27 | \
 174                            (PLLSS_CLAMP << 22))
 175 #define PLLSS_CTRL1_DEFAULT \
 176                         ((PLLSS_SDM_SSC_MAX << 16) | PLLSS_SDM_SSC_MIN)
 177 #define PLLSS_CTRL2_DEFAULT \
 178                         ((PLLSS_SDM_SSC_STEP << 16) | PLLSS_SDM_DIN)
 179 #define PLLSS_LOCK_OVERRIDE     BIT(24)
 180 #define PLLSS_REF_SRC_SEL_SHIFT 25
 181 #define PLLSS_REF_SRC_SEL_MASK  (3 << PLLSS_REF_SRC_SEL_SHIFT)
 182
 183 #define UTMIP_PLL_CFG1 0x484
 184 #define UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(x) (((x) & 0xfff) << 0)
 185 #define UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(x) (((x) & 0x1f) << 27)
 186 #define UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN BIT(12)
 187 #define UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN BIT(14)
 188 #define UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP BIT(15)
 189 #define UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN BIT(16)
 190 #define UTMIP_PLL_CFG1_FORCE_PLLU_POWERUP BIT(17)
 191
 192 #define UTMIP_PLL_CFG2 0x488
 193 #define UTMIP_PLL_CFG2_STABLE_COUNT(x) (((x) & 0xfff) << 6)
 194 #define UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(x) (((x) & 0x3f) << 18)
 195 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN BIT(0)
 196 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERUP BIT(1)
 197 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN BIT(2)
 198 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERUP BIT(3)
 199 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN BIT(4)
 200 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERUP BIT(5)
 201 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_D_POWERDOWN BIT(24)
 202 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_D_POWERUP BIT(25)
 203 #define UTMIP_PLL_CFG2_PHY_XTAL_CLOCKEN BIT(30)
 204
 205 #define UTMIPLL_HW_PWRDN_CFG0 0x52c
 206 #define UTMIPLL_HW_PWRDN_CFG0_IDDQ_SWCTL BIT(0)
 207 #define UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE BIT(1)
 208 #define UTMIPLL_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL BIT(2)
 209 #define UTMIPLL_HW_PWRDN_CFG0_SEQ_IN_SWCTL BIT(4)
 210 #define UTMIPLL_HW_PWRDN_CFG0_SEQ_RESET_INPUT_VALUE BIT(5)
 211 #define UTMIPLL_HW_PWRDN_CFG0_USE_LOCKDET BIT(6)
 212 #define UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE BIT(24)
 213 #define UTMIPLL_HW_PWRDN_CFG0_SEQ_START_STATE BIT(25)
 214
 215 #define PLLU_HW_PWRDN_CFG0 0x530
 216 #define PLLU_HW_PWRDN_CFG0_CLK_SWITCH_SWCTL BIT(0)
 217 #define PLLU_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL BIT(2)
 218 #define PLLU_HW_PWRDN_CFG0_USE_LOCKDET BIT(6)
 219 #define PLLU_HW_PWRDN_CFG0_USE_SWITCH_DETECT BIT(7)
 220 #define PLLU_HW_PWRDN_CFG0_SEQ_ENABLE BIT(24)
 221 #define PLLU_HW_PWRDN_CFG0_IDDQ_PD_INCLUDE BIT(28)
 222
 223 #define XUSB_PLL_CFG0 0x534
 224 #define XUSB_PLL_CFG0_UTMIPLL_LOCK_DLY 0x3ff
 225 #define XUSB_PLL_CFG0_PLLU_LOCK_DLY (0x3ff << 14)
 226
 227 #define PLLU_BASE_CLKENABLE_USB BIT(21)
 228 #define PLLU_BASE_OVERRIDE BIT(24)
 229
 230 #define pll_readl(offset, p) readl_relaxed(p->clk_base + offset)
 231 #define pll_readl_base(p) pll_readl(p->params->base_reg, p)
 232 #define pll_readl_misc(p) pll_readl(p->params->misc_reg, p)
 233 #define pll_override_readl(offset, p) readl_relaxed(p->pmc + offset)
 234 #define pll_readl_sdm_din(p) pll_readl(p->params->sdm_din_reg, p)
 235 #define pll_readl_sdm_ctrl(p) pll_readl(p->params->sdm_ctrl_reg, p)
 236
 237 #define pll_writel(val, offset, p) writel_relaxed(val, p->clk_base + offset)
 238 #define pll_writel_base(val, p) pll_writel(val, p->params->base_reg, p)
 239 #define pll_writel_misc(val, p) pll_writel(val, p->params->misc_reg, p)
 240 #define pll_override_writel(val, offset, p) writel(val, p->pmc + offset)
 241 #define pll_writel_sdm_din(val, p) pll_writel(val, p->params->sdm_din_reg, p)
 242 #define pll_writel_sdm_ctrl(val, p) pll_writel(val, p->params->sdm_ctrl_reg, p)
 243
 244 #define mask(w) ((1 << (w)) - 1)
 245 #define divm_mask(p) mask(p->params->div_nmp->divm_width)
 246 #define divn_mask(p) mask(p->params->div_nmp->divn_width)
 247 #define divp_mask(p) (p->params->flags & TEGRA_PLLU ? PLLU_POST_DIVP_MASK :\
 248                       mask(p->params->div_nmp->divp_width))
 249 #define sdm_din_mask(p) p->params->sdm_din_mask
 250 #define sdm_en_mask(p) p->params->sdm_ctrl_en_mask
 251
 252 #define divm_shift(p) (p)->params->div_nmp->divm_shift
 253 #define divn_shift(p) (p)->params->div_nmp->divn_shift
 254 #define divp_shift(p) (p)->params->div_nmp->divp_shift
 255
 256 #define divm_mask_shifted(p) (divm_mask(p) << divm_shift(p))
 257 #define divn_mask_shifted(p) (divn_mask(p) << divn_shift(p))
 258 #define divp_mask_shifted(p) (divp_mask(p) << divp_shift(p))
 259
 260 #define divm_max(p) (divm_mask(p))
 261 #define divn_max(p) (divn_mask(p))
 262 #define divp_max(p) (1 << (divp_mask(p)))
 263
 264 #define sdin_din_to_data(din)   ((u16)((din) ? : 0xFFFFU))
 265 #define sdin_data_to_din(dat)   (((dat) == 0xFFFFU) ? 0 : (s16)dat)
 266
 267 static struct div_nmp default_nmp = {
 268         .divn_shift = PLL_BASE_DIVN_SHIFT,
 269         .divn_width = PLL_BASE_DIVN_WIDTH,
 270         .divm_shift = PLL_BASE_DIVM_SHIFT,
 271         .divm_width = PLL_BASE_DIVM_WIDTH,
 272         .divp_shift = PLL_BASE_DIVP_SHIFT,
 273         .divp_width = PLL_BASE_DIVP_WIDTH,
 274 };
 275
 276 static void clk_pll_enable_lock(struct tegra_clk_pll *pll)
 277 {
 278         u32 val;
 279
 280         if (!(pll->params->flags & TEGRA_PLL_USE_LOCK))
 281                 return;
 282
 283         if (!(pll->params->flags & TEGRA_PLL_HAS_LOCK_ENABLE))
 284                 return;
 285
 286         val = pll_readl_misc(pll);
 287         val |= BIT(pll->params->lock_enable_bit_idx);
 288         pll_writel_misc(val, pll);
 289 }
 290
 291 static int clk_pll_wait_for_lock(struct tegra_clk_pll *pll)
 292 {
 293         int i;
 294         u32 val, lock_mask;
 295         void __iomem *lock_addr;
 296
 297         if (!(pll->params->flags & TEGRA_PLL_USE_LOCK)) {
 298                 udelay(pll->params->lock_delay);
 299                 return 0;
 300         }
 301
 302         lock_addr = pll->clk_base;
 303         if (pll->params->flags & TEGRA_PLL_LOCK_MISC)
 304                 lock_addr += pll->params->misc_reg;
 305         else
 306                 lock_addr += pll->params->base_reg;
 307
 308         lock_mask = pll->params->lock_mask;
 309
 310         for (i = 0; i < pll->params->lock_delay; i++) {
 311                 val = readl_relaxed(lock_addr);
 312                 if ((val & lock_mask) == lock_mask) {
 313                         udelay(PLL_POST_LOCK_DELAY);
 314                         return 0;
 315                 }
 316                 udelay(2); /* timeout = 2 * lock time */
 317         }
 318
 319         pr_err("%s: Timed out waiting for pll %s lock\n", __func__,
 320                clk_hw_get_name(&pll->hw));
 321
 322         return -1;
 323 }
 324
 325 int tegra_pll_wait_for_lock(struct tegra_clk_pll *pll)
 326 {
 327         return clk_pll_wait_for_lock(pll);
 328 }
 329
 330 static bool pllm_clk_is_gated_by_pmc(struct tegra_clk_pll *pll)
 331 {
 332         u32 val = readl_relaxed(pll->pmc + PMC_PLLP_WB0_OVERRIDE);
 333
 334         return (val & PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE) &&
 335               !(val & PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE);
 336 }
 337
 338 static int clk_pll_is_enabled(struct clk_hw *hw)
 339 {
 340         struct tegra_clk_pll *pll = to_clk_pll(hw);
 341         u32 val;
 342
 343         /*
 344          * Power Management Controller (PMC) can override the PLLM clock
 345          * settings, including the enable-state. The PLLM is enabled when
 346          * PLLM's CaR state is ON and when PLLM isn't gated by PMC.
 347          */
 348         if ((pll->params->flags & TEGRA_PLLM) && pllm_clk_is_gated_by_pmc(pll))
 349                 return 0;
 350
 351         val = pll_readl_base(pll);
 352
 353         return val & PLL_BASE_ENABLE ? 1 : 0;
 354 }
 355
 356 static void _clk_pll_enable(struct clk_hw *hw)
 357 {
 358         struct tegra_clk_pll *pll = to_clk_pll(hw);
 359         u32 val;
 360
 361         if (pll->params->iddq_reg) {
 362                 val = pll_readl(pll->params->iddq_reg, pll);
 363                 val &= ~BIT(pll->params->iddq_bit_idx);
 364                 pll_writel(val, pll->params->iddq_reg, pll);
 365                 udelay(5);
 366         }
 367
 368         if (pll->params->reset_reg) {
 369                 val = pll_readl(pll->params->reset_reg, pll);
 370                 val &= ~BIT(pll->params->reset_bit_idx);
 371                 pll_writel(val, pll->params->reset_reg, pll);
 372         }
 373
 374         clk_pll_enable_lock(pll);
 375
 376         val = pll_readl_base(pll);
 377         if (pll->params->flags & TEGRA_PLL_BYPASS)
 378                 val &= ~PLL_BASE_BYPASS;
 379         val |= PLL_BASE_ENABLE;
 380         pll_writel_base(val, pll);
 381
 382         if (pll->params->flags & TEGRA_PLLM) {
 383                 val = readl_relaxed(pll->pmc + PMC_PLLP_WB0_OVERRIDE);
 384                 val |= PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE;
 385                 writel_relaxed(val, pll->pmc + PMC_PLLP_WB0_OVERRIDE);
 386         }
 387 }
 388
 389 static void _clk_pll_disable(struct clk_hw *hw)
 390 {
 391         struct tegra_clk_pll *pll = to_clk_pll(hw);
 392         u32 val;
 393
 394         val = pll_readl_base(pll);
 395         if (pll->params->flags & TEGRA_PLL_BYPASS)
 396                 val &= ~PLL_BASE_BYPASS;
 397         val &= ~PLL_BASE_ENABLE;
 398         pll_writel_base(val, pll);
 399
 400         if (pll->params->flags & TEGRA_PLLM) {
 401                 val = readl_relaxed(pll->pmc + PMC_PLLP_WB0_OVERRIDE);
 402                 val &= ~PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE;
 403                 writel_relaxed(val, pll->pmc + PMC_PLLP_WB0_OVERRIDE);
 404         }
 405
 406         if (pll->params->reset_reg) {
 407                 val = pll_readl(pll->params->reset_reg, pll);
 408                 val |= BIT(pll->params->reset_bit_idx);
 409                 pll_writel(val, pll->params->reset_reg, pll);
 410         }
 411
 412         if (pll->params->iddq_reg) {
 413                 val = pll_readl(pll->params->iddq_reg, pll);
 414                 val |= BIT(pll->params->iddq_bit_idx);
 415                 pll_writel(val, pll->params->iddq_reg, pll);
 416                 udelay(2);
 417         }
 418 }
 419
 420 static void pll_clk_start_ss(struct tegra_clk_pll *pll)
 421 {
 422         if (pll->params->defaults_set && pll->params->ssc_ctrl_reg) {
 423                 u32 val = pll_readl(pll->params->ssc_ctrl_reg, pll);
 424
 425                 val |= pll->params->ssc_ctrl_en_mask;
 426                 pll_writel(val, pll->params->ssc_ctrl_reg, pll);
 427         }
 428 }
 429
 430 static void pll_clk_stop_ss(struct tegra_clk_pll *pll)
 431 {
 432         if (pll->params->defaults_set && pll->params->ssc_ctrl_reg) {
 433                 u32 val = pll_readl(pll->params->ssc_ctrl_reg, pll);
 434
 435                 val &= ~pll->params->ssc_ctrl_en_mask;
 436                 pll_writel(val, pll->params->ssc_ctrl_reg, pll);
 437         }
 438 }
 439
 440 static int clk_pll_enable(struct clk_hw *hw)
 441 {
 442         struct tegra_clk_pll *pll = to_clk_pll(hw);
 443         unsigned long flags = 0;
 444         int ret;
 445
 446         if (clk_pll_is_enabled(hw))
 447                 return 0;
 448
 449         if (pll->lock)
 450                 spin_lock_irqsave(pll->lock, flags);
 451
 452         _clk_pll_enable(hw);
 453
 454         ret = clk_pll_wait_for_lock(pll);
 455
 456         pll_clk_start_ss(pll);
 457
 458         if (pll->lock)
 459                 spin_unlock_irqrestore(pll->lock, flags);
 460
 461         return ret;
 462 }
 463
 464 static void clk_pll_disable(struct clk_hw *hw)
 465 {
 466         struct tegra_clk_pll *pll = to_clk_pll(hw);
 467         unsigned long flags = 0;
 468
 469         if (pll->lock)
 470                 spin_lock_irqsave(pll->lock, flags);
 471
 472         pll_clk_stop_ss(pll);
 473
 474         _clk_pll_disable(hw);
 475
 476         if (pll->lock)
 477                 spin_unlock_irqrestore(pll->lock, flags);
 478 }
 479
 480 static int _p_div_to_hw(struct clk_hw *hw, u8 p_div)
 481 {
 482         struct tegra_clk_pll *pll = to_clk_pll(hw);
 483         const struct pdiv_map *p_tohw = pll->params->pdiv_tohw;
 484
 485         if (p_tohw) {
 486                 while (p_tohw->pdiv) {
 487                         if (p_div <= p_tohw->pdiv)
 488                                 return p_tohw->hw_val;
 489                         p_tohw++;
 490                 }
 491                 return -EINVAL;
 492         }
 493         return -EINVAL;
 494 }
 495
 496 int tegra_pll_p_div_to_hw(struct tegra_clk_pll *pll, u8 p_div)
 497 {
 498         return _p_div_to_hw(&pll->hw, p_div);
 499 }
 500
 501 static int _hw_to_p_div(struct clk_hw *hw, u8 p_div_hw)
 502 {
 503         struct tegra_clk_pll *pll = to_clk_pll(hw);
 504         const struct pdiv_map *p_tohw = pll->params->pdiv_tohw;
 505
 506         if (p_tohw) {
 507                 while (p_tohw->pdiv) {
 508                         if (p_div_hw == p_tohw->hw_val)
 509                                 return p_tohw->pdiv;
 510                         p_tohw++;
 511                 }
 512                 return -EINVAL;
 513         }
 514
 515         return 1 << p_div_hw;
 516 }
 517
 518 static int _get_table_rate(struct clk_hw *hw,
 519                            struct tegra_clk_pll_freq_table *cfg,
 520                            unsigned long rate, unsigned long parent_rate)
 521 {
 522         struct tegra_clk_pll *pll = to_clk_pll(hw);
 523         struct tegra_clk_pll_freq_table *sel;
 524         int p;
 525
 526         for (sel = pll->params->freq_table; sel->input_rate != 0; sel++)
 527                 if (sel->input_rate == parent_rate &&
 528                     sel->output_rate == rate)
 529                         break;
 530
 531         if (sel->input_rate == 0)
 532                 return -EINVAL;
 533
 534         if (pll->params->pdiv_tohw) {
 535                 p = _p_div_to_hw(hw, sel->p);
 536                 if (p < 0)
 537                         return p;
 538         } else {
 539                 p = ilog2(sel->p);
 540         }
 541
 542         cfg->input_rate = sel->input_rate;
 543         cfg->output_rate = sel->output_rate;
 544         cfg->m = sel->m;
 545         cfg->n = sel->n;
 546         cfg->p = p;
 547         cfg->cpcon = sel->cpcon;
 548         cfg->sdm_data = sel->sdm_data;
 549
 550         return 0;
 551 }
 552
 553 static int _calc_rate(struct clk_hw *hw, struct tegra_clk_pll_freq_table *cfg,
 554                       unsigned long rate, unsigned long parent_rate)
 555 {
 556         struct tegra_clk_pll *pll = to_clk_pll(hw);
 557         unsigned long cfreq;
 558         u32 p_div = 0;
 559         int ret;
 560
 561         if (!rate)
 562                 return -EINVAL;
 563
 564         switch (parent_rate) {
 565         case 12000000:
 566         case 26000000:
 567                 cfreq = (rate <= 1000000 * 1000) ? 1000000 : 2000000;
 568                 break;
 569         case 13000000:
 570                 cfreq = (rate <= 1000000 * 1000) ? 1000000 : 2600000;
 571                 break;
 572         case 16800000:
 573         case 19200000:
 574                 cfreq = (rate <= 1200000 * 1000) ? 1200000 : 2400000;
 575                 break;
 576         case 9600000:
 577         case 28800000:
 578                 /*
 579                  * PLL_P_OUT1 rate is not listed in PLLA table
 580                  */
 581                 cfreq = parent_rate / (parent_rate / 1000000);
 582                 break;
 583         default:
 584                 pr_err("%s Unexpected reference rate %lu\n",
 585                        __func__, parent_rate);
 586                 BUG();
 587         }
 588
 589         /* Raise VCO to guarantee 0.5% accuracy */
 590         for (cfg->output_rate = rate; cfg->output_rate < 200 * cfreq;
 591              cfg->output_rate <<= 1)
 592                 p_div++;
 593
 594         cfg->m = parent_rate / cfreq;
 595         cfg->n = cfg->output_rate / cfreq;
 596         cfg->cpcon = OUT_OF_TABLE_CPCON;
 597
 598         if (cfg->m == 0 || cfg->m > divm_max(pll) ||
 599             cfg->n > divn_max(pll) || (1 << p_div) > divp_max(pll) ||
 600             cfg->output_rate > pll->params->vco_max) {
 601                 return -EINVAL;
 602         }
 603
 604         cfg->output_rate = cfg->n * DIV_ROUND_UP(parent_rate, cfg->m);
 605         cfg->output_rate >>= p_div;
 606
 607         if (pll->params->pdiv_tohw) {
 608                 ret = _p_div_to_hw(hw, 1 << p_div);
 609                 if (ret < 0)
 610                         return ret;
 611                 else
 612                         cfg->p = ret;
 613         } else
 614                 cfg->p = p_div;
 615
 616         return 0;
 617 }
 618
 619 /*
 620  * SDM (Sigma Delta Modulator) divisor is 16-bit 2's complement signed number
 621  * within (-2^12 ... 2^12-1) range. Represented in PLL data structure as
 622  * unsigned 16-bit value, with "0" divisor mapped to 0xFFFF. Data "0" is used
 623  * to indicate that SDM is disabled.
 624  *
 625  * Effective ndiv value when SDM is enabled: ndiv + 1/2 + sdm_din/2^13
 626  */
 627 static void clk_pll_set_sdm_data(struct clk_hw *hw,
 628                                  struct tegra_clk_pll_freq_table *cfg)
 629 {
 630         struct tegra_clk_pll *pll = to_clk_pll(hw);
 631         u32 val;
 632         bool enabled;
 633
 634         if (!pll->params->sdm_din_reg)
 635                 return;
 636
 637         if (cfg->sdm_data) {
 638                 val = pll_readl_sdm_din(pll) & (~sdm_din_mask(pll));
 639                 val |= sdin_data_to_din(cfg->sdm_data) & sdm_din_mask(pll);
 640                 pll_writel_sdm_din(val, pll);
 641         }
 642
 643         val = pll_readl_sdm_ctrl(pll);
 644         enabled = (val & sdm_en_mask(pll));
 645
 646         if (cfg->sdm_data == 0 && enabled)
 647                 val &= ~pll->params->sdm_ctrl_en_mask;
 648
 649         if (cfg->sdm_data != 0 && !enabled)
 650                 val |= pll->params->sdm_ctrl_en_mask;
 651
 652         pll_writel_sdm_ctrl(val, pll);
 653 }
 654
 655 static void _update_pll_mnp(struct tegra_clk_pll *pll,
 656                             struct tegra_clk_pll_freq_table *cfg)
 657 {
 658         u32 val;
 659         struct tegra_clk_pll_params *params = pll->params;
 660         struct div_nmp *div_nmp = params->div_nmp;
 661
 662         if ((params->flags & (TEGRA_PLLM | TEGRA_PLLMB)) &&
 663                 (pll_override_readl(PMC_PLLP_WB0_OVERRIDE, pll) &
 664                         PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE)) {
 665                 val = pll_override_readl(params->pmc_divp_reg, pll);
 666                 val &= ~(divp_mask(pll) << div_nmp->override_divp_shift);
 667                 val |= cfg->p << div_nmp->override_divp_shift;
 668                 pll_override_writel(val, params->pmc_divp_reg, pll);
 669
 670                 val = pll_override_readl(params->pmc_divnm_reg, pll);
 671                 val &= ~((divm_mask(pll) << div_nmp->override_divm_shift) |
 672                         (divn_mask(pll) << div_nmp->override_divn_shift));
 673                 val |= (cfg->m << div_nmp->override_divm_shift) |
 674                         (cfg->n << div_nmp->override_divn_shift);
 675                 pll_override_writel(val, params->pmc_divnm_reg, pll);
 676         } else {
 677                 val = pll_readl_base(pll);
 678
 679                 val &= ~(divm_mask_shifted(pll) | divn_mask_shifted(pll) |
 680                          divp_mask_shifted(pll));
 681
 682                 val |= (cfg->m << divm_shift(pll)) |
 683                        (cfg->n << divn_shift(pll)) |
 684                        (cfg->p << divp_shift(pll));
 685
 686                 pll_writel_base(val, pll);
 687
 688                 clk_pll_set_sdm_data(&pll->hw, cfg);
 689         }
 690 }
 691
 692 static void _get_pll_mnp(struct tegra_clk_pll *pll,
 693                          struct tegra_clk_pll_freq_table *cfg)
 694 {
 695         u32 val;
 696         struct tegra_clk_pll_params *params = pll->params;
 697         struct div_nmp *div_nmp = params->div_nmp;
 698
 699         *cfg = (struct tegra_clk_pll_freq_table) { };
 700
 701         if ((params->flags & (TEGRA_PLLM | TEGRA_PLLMB)) &&
 702                 (pll_override_readl(PMC_PLLP_WB0_OVERRIDE, pll) &
 703                         PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE)) {
 704                 val = pll_override_readl(params->pmc_divp_reg, pll);
 705                 cfg->p = (val >> div_nmp->override_divp_shift) & divp_mask(pll);
 706
 707                 val = pll_override_readl(params->pmc_divnm_reg, pll);
 708                 cfg->m = (val >> div_nmp->override_divm_shift) & divm_mask(pll);
 709                 cfg->n = (val >> div_nmp->override_divn_shift) & divn_mask(pll);
 710         }  else {
 711                 val = pll_readl_base(pll);
 712
 713                 cfg->m = (val >> div_nmp->divm_shift) & divm_mask(pll);
 714                 cfg->n = (val >> div_nmp->divn_shift) & divn_mask(pll);
 715                 cfg->p = (val >> div_nmp->divp_shift) & divp_mask(pll);
 716
 717                 if (pll->params->sdm_din_reg) {
 718                         if (sdm_en_mask(pll) & pll_readl_sdm_ctrl(pll)) {
 719                                 val = pll_readl_sdm_din(pll);
 720                                 val &= sdm_din_mask(pll);
 721                                 cfg->sdm_data = sdin_din_to_data(val);
 722                         }
 723                 }
 724         }
 725 }
 726
 727 static void _update_pll_cpcon(struct tegra_clk_pll *pll,
 728                               struct tegra_clk_pll_freq_table *cfg,
 729                               unsigned long rate)
 730 {
 731         u32 val;
 732
 733         val = pll_readl_misc(pll);
 734
 735         val &= ~(PLL_MISC_CPCON_MASK << PLL_MISC_CPCON_SHIFT);
 736         val |= cfg->cpcon << PLL_MISC_CPCON_SHIFT;
 737
 738         if (pll->params->flags & TEGRA_PLL_SET_LFCON) {
 739                 val &= ~(PLL_MISC_LFCON_MASK << PLL_MISC_LFCON_SHIFT);
 740                 if (cfg->n >= PLLDU_LFCON_SET_DIVN)
 741                         val |= 1 << PLL_MISC_LFCON_SHIFT;
 742         } else if (pll->params->flags & TEGRA_PLL_SET_DCCON) {
 743                 val &= ~(1 << PLL_MISC_DCCON_SHIFT);
 744                 if (rate >= (pll->params->vco_max >> 1))
 745                         val |= 1 << PLL_MISC_DCCON_SHIFT;
 746         }
 747
 748         pll_writel_misc(val, pll);
 749 }
 750
 751 static int _program_pll(struct clk_hw *hw, struct tegra_clk_pll_freq_table *cfg,
 752                         unsigned long rate)
 753 {
 754         struct tegra_clk_pll *pll = to_clk_pll(hw);
 755         struct tegra_clk_pll_freq_table old_cfg;
 756         int state, ret = 0;
 757
 758         state = clk_pll_is_enabled(hw);
 759
 760         if (state && pll->params->pre_rate_change) {
 761                 ret = pll->params->pre_rate_change();
 762                 if (WARN_ON(ret))
 763                         return ret;
 764         }
 765
 766         _get_pll_mnp(pll, &old_cfg);
 767
 768         if (state && pll->params->defaults_set && pll->params->dyn_ramp &&
 769                         (cfg->m == old_cfg.m) && (cfg->p == old_cfg.p)) {
 770                 ret = pll->params->dyn_ramp(pll, cfg);
 771                 if (!ret)
 772                         goto done;
 773         }
 774
 775         if (state) {
 776                 pll_clk_stop_ss(pll);
 777                 _clk_pll_disable(hw);
 778         }
 779
 780         if (!pll->params->defaults_set && pll->params->set_defaults)
 781                 pll->params->set_defaults(pll);
 782
 783         _update_pll_mnp(pll, cfg);
 784
 785         if (pll->params->flags & TEGRA_PLL_HAS_CPCON)
 786                 _update_pll_cpcon(pll, cfg, rate);
 787
 788         if (state) {
 789                 _clk_pll_enable(hw);
 790                 ret = clk_pll_wait_for_lock(pll);
 791                 pll_clk_start_ss(pll);
 792         }
 793
 794 done:
 795         if (state && pll->params->post_rate_change)
 796                 pll->params->post_rate_change();
 797
 798         return ret;
 799 }
 800
 801 static int clk_pll_set_rate(struct clk_hw *hw, unsigned long rate,
 802                         unsigned long parent_rate)
 803 {
 804         struct tegra_clk_pll *pll = to_clk_pll(hw);
 805         struct tegra_clk_pll_freq_table cfg, old_cfg;
 806         unsigned long flags = 0;
 807         int ret = 0;
 808
 809         if (pll->params->flags & TEGRA_PLL_FIXED) {
 810                 if (rate != pll->params->fixed_rate) {
 811                         pr_err("%s: Can not change %s fixed rate %lu to %lu\n",
 812                                 __func__, clk_hw_get_name(hw),
 813                                 pll->params->fixed_rate, rate);
 814                         return -EINVAL;
 815                 }
 816                 return 0;
 817         }
 818
 819         if (_get_table_rate(hw, &cfg, rate, parent_rate) &&
 820             pll->params->calc_rate(hw, &cfg, rate, parent_rate)) {
 821                 pr_err("%s: Failed to set %s rate %lu\n", __func__,
 822                        clk_hw_get_name(hw), rate);
 823                 WARN_ON(1);
 824                 return -EINVAL;
 825         }
 826         if (pll->lock)
 827                 spin_lock_irqsave(pll->lock, flags);
 828
 829         _get_pll_mnp(pll, &old_cfg);
 830         if (pll->params->flags & TEGRA_PLL_VCO_OUT)
 831                 cfg.p = old_cfg.p;
 832
 833         if (old_cfg.m != cfg.m || old_cfg.n != cfg.n || old_cfg.p != cfg.p ||
 834                 old_cfg.sdm_data != cfg.sdm_data)
 835                 ret = _program_pll(hw, &cfg, rate);
 836
 837         if (pll->lock)
 838                 spin_unlock_irqrestore(pll->lock, flags);
 839
 840         return ret;
 841 }
 842
 843 static long clk_pll_round_rate(struct clk_hw *hw, unsigned long rate,
 844                         unsigned long *prate)
 845 {
 846         struct tegra_clk_pll *pll = to_clk_pll(hw);
 847         struct tegra_clk_pll_freq_table cfg;
 848
 849         if (pll->params->flags & TEGRA_PLL_FIXED) {
 850                 /* PLLM/MB are used for memory; we do not change rate */
 851                 if (pll->params->flags & (TEGRA_PLLM | TEGRA_PLLMB))
 852                         return clk_hw_get_rate(hw);
 853                 return pll->params->fixed_rate;
 854         }
 855
 856         if (_get_table_rate(hw, &cfg, rate, *prate) &&
 857             pll->params->calc_rate(hw, &cfg, rate, *prate))
 858                 return -EINVAL;
 859
 860         return cfg.output_rate;
 861 }
 862
 863 static unsigned long clk_pll_recalc_rate(struct clk_hw *hw,
 864                                          unsigned long parent_rate)
 865 {
 866         struct tegra_clk_pll *pll = to_clk_pll(hw);
 867         struct tegra_clk_pll_freq_table cfg;
 868         u32 val;
 869         u64 rate = parent_rate;
 870         int pdiv;
 871
 872         val = pll_readl_base(pll);
 873
 874         if ((pll->params->flags & TEGRA_PLL_BYPASS) && (val & PLL_BASE_BYPASS))
 875                 return parent_rate;
 876
 877         if ((pll->params->flags & TEGRA_PLL_FIXED) &&
 878             !(pll->params->flags & (TEGRA_PLLM | TEGRA_PLLMB)) &&
 879                         !(val & PLL_BASE_OVERRIDE)) {
 880                 struct tegra_clk_pll_freq_table sel;
 881                 if (_get_table_rate(hw, &sel, pll->params->fixed_rate,
 882                                         parent_rate)) {
 883                         pr_err("Clock %s has unknown fixed frequency\n",
 884                                clk_hw_get_name(hw));
 885                         BUG();
 886                 }
 887                 return pll->params->fixed_rate;
 888         }
 889
 890         _get_pll_mnp(pll, &cfg);
 891
 892         if (pll->params->flags & TEGRA_PLL_VCO_OUT) {
 893                 pdiv = 1;
 894         } else {
 895                 pdiv = _hw_to_p_div(hw, cfg.p);
 896                 if (pdiv < 0) {
 897                         WARN(1, "Clock %s has invalid pdiv value : 0x%x\n",
 898                              clk_hw_get_name(hw), cfg.p);
 899                         pdiv = 1;
 900                 }
 901         }
 902
 903         if (pll->params->set_gain)
 904                 pll->params->set_gain(&cfg);
 905
 906         cfg.m *= pdiv;
 907
 908         rate *= cfg.n;
 909         do_div(rate, cfg.m);
 910
 911         return rate;
 912 }
 913
 914 static int clk_plle_training(struct tegra_clk_pll *pll)
 915 {
 916         u32 val;
 917         unsigned long timeout;
 918
 919         if (!pll->pmc)
 920                 return -ENOSYS;
 921
 922         /*
 923          * PLLE is already disabled, and setup cleared;
 924          * create falling edge on PLLE IDDQ input.
 925          */
 926         val = readl(pll->pmc + PMC_SATA_PWRGT);
 927         val |= PMC_SATA_PWRGT_PLLE_IDDQ_VALUE;
 928         writel(val, pll->pmc + PMC_SATA_PWRGT);
 929
 930         val = readl(pll->pmc + PMC_SATA_PWRGT);
 931         val |= PMC_SATA_PWRGT_PLLE_IDDQ_SWCTL;
 932         writel(val, pll->pmc + PMC_SATA_PWRGT);
 933
 934         val = readl(pll->pmc + PMC_SATA_PWRGT);
 935         val &= ~PMC_SATA_PWRGT_PLLE_IDDQ_VALUE;
 936         writel(val, pll->pmc + PMC_SATA_PWRGT);
 937
 938         val = pll_readl_misc(pll);
 939
 940         timeout = jiffies + msecs_to_jiffies(100);
 941         while (1) {
 942                 val = pll_readl_misc(pll);
 943                 if (val & PLLE_MISC_READY)
 944                         break;
 945                 if (time_after(jiffies, timeout)) {
 946                         pr_err("%s: timeout waiting for PLLE\n", __func__);
 947                         return -EBUSY;
 948                 }
 949                 udelay(300);
 950         }
 951
 952         return 0;
 953 }
 954
 955 static int clk_plle_enable(struct clk_hw *hw)
 956 {
 957         struct tegra_clk_pll *pll = to_clk_pll(hw);
 958         struct tegra_clk_pll_freq_table sel;
 959         unsigned long input_rate;
 960         u32 val;
 961         int err;
 962
 963         if (clk_pll_is_enabled(hw))
 964                 return 0;
 965
 966         input_rate = clk_hw_get_rate(clk_hw_get_parent(hw));
 967
 968         if (_get_table_rate(hw, &sel, pll->params->fixed_rate, input_rate))
 969                 return -EINVAL;
 970
 971         clk_pll_disable(hw);
 972
 973         val = pll_readl_misc(pll);
 974         val &= ~(PLLE_MISC_LOCK_ENABLE | PLLE_MISC_SETUP_MASK);
 975         pll_writel_misc(val, pll);
 976
 977         val = pll_readl_misc(pll);
 978         if (!(val & PLLE_MISC_READY)) {
 979                 err = clk_plle_training(pll);
 980                 if (err)
 981                         return err;
 982         }
 983
 984         if (pll->params->flags & TEGRA_PLLE_CONFIGURE) {
 985                 /* configure dividers */
 986                 val = pll_readl_base(pll);
 987                 val &= ~(divp_mask_shifted(pll) | divn_mask_shifted(pll) |
 988                          divm_mask_shifted(pll));
 989                 val &= ~(PLLE_BASE_DIVCML_MASK << PLLE_BASE_DIVCML_SHIFT);
 990                 val |= sel.m << divm_shift(pll);
 991                 val |= sel.n << divn_shift(pll);
 992                 val |= sel.p << divp_shift(pll);
 993                 val |= sel.cpcon << PLLE_BASE_DIVCML_SHIFT;
 994                 pll_writel_base(val, pll);
 995         }
 996
 997         val = pll_readl_misc(pll);
 998         val |= PLLE_MISC_SETUP_VALUE;
 999         val |= PLLE_MISC_LOCK_ENABLE;
1000         pll_writel_misc(val, pll);
1001
1002         val = readl(pll->clk_base + PLLE_SS_CTRL);
1003         val &= ~PLLE_SS_COEFFICIENTS_MASK;
1004         val |= PLLE_SS_DISABLE;
1005         writel(val, pll->clk_base + PLLE_SS_CTRL);
1006
1007         val = pll_readl_base(pll);
1008         val |= (PLL_BASE_BYPASS | PLL_BASE_ENABLE);
1009         pll_writel_base(val, pll);
1010
1011         clk_pll_wait_for_lock(pll);
1012
1013         return 0;
1014 }
1015
1016 static unsigned long clk_plle_recalc_rate(struct clk_hw *hw,
1017                                          unsigned long parent_rate)
1018 {
1019         struct tegra_clk_pll *pll = to_clk_pll(hw);
1020         u32 val = pll_readl_base(pll);
1021         u32 divn = 0, divm = 0, divp = 0;
1022         u64 rate = parent_rate;
1023
1024         divp = (val >> pll->params->div_nmp->divp_shift) & (divp_mask(pll));
1025         divn = (val >> pll->params->div_nmp->divn_shift) & (divn_mask(pll));
1026         divm = (val >> pll->params->div_nmp->divm_shift) & (divm_mask(pll));
1027         divm *= divp;
1028
1029         rate *= divn;
1030         do_div(rate, divm);
1031         return rate;
1032 }
1033
1034 static void tegra_clk_pll_restore_context(struct clk_hw *hw)
1035 {
1036         struct tegra_clk_pll *pll = to_clk_pll(hw);
1037         struct clk_hw *parent = clk_hw_get_parent(hw);
1038         unsigned long parent_rate = clk_hw_get_rate(parent);
1039         unsigned long rate = clk_hw_get_rate(hw);
1040
1041         if (clk_pll_is_enabled(hw))
1042                 return;
1043
1044         if (pll->params->set_defaults)
1045                 pll->params->set_defaults(pll);
1046
1047         clk_pll_set_rate(hw, rate, parent_rate);
1048
1049         if (!__clk_get_enable_count(hw->clk))
1050                 clk_pll_disable(hw);
1051         else
1052                 clk_pll_enable(hw);
1053 }
1054
1055 const struct clk_ops tegra_clk_pll_ops = {
1056         .is_enabled = clk_pll_is_enabled,
1057         .enable = clk_pll_enable,
1058         .disable = clk_pll_disable,
1059         .recalc_rate = clk_pll_recalc_rate,
1060         .round_rate = clk_pll_round_rate,
1061         .set_rate = clk_pll_set_rate,
1062         .restore_context = tegra_clk_pll_restore_context,
1063 };
1064
1065 const struct clk_ops tegra_clk_plle_ops = {
1066         .recalc_rate = clk_plle_recalc_rate,
1067         .is_enabled = clk_pll_is_enabled,
1068         .disable = clk_pll_disable,
1069         .enable = clk_plle_enable,
1070 };
1071
1072 /*
1073  * Structure defining the fields for USB UTMI clocks Parameters.
1074  */
1075 struct utmi_clk_param {
1076         /* Oscillator Frequency in Hz */
1077         u32 osc_frequency;
1078         /* UTMIP PLL Enable Delay Count  */
1079         u8 enable_delay_count;
1080         /* UTMIP PLL Stable count */
1081         u8 stable_count;
1082         /*  UTMIP PLL Active delay count */
1083         u8 active_delay_count;
1084         /* UTMIP PLL Xtal frequency count */
1085         u8 xtal_freq_count;
1086 };
1087
1088 static const struct utmi_clk_param utmi_parameters[] = {
1089         {
1090                 .osc_frequency = 13000000, .enable_delay_count = 0x02,
1091                 .stable_count = 0x33, .active_delay_count = 0x05,
1092                 .xtal_freq_count = 0x7f
1093         }, {
1094                 .osc_frequency = 19200000, .enable_delay_count = 0x03,
1095                 .stable_count = 0x4b, .active_delay_count = 0x06,
1096                 .xtal_freq_count = 0xbb
1097         }, {
1098                 .osc_frequency = 12000000, .enable_delay_count = 0x02,
1099                 .stable_count = 0x2f, .active_delay_count = 0x04,
1100                 .xtal_freq_count = 0x76
1101         }, {
1102                 .osc_frequency = 26000000, .enable_delay_count = 0x04,
1103                 .stable_count = 0x66, .active_delay_count = 0x09,
1104                 .xtal_freq_count = 0xfe
1105         }, {
1106                 .osc_frequency = 16800000, .enable_delay_count = 0x03,
1107                 .stable_count = 0x41, .active_delay_count = 0x0a,
1108                 .xtal_freq_count = 0xa4
1109         }, {
1110                 .osc_frequency = 38400000, .enable_delay_count = 0x0,
1111                 .stable_count = 0x0, .active_delay_count = 0x6,
1112                 .xtal_freq_count = 0x80
1113         },
1114 };
1115
1116 static int clk_pllu_enable(struct clk_hw *hw)
1117 {
1118         struct tegra_clk_pll *pll = to_clk_pll(hw);
1119         struct clk_hw *pll_ref = clk_hw_get_parent(hw);
1120         struct clk_hw *osc = clk_hw_get_parent(pll_ref);
1121         const struct utmi_clk_param *params = NULL;
1122         unsigned long flags = 0, input_rate;
1123         unsigned int i;
1124         int ret = 0;
1125         u32 value;
1126
1127         if (!osc) {
1128                 pr_err("%s: failed to get OSC clock\n", __func__);
1129                 return -EINVAL;
1130         }
1131
1132         input_rate = clk_hw_get_rate(osc);
1133
1134         if (pll->lock)
1135                 spin_lock_irqsave(pll->lock, flags);
1136
1137         if (!clk_pll_is_enabled(hw))
1138                 _clk_pll_enable(hw);
1139
1140         ret = clk_pll_wait_for_lock(pll);
1141         if (ret < 0)
1142                 goto out;
1143
1144         for (i = 0; i < ARRAY_SIZE(utmi_parameters); i++) {
1145                 if (input_rate == utmi_parameters[i].osc_frequency) {
1146                         params = &utmi_parameters[i];
1147                         break;
1148                 }
1149         }
1150
1151         if (!params) {
1152                 pr_err("%s: unexpected input rate %lu Hz\n", __func__,
1153                        input_rate);
1154                 ret = -EINVAL;
1155                 goto out;
1156         }
1157
1158         value = pll_readl_base(pll);
1159         value &= ~PLLU_BASE_OVERRIDE;
1160         pll_writel_base(value, pll);
1161
1162         value = readl_relaxed(pll->clk_base + UTMIP_PLL_CFG2);
1163         /* Program UTMIP PLL stable and active counts */
1164         value &= ~UTMIP_PLL_CFG2_STABLE_COUNT(~0);
1165         value |= UTMIP_PLL_CFG2_STABLE_COUNT(params->stable_count);
1166         value &= ~UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(~0);
1167         value |= UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(params->active_delay_count);
1168         /* Remove power downs from UTMIP PLL control bits */
1169         value &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN;
1170         value &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN;
1171         value &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN;
1172         writel_relaxed(value, pll->clk_base + UTMIP_PLL_CFG2);
1173
1174         value = readl_relaxed(pll->clk_base + UTMIP_PLL_CFG1);
1175         /* Program UTMIP PLL delay and oscillator frequency counts */
1176         value &= ~UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(~0);
1177         value |= UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(params->enable_delay_count);
1178         value &= ~UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(~0);
1179         value |= UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(params->xtal_freq_count);
1180         /* Remove power downs from UTMIP PLL control bits */
1181         value &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN;
1182         value &= ~UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN;
1183         value &= ~UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN;
1184         writel_relaxed(value, pll->clk_base + UTMIP_PLL_CFG1);
1185
1186 out:
1187         if (pll->lock)
1188                 spin_unlock_irqrestore(pll->lock, flags);
1189
1190         return ret;
1191 }
1192
1193 static const struct clk_ops tegra_clk_pllu_ops = {
1194         .is_enabled = clk_pll_is_enabled,
1195         .enable = clk_pllu_enable,
1196         .disable = clk_pll_disable,
1197         .recalc_rate = clk_pll_recalc_rate,
1198         .round_rate = clk_pll_round_rate,
1199         .set_rate = clk_pll_set_rate,
1200 };
1201
1202 static int _pll_fixed_mdiv(struct tegra_clk_pll_params *pll_params,
1203                            unsigned long parent_rate)
1204 {
1205         u16 mdiv = parent_rate / pll_params->cf_min;
1206
1207         if (pll_params->flags & TEGRA_MDIV_NEW)
1208                 return (!pll_params->mdiv_default ? mdiv :
1209                         min(mdiv, pll_params->mdiv_default));
1210
1211         if (pll_params->mdiv_default)
1212                 return pll_params->mdiv_default;
1213
1214         if (parent_rate > pll_params->cf_max)
1215                 return 2;
1216         else
1217                 return 1;
1218 }
1219
1220 static int _calc_dynamic_ramp_rate(struct clk_hw *hw,
1221                                 struct tegra_clk_pll_freq_table *cfg,
1222                                 unsigned long rate, unsigned long parent_rate)
1223 {
1224         struct tegra_clk_pll *pll = to_clk_pll(hw);
1225         unsigned int p;
1226         int p_div;
1227
1228         if (!rate)
1229                 return -EINVAL;
1230
1231         p = DIV_ROUND_UP(pll->params->vco_min, rate);
1232         cfg->m = _pll_fixed_mdiv(pll->params, parent_rate);
1233         cfg->output_rate = rate * p;
1234         cfg->n = cfg->output_rate * cfg->m / parent_rate;
1235         cfg->input_rate = parent_rate;
1236
1237         p_div = _p_div_to_hw(hw, p);
1238         if (p_div < 0)
1239                 return p_div;
1240
1241         cfg->p = p_div;
1242
1243         if (cfg->n > divn_max(pll) || cfg->output_rate > pll->params->vco_max)
1244                 return -EINVAL;
1245
1246         return 0;
1247 }
1248
1249 #if defined(CONFIG_ARCH_TEGRA_114_SOC) || \
1250         defined(CONFIG_ARCH_TEGRA_124_SOC) || \
1251         defined(CONFIG_ARCH_TEGRA_132_SOC) || \
1252         defined(CONFIG_ARCH_TEGRA_210_SOC)
1253
1254 u16 tegra_pll_get_fixed_mdiv(struct clk_hw *hw, unsigned long input_rate)
1255 {
1256         struct tegra_clk_pll *pll = to_clk_pll(hw);
1257
1258         return (u16)_pll_fixed_mdiv(pll->params, input_rate);
1259 }
1260
1261 static unsigned long _clip_vco_min(unsigned long vco_min,
1262                                    unsigned long parent_rate)
1263 {
1264         return DIV_ROUND_UP(vco_min, parent_rate) * parent_rate;
1265 }
1266
1267 static int _setup_dynamic_ramp(struct tegra_clk_pll_params *pll_params,
1268                                void __iomem *clk_base,
1269                                unsigned long parent_rate)
1270 {
1271         u32 val;
1272         u32 step_a, step_b;
1273
1274         switch (parent_rate) {
1275         case 12000000:
1276         case 13000000:
1277         case 26000000:
1278                 step_a = 0x2B;
1279                 step_b = 0x0B;
1280                 break;
1281         case 16800000:
1282                 step_a = 0x1A;
1283                 step_b = 0x09;
1284                 break;
1285         case 19200000:
1286                 step_a = 0x12;
1287                 step_b = 0x08;
1288                 break;
1289         default:
1290                 pr_err("%s: Unexpected reference rate %lu\n",
1291                         __func__, parent_rate);
1292                 WARN_ON(1);
1293                 return -EINVAL;
1294         }
1295
1296         val = step_a << pll_params->stepa_shift;
1297         val |= step_b << pll_params->stepb_shift;
1298         writel_relaxed(val, clk_base + pll_params->dyn_ramp_reg);
1299
1300         return 0;
1301 }
1302
1303 static int _pll_ramp_calc_pll(struct clk_hw *hw,
1304                               struct tegra_clk_pll_freq_table *cfg,
1305                               unsigned long rate, unsigned long parent_rate)
1306 {
1307         struct tegra_clk_pll *pll = to_clk_pll(hw);
1308         int err = 0;
1309
1310         err = _get_table_rate(hw, cfg, rate, parent_rate);
1311         if (err < 0)
1312                 err = _calc_dynamic_ramp_rate(hw, cfg, rate, parent_rate);
1313         else {
1314                 if (cfg->m != _pll_fixed_mdiv(pll->params, parent_rate)) {
1315                         WARN_ON(1);
1316                         err = -EINVAL;
1317                         goto out;
1318                 }
1319         }
1320
1321         if (cfg->p >  pll->params->max_p)
1322                 err = -EINVAL;
1323
1324 out:
1325         return err;
1326 }
1327
1328 static int clk_pllxc_set_rate(struct clk_hw *hw, unsigned long rate,
1329                                 unsigned long parent_rate)
1330 {
1331         struct tegra_clk_pll *pll = to_clk_pll(hw);
1332         struct tegra_clk_pll_freq_table cfg, old_cfg;
1333         unsigned long flags = 0;
1334         int ret;
1335
1336         ret = _pll_ramp_calc_pll(hw, &cfg, rate, parent_rate);
1337         if (ret < 0)
1338                 return ret;
1339
1340         if (pll->lock)
1341                 spin_lock_irqsave(pll->lock, flags);
1342
1343         _get_pll_mnp(pll, &old_cfg);
1344         if (pll->params->flags & TEGRA_PLL_VCO_OUT)
1345                 cfg.p = old_cfg.p;
1346
1347         if (old_cfg.m != cfg.m || old_cfg.n != cfg.n || old_cfg.p != cfg.p)
1348                 ret = _program_pll(hw, &cfg, rate);
1349
1350         if (pll->lock)
1351                 spin_unlock_irqrestore(pll->lock, flags);
1352
1353         return ret;
1354 }
1355
1356 static long clk_pll_ramp_round_rate(struct clk_hw *hw, unsigned long rate,
1357                                 unsigned long *prate)
1358 {
1359         struct tegra_clk_pll *pll = to_clk_pll(hw);
1360         struct tegra_clk_pll_freq_table cfg;
1361         int ret, p_div;
1362         u64 output_rate = *prate;
1363
1364         ret = _pll_ramp_calc_pll(hw, &cfg, rate, *prate);
1365         if (ret < 0)
1366                 return ret;
1367
1368         p_div = _hw_to_p_div(hw, cfg.p);
1369         if (p_div < 0)
1370                 return p_div;
1371
1372         if (pll->params->set_gain)
1373                 pll->params->set_gain(&cfg);
1374
1375         output_rate *= cfg.n;
1376         do_div(output_rate, cfg.m * p_div);
1377
1378         return output_rate;
1379 }
1380
1381 static void _pllcx_strobe(struct tegra_clk_pll *pll)
1382 {
1383         u32 val;
1384
1385         val = pll_readl_misc(pll);
1386         val |= PLLCX_MISC_STROBE;
1387         pll_writel_misc(val, pll);
1388         udelay(2);
1389
1390         val &= ~PLLCX_MISC_STROBE;
1391         pll_writel_misc(val, pll);
1392 }
1393
1394 static int clk_pllc_enable(struct clk_hw *hw)
1395 {
1396         struct tegra_clk_pll *pll = to_clk_pll(hw);
1397         u32 val;
1398         int ret;
1399         unsigned long flags = 0;
1400
1401         if (clk_pll_is_enabled(hw))
1402                 return 0;
1403
1404         if (pll->lock)
1405                 spin_lock_irqsave(pll->lock, flags);
1406
1407         _clk_pll_enable(hw);
1408         udelay(2);
1409
1410         val = pll_readl_misc(pll);
1411         val &= ~PLLCX_MISC_RESET;
1412         pll_writel_misc(val, pll);
1413         udelay(2);
1414
1415         _pllcx_strobe(pll);
1416
1417         ret = clk_pll_wait_for_lock(pll);
1418
1419         if (pll->lock)
1420                 spin_unlock_irqrestore(pll->lock, flags);
1421
1422         return ret;
1423 }
1424
1425 static void _clk_pllc_disable(struct clk_hw *hw)
1426 {
1427         struct tegra_clk_pll *pll = to_clk_pll(hw);
1428         u32 val;
1429
1430         _clk_pll_disable(hw);
1431
1432         val = pll_readl_misc(pll);
1433         val |= PLLCX_MISC_RESET;
1434         pll_writel_misc(val, pll);
1435         udelay(2);
1436 }
1437
1438 static void clk_pllc_disable(struct clk_hw *hw)
1439 {
1440         struct tegra_clk_pll *pll = to_clk_pll(hw);
1441         unsigned long flags = 0;
1442
1443         if (pll->lock)
1444                 spin_lock_irqsave(pll->lock, flags);
1445
1446         _clk_pllc_disable(hw);
1447
1448         if (pll->lock)
1449                 spin_unlock_irqrestore(pll->lock, flags);
1450 }
1451
1452 static int _pllcx_update_dynamic_coef(struct tegra_clk_pll *pll,
1453                                         unsigned long input_rate, u32 n)
1454 {
1455         u32 val, n_threshold;
1456
1457         switch (input_rate) {
1458         case 12000000:
1459                 n_threshold = 70;
1460                 break;
1461         case 13000000:
1462         case 26000000:
1463                 n_threshold = 71;
1464                 break;
1465         case 16800000:
1466                 n_threshold = 55;
1467                 break;
1468         case 19200000:
1469                 n_threshold = 48;
1470                 break;
1471         default:
1472                 pr_err("%s: Unexpected reference rate %lu\n",
1473                         __func__, input_rate);
1474                 return -EINVAL;
1475         }
1476
1477         val = pll_readl_misc(pll);
1478         val &= ~(PLLCX_MISC_SDM_DIV_MASK | PLLCX_MISC_FILT_DIV_MASK);
1479         val |= n <= n_threshold ?
1480                 PLLCX_MISC_DIV_LOW_RANGE : PLLCX_MISC_DIV_HIGH_RANGE;
1481         pll_writel_misc(val, pll);
1482
1483         return 0;
1484 }
1485
1486 static int clk_pllc_set_rate(struct clk_hw *hw, unsigned long rate,
1487                                 unsigned long parent_rate)
1488 {
1489         struct tegra_clk_pll_freq_table cfg, old_cfg;
1490         struct tegra_clk_pll *pll = to_clk_pll(hw);
1491         unsigned long flags = 0;
1492         int state, ret = 0;
1493
1494         if (pll->lock)
1495                 spin_lock_irqsave(pll->lock, flags);
1496
1497         ret = _pll_ramp_calc_pll(hw, &cfg, rate, parent_rate);
1498         if (ret < 0)
1499                 goto out;
1500
1501         _get_pll_mnp(pll, &old_cfg);
1502
1503         if (cfg.m != old_cfg.m) {
1504                 WARN_ON(1);
1505                 goto out;
1506         }
1507
1508         if (old_cfg.n == cfg.n && old_cfg.p == cfg.p)
1509                 goto out;
1510
1511         state = clk_pll_is_enabled(hw);
1512         if (state)
1513                 _clk_pllc_disable(hw);
1514
1515         ret = _pllcx_update_dynamic_coef(pll, parent_rate, cfg.n);
1516         if (ret < 0)
1517                 goto out;
1518
1519         _update_pll_mnp(pll, &cfg);
1520
1521         if (state)
1522                 ret = clk_pllc_enable(hw);
1523
1524 out:
1525         if (pll->lock)
1526                 spin_unlock_irqrestore(pll->lock, flags);
1527
1528         return ret;
1529 }
1530
1531 static long _pllre_calc_rate(struct tegra_clk_pll *pll,
1532                              struct tegra_clk_pll_freq_table *cfg,
1533                              unsigned long rate, unsigned long parent_rate)
1534 {
1535         u16 m, n;
1536         u64 output_rate = parent_rate;
1537
1538         m = _pll_fixed_mdiv(pll->params, parent_rate);
1539         n = rate * m / parent_rate;
1540
1541         output_rate *= n;
1542         do_div(output_rate, m);
1543
1544         if (cfg) {
1545                 cfg->m = m;
1546                 cfg->n = n;
1547         }
1548
1549         return output_rate;
1550 }
1551
1552 static int clk_pllre_set_rate(struct clk_hw *hw, unsigned long rate,
1553                                 unsigned long parent_rate)
1554 {
1555         struct tegra_clk_pll_freq_table cfg, old_cfg;
1556         struct tegra_clk_pll *pll = to_clk_pll(hw);
1557         unsigned long flags = 0;
1558         int state, ret = 0;
1559
1560         if (pll->lock)
1561                 spin_lock_irqsave(pll->lock, flags);
1562
1563         _pllre_calc_rate(pll, &cfg, rate, parent_rate);
1564         _get_pll_mnp(pll, &old_cfg);
1565         cfg.p = old_cfg.p;
1566
1567         if (cfg.m != old_cfg.m || cfg.n != old_cfg.n) {
1568                 state = clk_pll_is_enabled(hw);
1569                 if (state)
1570                         _clk_pll_disable(hw);
1571
1572                 _update_pll_mnp(pll, &cfg);
1573
1574                 if (state) {
1575                         _clk_pll_enable(hw);
1576                         ret = clk_pll_wait_for_lock(pll);
1577                 }
1578         }
1579
1580         if (pll->lock)
1581                 spin_unlock_irqrestore(pll->lock, flags);
1582
1583         return ret;
1584 }
1585
1586 static unsigned long clk_pllre_recalc_rate(struct clk_hw *hw,
1587                                          unsigned long parent_rate)
1588 {
1589         struct tegra_clk_pll_freq_table cfg;
1590         struct tegra_clk_pll *pll = to_clk_pll(hw);
1591         u64 rate = parent_rate;
1592
1593         _get_pll_mnp(pll, &cfg);
1594
1595         rate *= cfg.n;
1596         do_div(rate, cfg.m);
1597
1598         return rate;
1599 }
1600
1601 static long clk_pllre_round_rate(struct clk_hw *hw, unsigned long rate,
1602                                  unsigned long *prate)
1603 {
1604         struct tegra_clk_pll *pll = to_clk_pll(hw);
1605
1606         return _pllre_calc_rate(pll, NULL, rate, *prate);
1607 }
1608
1609 static int clk_plle_tegra114_enable(struct clk_hw *hw)
1610 {
1611         struct tegra_clk_pll *pll = to_clk_pll(hw);
1612         struct tegra_clk_pll_freq_table sel;
1613         u32 val;
1614         int ret;
1615         unsigned long flags = 0;
1616         unsigned long input_rate;
1617
1618         input_rate = clk_hw_get_rate(clk_hw_get_parent(hw));
1619
1620         if (_get_table_rate(hw, &sel, pll->params->fixed_rate, input_rate))
1621                 return -EINVAL;
1622
1623         if (pll->lock)
1624                 spin_lock_irqsave(pll->lock, flags);
1625
1626         val = pll_readl_base(pll);
1627         val &= ~BIT(29); /* Disable lock override */
1628         pll_writel_base(val, pll);
1629
1630         val = pll_readl(pll->params->aux_reg, pll);
1631         val |= PLLE_AUX_ENABLE_SWCTL;
1632         val &= ~PLLE_AUX_SEQ_ENABLE;
1633         pll_writel(val, pll->params->aux_reg, pll);
1634         udelay(1);
1635
1636         val = pll_readl_misc(pll);
1637         val |= PLLE_MISC_LOCK_ENABLE;
1638         val |= PLLE_MISC_IDDQ_SW_CTRL;
1639         val &= ~PLLE_MISC_IDDQ_SW_VALUE;
1640         val |= PLLE_MISC_PLLE_PTS;
1641         val &= ~(PLLE_MISC_VREG_BG_CTRL_MASK | PLLE_MISC_VREG_CTRL_MASK);
1642         pll_writel_misc(val, pll);
1643         udelay(5);
1644
1645         val = pll_readl(PLLE_SS_CTRL, pll);
1646         val |= PLLE_SS_DISABLE;
1647         pll_writel(val, PLLE_SS_CTRL, pll);
1648
1649         val = pll_readl_base(pll);
1650         val &= ~(divp_mask_shifted(pll) | divn_mask_shifted(pll) |
1651                  divm_mask_shifted(pll));
1652         val &= ~(PLLE_BASE_DIVCML_MASK << PLLE_BASE_DIVCML_SHIFT);
1653         val |= sel.m << divm_shift(pll);
1654         val |= sel.n << divn_shift(pll);
1655         val |= sel.cpcon << PLLE_BASE_DIVCML_SHIFT;
1656         pll_writel_base(val, pll);
1657         udelay(1);
1658
1659         _clk_pll_enable(hw);
1660         ret = clk_pll_wait_for_lock(pll);
1661
1662         if (ret < 0)
1663                 goto out;
1664
1665         val = pll_readl(PLLE_SS_CTRL, pll);
1666         val &= ~(PLLE_SS_CNTL_CENTER | PLLE_SS_CNTL_INVERT);
1667         val &= ~PLLE_SS_COEFFICIENTS_MASK;
1668         val |= PLLE_SS_COEFFICIENTS_VAL_TEGRA114;
1669         pll_writel(val, PLLE_SS_CTRL, pll);
1670         val &= ~(PLLE_SS_CNTL_SSC_BYP | PLLE_SS_CNTL_BYPASS_SS);
1671         pll_writel(val, PLLE_SS_CTRL, pll);
1672         udelay(1);
1673         val &= ~PLLE_SS_CNTL_INTERP_RESET;
1674         pll_writel(val, PLLE_SS_CTRL, pll);
1675         udelay(1);
1676
1677         /* Enable HW control of XUSB brick PLL */
1678         val = pll_readl_misc(pll);
1679         val &= ~PLLE_MISC_IDDQ_SW_CTRL;
1680         pll_writel_misc(val, pll);
1681
1682         val = pll_readl(pll->params->aux_reg, pll);
1683         val |= (PLLE_AUX_USE_LOCKDET | PLLE_AUX_SEQ_START_STATE);
1684         val &= ~(PLLE_AUX_ENABLE_SWCTL | PLLE_AUX_SS_SWCTL);
1685         pll_writel(val, pll->params->aux_reg, pll);
1686         udelay(1);
1687         val |= PLLE_AUX_SEQ_ENABLE;
1688         pll_writel(val, pll->params->aux_reg, pll);
1689
1690         val = pll_readl(XUSBIO_PLL_CFG0, pll);
1691         val |= (XUSBIO_PLL_CFG0_PADPLL_USE_LOCKDET |
1692                 XUSBIO_PLL_CFG0_SEQ_START_STATE);
1693         val &= ~(XUSBIO_PLL_CFG0_CLK_ENABLE_SWCTL |
1694                  XUSBIO_PLL_CFG0_PADPLL_RESET_SWCTL);
1695         pll_writel(val, XUSBIO_PLL_CFG0, pll);
1696         udelay(1);
1697         val |= XUSBIO_PLL_CFG0_SEQ_ENABLE;
1698         pll_writel(val, XUSBIO_PLL_CFG0, pll);
1699
1700         /* Enable HW control of SATA PLL */
1701         val = pll_readl(SATA_PLL_CFG0, pll);
1702         val &= ~SATA_PLL_CFG0_PADPLL_RESET_SWCTL;
1703         val |= SATA_PLL_CFG0_PADPLL_USE_LOCKDET;
1704         val |= SATA_PLL_CFG0_SEQ_START_STATE;
1705         pll_writel(val, SATA_PLL_CFG0, pll);
1706
1707         udelay(1);
1708
1709         val = pll_readl(SATA_PLL_CFG0, pll);
1710         val |= SATA_PLL_CFG0_SEQ_ENABLE;
1711         pll_writel(val, SATA_PLL_CFG0, pll);
1712
1713 out:
1714         if (pll->lock)
1715                 spin_unlock_irqrestore(pll->lock, flags);
1716
1717         return ret;
1718 }
1719
1720 static void clk_plle_tegra114_disable(struct clk_hw *hw)
1721 {
1722         struct tegra_clk_pll *pll = to_clk_pll(hw);
1723         unsigned long flags = 0;
1724         u32 val;
1725
1726         if (pll->lock)
1727                 spin_lock_irqsave(pll->lock, flags);
1728
1729         _clk_pll_disable(hw);
1730
1731         val = pll_readl_misc(pll);
1732         val |= PLLE_MISC_IDDQ_SW_CTRL | PLLE_MISC_IDDQ_SW_VALUE;
1733         pll_writel_misc(val, pll);
1734         udelay(1);
1735
1736         if (pll->lock)
1737                 spin_unlock_irqrestore(pll->lock, flags);
1738 }
1739
1740 static int clk_pllu_tegra114_enable(struct clk_hw *hw)
1741 {
1742         struct tegra_clk_pll *pll = to_clk_pll(hw);
1743         const struct utmi_clk_param *params = NULL;
1744         struct clk *osc = __clk_lookup("osc");
1745         unsigned long flags = 0, input_rate;
1746         unsigned int i;
1747         int ret = 0;
1748         u32 value;
1749
1750         if (!osc) {
1751                 pr_err("%s: failed to get OSC clock\n", __func__);
1752                 return -EINVAL;
1753         }
1754
1755         input_rate = clk_hw_get_rate(__clk_get_hw(osc));
1756
1757         if (pll->lock)
1758                 spin_lock_irqsave(pll->lock, flags);
1759
1760         if (!clk_pll_is_enabled(hw))
1761                 _clk_pll_enable(hw);
1762
1763         ret = clk_pll_wait_for_lock(pll);
1764         if (ret < 0)
1765                 goto out;
1766
1767         for (i = 0; i < ARRAY_SIZE(utmi_parameters); i++) {
1768                 if (input_rate == utmi_parameters[i].osc_frequency) {
1769                         params = &utmi_parameters[i];
1770                         break;
1771                 }
1772         }
1773
1774         if (!params) {
1775                 pr_err("%s: unexpected input rate %lu Hz\n", __func__,
1776                        input_rate);
1777                 ret = -EINVAL;
1778                 goto out;
1779         }
1780
1781         value = pll_readl_base(pll);
1782         value &= ~PLLU_BASE_OVERRIDE;
1783         pll_writel_base(value, pll);
1784
1785         value = readl_relaxed(pll->clk_base + UTMIP_PLL_CFG2);
1786         /* Program UTMIP PLL stable and active counts */
1787         value &= ~UTMIP_PLL_CFG2_STABLE_COUNT(~0);
1788         value |= UTMIP_PLL_CFG2_STABLE_COUNT(params->stable_count);
1789         value &= ~UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(~0);
1790         value |= UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(params->active_delay_count);
1791         /* Remove power downs from UTMIP PLL control bits */
1792         value &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN;
1793         value &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN;
1794         value &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN;
1795         writel_relaxed(value, pll->clk_base + UTMIP_PLL_CFG2);
1796
1797         value = readl_relaxed(pll->clk_base + UTMIP_PLL_CFG1);
1798         /* Program UTMIP PLL delay and oscillator frequency counts */
1799         value &= ~UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(~0);
1800         value |= UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(params->enable_delay_count);
1801         value &= ~UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(~0);
1802         value |= UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(params->xtal_freq_count);
1803         /* Remove power downs from UTMIP PLL control bits */
1804         value &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN;
1805         value &= ~UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN;
1806         value &= ~UTMIP_PLL_CFG1_FORCE_PLLU_POWERUP;
1807         value &= ~UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN;
1808         writel_relaxed(value, pll->clk_base + UTMIP_PLL_CFG1);
1809
1810         /* Setup HW control of UTMIPLL */
1811         value = readl_relaxed(pll->clk_base + UTMIPLL_HW_PWRDN_CFG0);
1812         value |= UTMIPLL_HW_PWRDN_CFG0_USE_LOCKDET;
1813         value &= ~UTMIPLL_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL;
1814         value |= UTMIPLL_HW_PWRDN_CFG0_SEQ_START_STATE;
1815         writel_relaxed(value, pll->clk_base + UTMIPLL_HW_PWRDN_CFG0);
1816
1817         value = readl_relaxed(pll->clk_base + UTMIP_PLL_CFG1);
1818         value &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP;
1819         value &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN;
1820         writel_relaxed(value, pll->clk_base + UTMIP_PLL_CFG1);
1821
1822         udelay(1);
1823
1824         /*
1825          * Setup SW override of UTMIPLL assuming USB2.0 ports are assigned
1826          * to USB2
1827          */
1828         value = readl_relaxed(pll->clk_base + UTMIPLL_HW_PWRDN_CFG0);
1829         value |= UTMIPLL_HW_PWRDN_CFG0_IDDQ_SWCTL;
1830         value &= ~UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE;
1831         writel_relaxed(value, pll->clk_base + UTMIPLL_HW_PWRDN_CFG0);
1832
1833         udelay(1);
1834
1835         /* Enable HW control of UTMIPLL */
1836         value = readl_relaxed(pll->clk_base + UTMIPLL_HW_PWRDN_CFG0);
1837         value |= UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE;
1838         writel_relaxed(value, pll->clk_base + UTMIPLL_HW_PWRDN_CFG0);
1839
1840 out:
1841         if (pll->lock)
1842                 spin_unlock_irqrestore(pll->lock, flags);
1843
1844         return ret;
1845 }
1846
1847 static void _clk_plle_tegra_init_parent(struct tegra_clk_pll *pll)
1848 {
1849         u32 val, val_aux;
1850
1851         /* ensure parent is set to pll_ref */
1852         val = pll_readl_base(pll);
1853         val_aux = pll_readl(pll->params->aux_reg, pll);
1854
1855         if (val & PLL_BASE_ENABLE) {
1856                 if ((val_aux & PLLE_AUX_PLLRE_SEL) ||
1857                     (val_aux & PLLE_AUX_PLLP_SEL))
1858                         WARN(1, "pll_e enabled with unsupported parent %s\n",
1859                              (val_aux & PLLE_AUX_PLLP_SEL) ? "pllp_out0" :
1860                              "pll_re_vco");
1861         } else {
1862                 val_aux &= ~(PLLE_AUX_PLLRE_SEL | PLLE_AUX_PLLP_SEL);
1863                 pll_writel(val_aux, pll->params->aux_reg, pll);
1864                 fence_udelay(1, pll->clk_base);
1865         }
1866 }
1867 #endif
1868
1869 static struct tegra_clk_pll *_tegra_init_pll(void __iomem *clk_base,
1870                 void __iomem *pmc, struct tegra_clk_pll_params *pll_params,
1871                 spinlock_t *lock)
1872 {
1873         struct tegra_clk_pll *pll;
1874
1875         pll = kzalloc(sizeof(*pll), GFP_KERNEL);
1876         if (!pll)
1877                 return ERR_PTR(-ENOMEM);
1878
1879         pll->clk_base = clk_base;
1880         pll->pmc = pmc;
1881
1882         pll->params = pll_params;
1883         pll->lock = lock;
1884
1885         if (!pll_params->div_nmp)
1886                 pll_params->div_nmp = &default_nmp;
1887
1888         return pll;
1889 }
1890
1891 static struct clk *_tegra_clk_register_pll(struct tegra_clk_pll *pll,
1892                 const char *name, const char *parent_name, unsigned long flags,
1893                 const struct clk_ops *ops)
1894 {
1895         struct clk_init_data init;
1896
1897         init.name = name;
1898         init.ops = ops;
1899         init.flags = flags;
1900         init.parent_names = (parent_name ? &parent_name : NULL);
1901         init.num_parents = (parent_name ? 1 : 0);
1902
1903         /* Default to _calc_rate if unspecified */
1904         if (!pll->params->calc_rate) {
1905                 if (pll->params->flags & TEGRA_PLLM)
1906                         pll->params->calc_rate = _calc_dynamic_ramp_rate;
1907                 else
1908                         pll->params->calc_rate = _calc_rate;
1909         }
1910
1911         if (pll->params->set_defaults)
1912                 pll->params->set_defaults(pll);
1913
1914         /* Data in .init is copied by clk_register(), so stack variable OK */
1915         pll->hw.init = &init;
1916
1917         return tegra_clk_dev_register(&pll->hw);
1918 }
1919
1920 struct clk *tegra_clk_register_pll(const char *name, const char *parent_name,
1921                 void __iomem *clk_base, void __iomem *pmc,
1922                 unsigned long flags, struct tegra_clk_pll_params *pll_params,
1923                 spinlock_t *lock)
1924 {
1925         struct tegra_clk_pll *pll;
1926         struct clk *clk;
1927
1928         pll_params->flags |= TEGRA_PLL_BYPASS;
1929
1930         pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
1931         if (IS_ERR(pll))
1932                 return ERR_CAST(pll);
1933
1934         clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
1935                                       &tegra_clk_pll_ops);
1936         if (IS_ERR(clk))
1937                 kfree(pll);
1938
1939         return clk;
1940 }
1941
1942 static struct div_nmp pll_e_nmp = {
1943         .divn_shift = PLLE_BASE_DIVN_SHIFT,
1944         .divn_width = PLLE_BASE_DIVN_WIDTH,
1945         .divm_shift = PLLE_BASE_DIVM_SHIFT,
1946         .divm_width = PLLE_BASE_DIVM_WIDTH,
1947         .divp_shift = PLLE_BASE_DIVP_SHIFT,
1948         .divp_width = PLLE_BASE_DIVP_WIDTH,
1949 };
1950
1951 struct clk *tegra_clk_register_plle(const char *name, const char *parent_name,
1952                 void __iomem *clk_base, void __iomem *pmc,
1953                 unsigned long flags, struct tegra_clk_pll_params *pll_params,
1954                 spinlock_t *lock)
1955 {
1956         struct tegra_clk_pll *pll;
1957         struct clk *clk;
1958
1959         pll_params->flags |= TEGRA_PLL_BYPASS;
1960
1961         if (!pll_params->div_nmp)
1962                 pll_params->div_nmp = &pll_e_nmp;
1963
1964         pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
1965         if (IS_ERR(pll))
1966                 return ERR_CAST(pll);
1967
1968         clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
1969                                       &tegra_clk_plle_ops);
1970         if (IS_ERR(clk))
1971                 kfree(pll);
1972
1973         return clk;
1974 }
1975
1976 struct clk *tegra_clk_register_pllu(const char *name, const char *parent_name,
1977                 void __iomem *clk_base, unsigned long flags,
1978                 struct tegra_clk_pll_params *pll_params, spinlock_t *lock)
1979 {
1980         struct tegra_clk_pll *pll;
1981         struct clk *clk;
1982
1983         pll_params->flags |= TEGRA_PLLU;
1984
1985         pll = _tegra_init_pll(clk_base, NULL, pll_params, lock);
1986         if (IS_ERR(pll))
1987                 return ERR_CAST(pll);
1988
1989         clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
1990                                       &tegra_clk_pllu_ops);
1991         if (IS_ERR(clk))
1992                 kfree(pll);
1993
1994         return clk;
1995 }
1996
1997 #if defined(CONFIG_ARCH_TEGRA_114_SOC) || \
1998         defined(CONFIG_ARCH_TEGRA_124_SOC) || \
1999         defined(CONFIG_ARCH_TEGRA_132_SOC) || \
2000         defined(CONFIG_ARCH_TEGRA_210_SOC)
2001 static const struct clk_ops tegra_clk_pllxc_ops = {
2002         .is_enabled = clk_pll_is_enabled,
2003         .enable = clk_pll_enable,
2004         .disable = clk_pll_disable,
2005         .recalc_rate = clk_pll_recalc_rate,
2006         .round_rate = clk_pll_ramp_round_rate,
2007         .set_rate = clk_pllxc_set_rate,
2008 };
2009
2010 static const struct clk_ops tegra_clk_pllc_ops = {
2011         .is_enabled = clk_pll_is_enabled,
2012         .enable = clk_pllc_enable,
2013         .disable = clk_pllc_disable,
2014         .recalc_rate = clk_pll_recalc_rate,
2015         .round_rate = clk_pll_ramp_round_rate,
2016         .set_rate = clk_pllc_set_rate,
2017 };
2018
2019 static const struct clk_ops tegra_clk_pllre_ops = {
2020         .is_enabled = clk_pll_is_enabled,
2021         .enable = clk_pll_enable,
2022         .disable = clk_pll_disable,
2023         .recalc_rate = clk_pllre_recalc_rate,
2024         .round_rate = clk_pllre_round_rate,
2025         .set_rate = clk_pllre_set_rate,
2026 };
2027
2028 static const struct clk_ops tegra_clk_plle_tegra114_ops = {
2029         .is_enabled =  clk_pll_is_enabled,
2030         .enable = clk_plle_tegra114_enable,
2031         .disable = clk_plle_tegra114_disable,
2032         .recalc_rate = clk_pll_recalc_rate,
2033 };
2034
2035 static const struct clk_ops tegra_clk_pllu_tegra114_ops = {
2036         .is_enabled =  clk_pll_is_enabled,
2037         .enable = clk_pllu_tegra114_enable,
2038         .disable = clk_pll_disable,
2039         .recalc_rate = clk_pll_recalc_rate,
2040 };
2041
2042 struct clk *tegra_clk_register_pllxc(const char *name, const char *parent_name,
2043                           void __iomem *clk_base, void __iomem *pmc,
2044                           unsigned long flags,
2045                           struct tegra_clk_pll_params *pll_params,
2046                           spinlock_t *lock)
2047 {
2048         struct tegra_clk_pll *pll;
2049         struct clk *clk, *parent;
2050         unsigned long parent_rate;
2051         u32 val, val_iddq;
2052
2053         parent = __clk_lookup(parent_name);
2054         if (!parent) {
2055                 WARN(1, "parent clk %s of %s must be registered first\n",
2056                         parent_name, name);
2057                 return ERR_PTR(-EINVAL);
2058         }
2059
2060         if (!pll_params->pdiv_tohw)
2061                 return ERR_PTR(-EINVAL);
2062
2063         parent_rate = clk_get_rate(parent);
2064
2065         pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
2066
2067         if (pll_params->adjust_vco)
2068                 pll_params->vco_min = pll_params->adjust_vco(pll_params,
2069                                                              parent_rate);
2070
2071         /*
2072          * If the pll has a set_defaults callback, it will take care of
2073          * configuring dynamic ramping and setting IDDQ in that path.
2074          */
2075         if (!pll_params->set_defaults) {
2076                 int err;
2077
2078                 err = _setup_dynamic_ramp(pll_params, clk_base, parent_rate);
2079                 if (err)
2080                         return ERR_PTR(err);
2081
2082                 val = readl_relaxed(clk_base + pll_params->base_reg);
2083                 val_iddq = readl_relaxed(clk_base + pll_params->iddq_reg);
2084
2085                 if (val & PLL_BASE_ENABLE)
2086                         WARN_ON(val_iddq & BIT(pll_params->iddq_bit_idx));
2087                 else {
2088                         val_iddq |= BIT(pll_params->iddq_bit_idx);
2089                         writel_relaxed(val_iddq,
2090                                        clk_base + pll_params->iddq_reg);
2091                 }
2092         }
2093
2094         pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
2095         if (IS_ERR(pll))
2096                 return ERR_CAST(pll);
2097
2098         clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
2099                                       &tegra_clk_pllxc_ops);
2100         if (IS_ERR(clk))
2101                 kfree(pll);
2102
2103         return clk;
2104 }
2105
2106 struct clk *tegra_clk_register_pllre(const char *name, const char *parent_name,
2107                           void __iomem *clk_base, void __iomem *pmc,
2108                           unsigned long flags,
2109                           struct tegra_clk_pll_params *pll_params,
2110                           spinlock_t *lock, unsigned long parent_rate)
2111 {
2112         u32 val;
2113         struct tegra_clk_pll *pll;
2114         struct clk *clk;
2115
2116         pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
2117
2118         if (pll_params->adjust_vco)
2119                 pll_params->vco_min = pll_params->adjust_vco(pll_params,
2120                                                              parent_rate);
2121
2122         pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
2123         if (IS_ERR(pll))
2124                 return ERR_CAST(pll);
2125
2126         /* program minimum rate by default */
2127
2128         val = pll_readl_base(pll);
2129         if (val & PLL_BASE_ENABLE)
2130                 WARN_ON(readl_relaxed(clk_base + pll_params->iddq_reg) &
2131                                 BIT(pll_params->iddq_bit_idx));
2132         else {
2133                 int m;
2134
2135                 m = _pll_fixed_mdiv(pll_params, parent_rate);
2136                 val = m << divm_shift(pll);
2137                 val |= (pll_params->vco_min / parent_rate) << divn_shift(pll);
2138                 pll_writel_base(val, pll);
2139         }
2140
2141         /* disable lock override */
2142
2143         val = pll_readl_misc(pll);
2144         val &= ~BIT(29);
2145         pll_writel_misc(val, pll);
2146
2147         clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
2148                                       &tegra_clk_pllre_ops);
2149         if (IS_ERR(clk))
2150                 kfree(pll);
2151
2152         return clk;
2153 }
2154
2155 struct clk *tegra_clk_register_pllm(const char *name, const char *parent_name,
2156                           void __iomem *clk_base, void __iomem *pmc,
2157                           unsigned long flags,
2158                           struct tegra_clk_pll_params *pll_params,
2159                           spinlock_t *lock)
2160 {
2161         struct tegra_clk_pll *pll;
2162         struct clk *clk, *parent;
2163         unsigned long parent_rate;
2164
2165         if (!pll_params->pdiv_tohw)
2166                 return ERR_PTR(-EINVAL);
2167
2168         parent = __clk_lookup(parent_name);
2169         if (!parent) {
2170                 WARN(1, "parent clk %s of %s must be registered first\n",
2171                         parent_name, name);
2172                 return ERR_PTR(-EINVAL);
2173         }
2174
2175         parent_rate = clk_get_rate(parent);
2176
2177         pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
2178
2179         if (pll_params->adjust_vco)
2180                 pll_params->vco_min = pll_params->adjust_vco(pll_params,
2181                                                              parent_rate);
2182
2183         pll_params->flags |= TEGRA_PLL_BYPASS;
2184         pll_params->flags |= TEGRA_PLLM;
2185         pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
2186         if (IS_ERR(pll))
2187                 return ERR_CAST(pll);
2188
2189         clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
2190                                       &tegra_clk_pll_ops);
2191         if (IS_ERR(clk))
2192                 kfree(pll);
2193
2194         return clk;
2195 }
2196
2197 struct clk *tegra_clk_register_pllc(const char *name, const char *parent_name,
2198                           void __iomem *clk_base, void __iomem *pmc,
2199                           unsigned long flags,
2200                           struct tegra_clk_pll_params *pll_params,
2201                           spinlock_t *lock)
2202 {
2203         struct clk *parent, *clk;
2204         const struct pdiv_map *p_tohw = pll_params->pdiv_tohw;
2205         struct tegra_clk_pll *pll;
2206         struct tegra_clk_pll_freq_table cfg;
2207         unsigned long parent_rate;
2208
2209         if (!p_tohw)
2210                 return ERR_PTR(-EINVAL);
2211
2212         parent = __clk_lookup(parent_name);
2213         if (!parent) {
2214                 WARN(1, "parent clk %s of %s must be registered first\n",
2215                         parent_name, name);
2216                 return ERR_PTR(-EINVAL);
2217         }
2218
2219         parent_rate = clk_get_rate(parent);
2220
2221         pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
2222
2223         pll_params->flags |= TEGRA_PLL_BYPASS;
2224         pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
2225         if (IS_ERR(pll))
2226                 return ERR_CAST(pll);
2227
2228         /*
2229          * Most of PLLC register fields are shadowed, and can not be read
2230          * directly from PLL h/w. Hence, actual PLLC boot state is unknown.
2231          * Initialize PLL to default state: disabled, reset; shadow registers
2232          * loaded with default parameters; dividers are preset for half of
2233          * minimum VCO rate (the latter assured that shadowed divider settings
2234          * are within supported range).
2235          */
2236
2237         cfg.m = _pll_fixed_mdiv(pll_params, parent_rate);
2238         cfg.n = cfg.m * pll_params->vco_min / parent_rate;
2239
2240         while (p_tohw->pdiv) {
2241                 if (p_tohw->pdiv == 2) {
2242                         cfg.p = p_tohw->hw_val;
2243                         break;
2244                 }
2245                 p_tohw++;
2246         }
2247
2248         if (!p_tohw->pdiv) {
2249                 WARN_ON(1);
2250                 return ERR_PTR(-EINVAL);
2251         }
2252
2253         pll_writel_base(0, pll);
2254         _update_pll_mnp(pll, &cfg);
2255
2256         pll_writel_misc(PLLCX_MISC_DEFAULT, pll);
2257         pll_writel(PLLCX_MISC1_DEFAULT, pll_params->ext_misc_reg[0], pll);
2258         pll_writel(PLLCX_MISC2_DEFAULT, pll_params->ext_misc_reg[1], pll);
2259         pll_writel(PLLCX_MISC3_DEFAULT, pll_params->ext_misc_reg[2], pll);
2260
2261         _pllcx_update_dynamic_coef(pll, parent_rate, cfg.n);
2262
2263         clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
2264                                       &tegra_clk_pllc_ops);
2265         if (IS_ERR(clk))
2266                 kfree(pll);
2267
2268         return clk;
2269 }
2270
2271 struct clk *tegra_clk_register_plle_tegra114(const char *name,
2272                                 const char *parent_name,
2273                                 void __iomem *clk_base, unsigned long flags,
2274                                 struct tegra_clk_pll_params *pll_params,
2275                                 spinlock_t *lock)
2276 {
2277         struct tegra_clk_pll *pll;
2278         struct clk *clk;
2279
2280         pll = _tegra_init_pll(clk_base, NULL, pll_params, lock);
2281         if (IS_ERR(pll))
2282                 return ERR_CAST(pll);
2283
2284         _clk_plle_tegra_init_parent(pll);
2285
2286         clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
2287                                       &tegra_clk_plle_tegra114_ops);
2288         if (IS_ERR(clk))
2289                 kfree(pll);
2290
2291         return clk;
2292 }
2293
2294 struct clk *
2295 tegra_clk_register_pllu_tegra114(const char *name, const char *parent_name,
2296                                  void __iomem *clk_base, unsigned long flags,
2297                                  struct tegra_clk_pll_params *pll_params,
2298                                  spinlock_t *lock)
2299 {
2300         struct tegra_clk_pll *pll;
2301         struct clk *clk;
2302
2303         pll_params->flags |= TEGRA_PLLU;
2304
2305         pll = _tegra_init_pll(clk_base, NULL, pll_params, lock);
2306         if (IS_ERR(pll))
2307                 return ERR_CAST(pll);
2308
2309         clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
2310                                       &tegra_clk_pllu_tegra114_ops);
2311         if (IS_ERR(clk))
2312                 kfree(pll);
2313
2314         return clk;
2315 }
2316 #endif
2317
2318 #if defined(CONFIG_ARCH_TEGRA_124_SOC) || defined(CONFIG_ARCH_TEGRA_132_SOC) || defined(CONFIG_ARCH_TEGRA_210_SOC)
2319 static const struct clk_ops tegra_clk_pllss_ops = {
2320         .is_enabled = clk_pll_is_enabled,
2321         .enable = clk_pll_enable,
2322         .disable = clk_pll_disable,
2323         .recalc_rate = clk_pll_recalc_rate,
2324         .round_rate = clk_pll_ramp_round_rate,
2325         .set_rate = clk_pllxc_set_rate,
2326         .restore_context = tegra_clk_pll_restore_context,
2327 };
2328
2329 struct clk *tegra_clk_register_pllss(const char *name, const char *parent_name,
2330                                 void __iomem *clk_base, unsigned long flags,
2331                                 struct tegra_clk_pll_params *pll_params,
2332                                 spinlock_t *lock)
2333 {
2334         struct tegra_clk_pll *pll;
2335         struct clk *clk, *parent;
2336         struct tegra_clk_pll_freq_table cfg;
2337         unsigned long parent_rate;
2338         u32 val, val_iddq;
2339         int i;
2340
2341         if (!pll_params->div_nmp)
2342                 return ERR_PTR(-EINVAL);
2343
2344         parent = __clk_lookup(parent_name);
2345         if (!parent) {
2346                 WARN(1, "parent clk %s of %s must be registered first\n",
2347                         parent_name, name);
2348                 return ERR_PTR(-EINVAL);
2349         }
2350
2351         pll = _tegra_init_pll(clk_base, NULL, pll_params, lock);
2352         if (IS_ERR(pll))
2353                 return ERR_CAST(pll);
2354
2355         val = pll_readl_base(pll);
2356         val &= ~PLLSS_REF_SRC_SEL_MASK;
2357         pll_writel_base(val, pll);
2358
2359         parent_rate = clk_get_rate(parent);
2360
2361         pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
2362
2363         /* initialize PLL to minimum rate */
2364
2365         cfg.m = _pll_fixed_mdiv(pll_params, parent_rate);
2366         cfg.n = cfg.m * pll_params->vco_min / parent_rate;
2367
2368         for (i = 0; pll_params->pdiv_tohw[i].pdiv; i++)
2369                 ;
2370         if (!i) {
2371                 kfree(pll);
2372                 return ERR_PTR(-EINVAL);
2373         }
2374
2375         cfg.p = pll_params->pdiv_tohw[i-1].hw_val;
2376
2377         _update_pll_mnp(pll, &cfg);
2378
2379         pll_writel_misc(PLLSS_MISC_DEFAULT, pll);
2380         pll_writel(PLLSS_CFG_DEFAULT, pll_params->ext_misc_reg[0], pll);
2381         pll_writel(PLLSS_CTRL1_DEFAULT, pll_params->ext_misc_reg[1], pll);
2382         pll_writel(PLLSS_CTRL1_DEFAULT, pll_params->ext_misc_reg[2], pll);
2383
2384         val = pll_readl_base(pll);
2385         val_iddq = readl_relaxed(clk_base + pll_params->iddq_reg);
2386         if (val & PLL_BASE_ENABLE) {
2387                 if (val_iddq & BIT(pll_params->iddq_bit_idx)) {
2388                         WARN(1, "%s is on but IDDQ set\n", name);
2389                         kfree(pll);
2390                         return ERR_PTR(-EINVAL);
2391                 }
2392         } else {
2393                 val_iddq |= BIT(pll_params->iddq_bit_idx);
2394                 writel_relaxed(val_iddq, clk_base + pll_params->iddq_reg);
2395         }
2396
2397         val &= ~PLLSS_LOCK_OVERRIDE;
2398         pll_writel_base(val, pll);
2399
2400         clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
2401                                         &tegra_clk_pllss_ops);
2402
2403         if (IS_ERR(clk))
2404                 kfree(pll);
2405
2406         return clk;
2407 }
2408 #endif
2409
2410 #if defined(CONFIG_ARCH_TEGRA_210_SOC)
2411 struct clk *tegra_clk_register_pllre_tegra210(const char *name,
2412                           const char *parent_name, void __iomem *clk_base,
2413                           void __iomem *pmc, unsigned long flags,
2414                           struct tegra_clk_pll_params *pll_params,
2415                           spinlock_t *lock, unsigned long parent_rate)
2416 {
2417         struct tegra_clk_pll *pll;
2418         struct clk *clk;
2419
2420         pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
2421
2422         if (pll_params->adjust_vco)
2423                 pll_params->vco_min = pll_params->adjust_vco(pll_params,
2424                                                              parent_rate);
2425
2426         pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
2427         if (IS_ERR(pll))
2428                 return ERR_CAST(pll);
2429
2430         clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
2431                                       &tegra_clk_pll_ops);
2432         if (IS_ERR(clk))
2433                 kfree(pll);
2434
2435         return clk;
2436 }
2437
2438 static int clk_plle_tegra210_is_enabled(struct clk_hw *hw)
2439 {
2440         struct tegra_clk_pll *pll = to_clk_pll(hw);
2441         u32 val;
2442
2443         val = pll_readl_base(pll);
2444
2445         return val & PLLE_BASE_ENABLE ? 1 : 0;
2446 }
2447
2448 static int clk_plle_tegra210_enable(struct clk_hw *hw)
2449 {
2450         struct tegra_clk_pll *pll = to_clk_pll(hw);
2451         struct tegra_clk_pll_freq_table sel;
2452         u32 val;
2453         int ret = 0;
2454         unsigned long flags = 0;
2455         unsigned long input_rate;
2456
2457         if (clk_plle_tegra210_is_enabled(hw))
2458                 return 0;
2459
2460         input_rate = clk_hw_get_rate(clk_hw_get_parent(hw));
2461
2462         if (_get_table_rate(hw, &sel, pll->params->fixed_rate, input_rate))
2463                 return -EINVAL;
2464
2465         if (pll->lock)
2466                 spin_lock_irqsave(pll->lock, flags);
2467
2468         val = pll_readl(pll->params->aux_reg, pll);
2469         if (val & PLLE_AUX_SEQ_ENABLE)
2470                 goto out;
2471
2472         val = pll_readl_base(pll);
2473         val &= ~BIT(30); /* Disable lock override */
2474         pll_writel_base(val, pll);
2475
2476         val = pll_readl_misc(pll);
2477         val |= PLLE_MISC_LOCK_ENABLE;
2478         val |= PLLE_MISC_IDDQ_SW_CTRL;
2479         val &= ~PLLE_MISC_IDDQ_SW_VALUE;
2480         val |= PLLE_MISC_PLLE_PTS;
2481         val &= ~(PLLE_MISC_VREG_BG_CTRL_MASK | PLLE_MISC_VREG_CTRL_MASK);
2482         pll_writel_misc(val, pll);
2483         udelay(5);
2484
2485         val = pll_readl(PLLE_SS_CTRL, pll);
2486         val |= PLLE_SS_DISABLE;
2487         pll_writel(val, PLLE_SS_CTRL, pll);
2488
2489         val = pll_readl_base(pll);
2490         val &= ~(divp_mask_shifted(pll) | divn_mask_shifted(pll) |
2491                  divm_mask_shifted(pll));
2492         val &= ~(PLLE_BASE_DIVCML_MASK << PLLE_BASE_DIVCML_SHIFT);
2493         val |= sel.m << divm_shift(pll);
2494         val |= sel.n << divn_shift(pll);
2495         val |= sel.cpcon << PLLE_BASE_DIVCML_SHIFT;
2496         pll_writel_base(val, pll);
2497         udelay(1);
2498
2499         val = pll_readl_base(pll);
2500         val |= PLLE_BASE_ENABLE;
2501         pll_writel_base(val, pll);
2502
2503         ret = clk_pll_wait_for_lock(pll);
2504
2505         if (ret < 0)
2506                 goto out;
2507
2508         val = pll_readl(PLLE_SS_CTRL, pll);
2509         val &= ~(PLLE_SS_CNTL_CENTER | PLLE_SS_CNTL_INVERT);
2510         val &= ~PLLE_SS_COEFFICIENTS_MASK;
2511         val |= PLLE_SS_COEFFICIENTS_VAL_TEGRA210;
2512         pll_writel(val, PLLE_SS_CTRL, pll);
2513         val &= ~(PLLE_SS_CNTL_SSC_BYP | PLLE_SS_CNTL_BYPASS_SS);
2514         pll_writel(val, PLLE_SS_CTRL, pll);
2515         udelay(1);
2516         val &= ~PLLE_SS_CNTL_INTERP_RESET;
2517         pll_writel(val, PLLE_SS_CTRL, pll);
2518         udelay(1);
2519
2520 out:
2521         if (pll->lock)
2522                 spin_unlock_irqrestore(pll->lock, flags);
2523
2524         return ret;
2525 }
2526
2527 static void clk_plle_tegra210_disable(struct clk_hw *hw)
2528 {
2529         struct tegra_clk_pll *pll = to_clk_pll(hw);
2530         unsigned long flags = 0;
2531         u32 val;
2532
2533         if (pll->lock)
2534                 spin_lock_irqsave(pll->lock, flags);
2535
2536         /* If PLLE HW sequencer is enabled, SW should not disable PLLE */
2537         val = pll_readl(pll->params->aux_reg, pll);
2538         if (val & PLLE_AUX_SEQ_ENABLE)
2539                 goto out;
2540
2541         val = pll_readl_base(pll);
2542         val &= ~PLLE_BASE_ENABLE;
2543         pll_writel_base(val, pll);
2544
2545         val = pll_readl(pll->params->aux_reg, pll);
2546         val |= PLLE_AUX_ENABLE_SWCTL | PLLE_AUX_SS_SWCTL;
2547         pll_writel(val, pll->params->aux_reg, pll);
2548
2549         val = pll_readl_misc(pll);
2550         val |= PLLE_MISC_IDDQ_SW_CTRL | PLLE_MISC_IDDQ_SW_VALUE;
2551         pll_writel_misc(val, pll);
2552         udelay(1);
2553
2554 out:
2555         if (pll->lock)
2556                 spin_unlock_irqrestore(pll->lock, flags);
2557 }
2558
2559 static void tegra_clk_plle_t210_restore_context(struct clk_hw *hw)
2560 {
2561         struct tegra_clk_pll *pll = to_clk_pll(hw);
2562
2563         _clk_plle_tegra_init_parent(pll);
2564 }
2565
2566 static const struct clk_ops tegra_clk_plle_tegra210_ops = {
2567         .is_enabled =  clk_plle_tegra210_is_enabled,
2568         .enable = clk_plle_tegra210_enable,
2569         .disable = clk_plle_tegra210_disable,
2570         .recalc_rate = clk_pll_recalc_rate,
2571         .restore_context = tegra_clk_plle_t210_restore_context,
2572 };
2573
2574 struct clk *tegra_clk_register_plle_tegra210(const char *name,
2575                                 const char *parent_name,
2576                                 void __iomem *clk_base, unsigned long flags,
2577                                 struct tegra_clk_pll_params *pll_params,
2578                                 spinlock_t *lock)
2579 {
2580         struct tegra_clk_pll *pll;
2581         struct clk *clk;
2582
2583         pll = _tegra_init_pll(clk_base, NULL, pll_params, lock);
2584         if (IS_ERR(pll))
2585                 return ERR_CAST(pll);
2586
2587         _clk_plle_tegra_init_parent(pll);
2588
2589         clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
2590                                       &tegra_clk_plle_tegra210_ops);
2591         if (IS_ERR(clk))
2592                 kfree(pll);
2593
2594         return clk;
2595 }
2596
2597 struct clk *tegra_clk_register_pllc_tegra210(const char *name,
2598                         const char *parent_name, void __iomem *clk_base,
2599                         void __iomem *pmc, unsigned long flags,
2600                         struct tegra_clk_pll_params *pll_params,
2601                         spinlock_t *lock)
2602 {
2603         struct clk *parent, *clk;
2604         const struct pdiv_map *p_tohw = pll_params->pdiv_tohw;
2605         struct tegra_clk_pll *pll;
2606         unsigned long parent_rate;
2607
2608         if (!p_tohw)
2609                 return ERR_PTR(-EINVAL);
2610
2611         parent = __clk_lookup(parent_name);
2612         if (!parent) {
2613                 WARN(1, "parent clk %s of %s must be registered first\n",
2614                         name, parent_name);
2615                 return ERR_PTR(-EINVAL);
2616         }
2617
2618         parent_rate = clk_get_rate(parent);
2619
2620         pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
2621
2622         if (pll_params->adjust_vco)
2623                 pll_params->vco_min = pll_params->adjust_vco(pll_params,
2624                                                              parent_rate);
2625
2626         pll_params->flags |= TEGRA_PLL_BYPASS;
2627         pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
2628         if (IS_ERR(pll))
2629                 return ERR_CAST(pll);
2630
2631         clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
2632                                       &tegra_clk_pll_ops);
2633         if (IS_ERR(clk))
2634                 kfree(pll);
2635
2636         return clk;
2637 }
2638
2639 struct clk *tegra_clk_register_pllss_tegra210(const char *name,
2640                                 const char *parent_name, void __iomem *clk_base,
2641                                 unsigned long flags,
2642                                 struct tegra_clk_pll_params *pll_params,
2643                                 spinlock_t *lock)
2644 {
2645         struct tegra_clk_pll *pll;
2646         struct clk *clk, *parent;
2647         unsigned long parent_rate;
2648         u32 val;
2649
2650         if (!pll_params->div_nmp)
2651                 return ERR_PTR(-EINVAL);
2652
2653         parent = __clk_lookup(parent_name);
2654         if (!parent) {
2655                 WARN(1, "parent clk %s of %s must be registered first\n",
2656                         name, parent_name);
2657                 return ERR_PTR(-EINVAL);
2658         }
2659
2660         val = readl_relaxed(clk_base + pll_params->base_reg);
2661         if (val & PLLSS_REF_SRC_SEL_MASK) {
2662                 WARN(1, "not supported reference clock for %s\n", name);
2663                 return ERR_PTR(-EINVAL);
2664         }
2665
2666         parent_rate = clk_get_rate(parent);
2667
2668         pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
2669
2670         if (pll_params->adjust_vco)
2671                 pll_params->vco_min = pll_params->adjust_vco(pll_params,
2672                                                              parent_rate);
2673
2674         pll_params->flags |= TEGRA_PLL_BYPASS;
2675         pll = _tegra_init_pll(clk_base, NULL, pll_params, lock);
2676         if (IS_ERR(pll))
2677                 return ERR_CAST(pll);
2678
2679         clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
2680                                         &tegra_clk_pll_ops);
2681
2682         if (IS_ERR(clk))
2683                 kfree(pll);
2684
2685         return clk;
2686 }
2687
2688 struct clk *tegra_clk_register_pllmb(const char *name, const char *parent_name,
2689                           void __iomem *clk_base, void __iomem *pmc,
2690                           unsigned long flags,
2691                           struct tegra_clk_pll_params *pll_params,
2692                           spinlock_t *lock)
2693 {
2694         struct tegra_clk_pll *pll;
2695         struct clk *clk, *parent;
2696         unsigned long parent_rate;
2697
2698         if (!pll_params->pdiv_tohw)
2699                 return ERR_PTR(-EINVAL);
2700
2701         parent = __clk_lookup(parent_name);
2702         if (!parent) {
2703                 WARN(1, "parent clk %s of %s must be registered first\n",
2704                         parent_name, name);
2705                 return ERR_PTR(-EINVAL);
2706         }
2707
2708         parent_rate = clk_get_rate(parent);
2709
2710         pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
2711
2712         if (pll_params->adjust_vco)
2713                 pll_params->vco_min = pll_params->adjust_vco(pll_params,
2714                                                              parent_rate);
2715
2716         pll_params->flags |= TEGRA_PLL_BYPASS;
2717         pll_params->flags |= TEGRA_PLLMB;
2718         pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
2719         if (IS_ERR(pll))
2720                 return ERR_CAST(pll);
2721
2722         clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
2723                                       &tegra_clk_pll_ops);
2724         if (IS_ERR(clk))
2725                 kfree(pll);
2726
2727         return clk;
2728 }
2729
2730 #endif