drivers/clk/sunxi-ng/ccu-sun5i.c

   1 /*
   2  * Copyright (c) 2016 Maxime Ripard. All rights reserved.
   3  *
   4  * This software is licensed under the terms of the GNU General Public
   5  * License version 2, as published by the Free Software Foundation, and
   6  * may be copied, distributed, and modified under those terms.
   7  *
   8  * This program is distributed in the hope that it will be useful,
   9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  */
  13
  14 #include <linux/clk-provider.h>
  15 #include <linux/of_address.h>
  16
  17 #include "ccu_common.h"
  18 #include "ccu_reset.h"
  19
  20 #include "ccu_div.h"
  21 #include "ccu_gate.h"
  22 #include "ccu_mp.h"
  23 #include "ccu_mult.h"
  24 #include "ccu_nk.h"
  25 #include "ccu_nkm.h"
  26 #include "ccu_nkmp.h"
  27 #include "ccu_nm.h"
  28 #include "ccu_phase.h"
  29
  30 #include "ccu-sun5i.h"
  31
  32 static struct ccu_nkmp pll_core_clk = {
  33         .enable         = BIT(31),
  34         .n              = _SUNXI_CCU_MULT_OFFSET(8, 5, 0),
  35         .k              = _SUNXI_CCU_MULT(4, 2),
  36         .m              = _SUNXI_CCU_DIV(0, 2),
  37         .p              = _SUNXI_CCU_DIV(16, 2),
  38         .common         = {
  39                 .reg            = 0x000,
  40                 .hw.init        = CLK_HW_INIT("pll-core",
  41                                               "hosc",
  42                                               &ccu_nkmp_ops,
  43                                               0),
  44         },
  45 };
  46
  47 /*
  48  * The Audio PLL is supposed to have 4 outputs: 3 fixed factors from
  49  * the base (2x, 4x and 8x), and one variable divider (the one true
  50  * pll audio).
  51  *
  52  * We don't have any need for the variable divider for now, so we just
  53  * hardcode it to match with the clock names
  54  */
  55 #define SUN5I_PLL_AUDIO_REG     0x008
  56
  57 static struct ccu_nm pll_audio_base_clk = {
  58         .enable         = BIT(31),
  59         .n              = _SUNXI_CCU_MULT_OFFSET(8, 7, 0),
  60
  61         /*
  62          * The datasheet is wrong here, this doesn't have any
  63          * offset
  64          */
  65         .m              = _SUNXI_CCU_DIV_OFFSET(0, 5, 0),
  66         .common         = {
  67                 .reg            = 0x008,
  68                 .hw.init        = CLK_HW_INIT("pll-audio-base",
  69                                               "hosc",
  70                                               &ccu_nm_ops,
  71                                               0),
  72         },
  73 };
  74
  75 static struct ccu_mult pll_video0_clk = {
  76         .enable         = BIT(31),
  77         .mult           = _SUNXI_CCU_MULT_OFFSET_MIN_MAX(0, 7, 0, 9, 127),
  78         .frac           = _SUNXI_CCU_FRAC(BIT(15), BIT(14),
  79                                           270000000, 297000000),
  80         .common         = {
  81                 .reg            = 0x010,
  82                 .features       = (CCU_FEATURE_FRACTIONAL |
  83                                    CCU_FEATURE_ALL_PREDIV),
  84                 .prediv         = 8,
  85                 .hw.init        = CLK_HW_INIT("pll-video0",
  86                                               "hosc",
  87                                               &ccu_mult_ops,
  88                                               0),
  89         },
  90 };
  91
  92 static struct ccu_nkmp pll_ve_clk = {
  93         .enable         = BIT(31),
  94         .n              = _SUNXI_CCU_MULT_OFFSET(8, 5, 0),
  95         .k              = _SUNXI_CCU_MULT(4, 2),
  96         .m              = _SUNXI_CCU_DIV(0, 2),
  97         .p              = _SUNXI_CCU_DIV(16, 2),
  98         .common         = {
  99                 .reg            = 0x018,
 100                 .hw.init        = CLK_HW_INIT("pll-ve",
 101                                               "hosc",
 102                                               &ccu_nkmp_ops,
 103                                               0),
 104         },
 105 };
 106
 107 static struct ccu_nk pll_ddr_base_clk = {
 108         .enable         = BIT(31),
 109         .n              = _SUNXI_CCU_MULT_OFFSET(8, 5, 0),
 110         .k              = _SUNXI_CCU_MULT(4, 2),
 111         .common         = {
 112                 .reg            = 0x020,
 113                 .hw.init        = CLK_HW_INIT("pll-ddr-base",
 114                                               "hosc",
 115                                               &ccu_nk_ops,
 116                                               0),
 117         },
 118 };
 119
 120 static SUNXI_CCU_M(pll_ddr_clk, "pll-ddr", "pll-ddr-base", 0x020, 0, 2,
 121                    CLK_IS_CRITICAL);
 122
 123 static struct ccu_div pll_ddr_other_clk = {
 124         .div            = _SUNXI_CCU_DIV_FLAGS(16, 2, CLK_DIVIDER_POWER_OF_TWO),
 125
 126         .common         = {
 127                 .reg            = 0x020,
 128                 .hw.init        = CLK_HW_INIT("pll-ddr-other", "pll-ddr-base",
 129                                               &ccu_div_ops,
 130                                               0),
 131         },
 132 };
 133
 134 static struct ccu_nk pll_periph_clk = {
 135         .enable         = BIT(31),
 136         .n              = _SUNXI_CCU_MULT_OFFSET(8, 5, 0),
 137         .k              = _SUNXI_CCU_MULT(4, 2),
 138         .fixed_post_div = 2,
 139         .common         = {
 140                 .reg            = 0x028,
 141                 .features       = CCU_FEATURE_FIXED_POSTDIV,
 142                 .hw.init        = CLK_HW_INIT("pll-periph",
 143                                               "hosc",
 144                                               &ccu_nk_ops,
 145                                               0),
 146         },
 147 };
 148
 149 static struct ccu_mult pll_video1_clk = {
 150         .enable         = BIT(31),
 151         .mult           = _SUNXI_CCU_MULT_OFFSET_MIN_MAX(0, 7, 0, 9, 127),
 152         .frac           = _SUNXI_CCU_FRAC(BIT(15), BIT(14),
 153                                   270000000, 297000000),
 154         .common         = {
 155                 .reg            = 0x030,
 156                 .features       = (CCU_FEATURE_FRACTIONAL |
 157                                    CCU_FEATURE_ALL_PREDIV),
 158                 .prediv         = 8,
 159                 .hw.init        = CLK_HW_INIT("pll-video1",
 160                                               "hosc",
 161                                               &ccu_mult_ops,
 162                                               0),
 163         },
 164 };
 165
 166 static SUNXI_CCU_GATE(hosc_clk, "hosc", "osc24M", 0x050, BIT(0), 0);
 167
 168 #define SUN5I_AHB_REG   0x054
 169 static const char * const cpu_parents[] = { "osc32k", "hosc",
 170                                             "pll-core" , "pll-periph" };
 171 static const struct ccu_mux_fixed_prediv cpu_predivs[] = {
 172         { .index = 3, .div = 3, },
 173 };
 174 static struct ccu_mux cpu_clk = {
 175         .mux            = {
 176                 .shift          = 16,
 177                 .width          = 2,
 178                 .fixed_predivs  = cpu_predivs,
 179                 .n_predivs      = ARRAY_SIZE(cpu_predivs),
 180         },
 181         .common         = {
 182                 .reg            = 0x054,
 183                 .features       = CCU_FEATURE_FIXED_PREDIV,
 184                 .hw.init        = CLK_HW_INIT_PARENTS("cpu",
 185                                                       cpu_parents,
 186                                                       &ccu_mux_ops,
 187                                                       CLK_IS_CRITICAL),
 188         }
 189 };
 190
 191 static SUNXI_CCU_M(axi_clk, "axi", "cpu", 0x054, 0, 2, 0);
 192
 193 static const char * const ahb_parents[] = { "axi" , "cpu", "pll-periph" };
 194 static const struct ccu_mux_fixed_prediv ahb_predivs[] = {
 195         { .index = 2, .div = 2, },
 196 };
 197 static struct ccu_div ahb_clk = {
 198         .div            = _SUNXI_CCU_DIV_FLAGS(4, 2, CLK_DIVIDER_POWER_OF_TWO),
 199         .mux            = {
 200                 .shift          = 6,
 201                 .width          = 2,
 202                 .fixed_predivs  = ahb_predivs,
 203                 .n_predivs      = ARRAY_SIZE(ahb_predivs),
 204         },
 205
 206         .common         = {
 207                 .reg            = 0x054,
 208                 .hw.init        = CLK_HW_INIT_PARENTS("ahb",
 209                                                       ahb_parents,
 210                                                       &ccu_div_ops,
 211                                                       0),
 212         },
 213 };
 214
 215 static struct clk_div_table apb0_div_table[] = {
 216         { .val = 0, .div = 2 },
 217         { .val = 1, .div = 2 },
 218         { .val = 2, .div = 4 },
 219         { .val = 3, .div = 8 },
 220         { /* Sentinel */ },
 221 };
 222 static SUNXI_CCU_DIV_TABLE(apb0_clk, "apb0", "ahb",
 223                            0x054, 8, 2, apb0_div_table, 0);
 224
 225 static const char * const apb1_parents[] = { "hosc", "pll-periph", "osc32k" };
 226 static SUNXI_CCU_MP_WITH_MUX(apb1_clk, "apb1", apb1_parents, 0x058,
 227                              0, 5,      /* M */
 228                              16, 2,     /* P */
 229                              24, 2,     /* mux */
 230                              0);
 231
 232 static SUNXI_CCU_GATE(axi_dram_clk,     "axi-dram",     "axi",
 233                       0x05c, BIT(0), 0);
 234
 235 static SUNXI_CCU_GATE(ahb_otg_clk,      "ahb-otg",      "ahb",
 236                       0x060, BIT(0), 0);
 237 static SUNXI_CCU_GATE(ahb_ehci_clk,     "ahb-ehci",     "ahb",
 238                       0x060, BIT(1), 0);
 239 static SUNXI_CCU_GATE(ahb_ohci_clk,     "ahb-ohci",     "ahb",
 240                       0x060, BIT(2), 0);
 241 static SUNXI_CCU_GATE(ahb_ss_clk,       "ahb-ss",       "ahb",
 242                       0x060, BIT(5), 0);
 243 static SUNXI_CCU_GATE(ahb_dma_clk,      "ahb-dma",      "ahb",
 244                       0x060, BIT(6), 0);
 245 static SUNXI_CCU_GATE(ahb_bist_clk,     "ahb-bist",     "ahb",
 246                       0x060, BIT(7), 0);
 247 static SUNXI_CCU_GATE(ahb_mmc0_clk,     "ahb-mmc0",     "ahb",
 248                       0x060, BIT(8), 0);
 249 static SUNXI_CCU_GATE(ahb_mmc1_clk,     "ahb-mmc1",     "ahb",
 250                       0x060, BIT(9), 0);
 251 static SUNXI_CCU_GATE(ahb_mmc2_clk,     "ahb-mmc2",     "ahb",
 252                       0x060, BIT(10), 0);
 253 static SUNXI_CCU_GATE(ahb_nand_clk,     "ahb-nand",     "ahb",
 254                       0x060, BIT(13), 0);
 255 static SUNXI_CCU_GATE(ahb_sdram_clk,    "ahb-sdram",    "ahb",
 256                       0x060, BIT(14), CLK_IS_CRITICAL);
 257 static SUNXI_CCU_GATE(ahb_emac_clk,     "ahb-emac",     "ahb",
 258                       0x060, BIT(17), 0);
 259 static SUNXI_CCU_GATE(ahb_ts_clk,       "ahb-ts",       "ahb",
 260                       0x060, BIT(18), 0);
 261 static SUNXI_CCU_GATE(ahb_spi0_clk,     "ahb-spi0",     "ahb",
 262                       0x060, BIT(20), 0);
 263 static SUNXI_CCU_GATE(ahb_spi1_clk,     "ahb-spi1",     "ahb",
 264                       0x060, BIT(21), 0);
 265 static SUNXI_CCU_GATE(ahb_spi2_clk,     "ahb-spi2",     "ahb",
 266                       0x060, BIT(22), 0);
 267 static SUNXI_CCU_GATE(ahb_gps_clk,      "ahb-gps",      "ahb",
 268                       0x060, BIT(26), 0);
 269 static SUNXI_CCU_GATE(ahb_hstimer_clk,  "ahb-hstimer",  "ahb",
 270                       0x060, BIT(28), 0);
 271
 272 static SUNXI_CCU_GATE(ahb_ve_clk,       "ahb-ve",       "ahb",
 273                       0x064, BIT(0), 0);
 274 static SUNXI_CCU_GATE(ahb_tve_clk,      "ahb-tve",      "ahb",
 275                       0x064, BIT(2), 0);
 276 static SUNXI_CCU_GATE(ahb_lcd_clk,      "ahb-lcd",      "ahb",
 277                       0x064, BIT(4), 0);
 278 static SUNXI_CCU_GATE(ahb_csi_clk,      "ahb-csi",      "ahb",
 279                       0x064, BIT(8), 0);
 280 static SUNXI_CCU_GATE(ahb_hdmi_clk,     "ahb-hdmi",     "ahb",
 281                       0x064, BIT(11), 0);
 282 static SUNXI_CCU_GATE(ahb_de_be_clk,    "ahb-de-be",    "ahb",
 283                       0x064, BIT(12), 0);
 284 static SUNXI_CCU_GATE(ahb_de_fe_clk,    "ahb-de-fe",    "ahb",
 285                       0x064, BIT(14), 0);
 286 static SUNXI_CCU_GATE(ahb_iep_clk,      "ahb-iep",      "ahb",
 287                       0x064, BIT(19), 0);
 288 static SUNXI_CCU_GATE(ahb_gpu_clk,      "ahb-gpu",      "ahb",
 289                       0x064, BIT(20), 0);
 290
 291 static SUNXI_CCU_GATE(apb0_codec_clk,   "apb0-codec",   "apb0",
 292                       0x068, BIT(0), 0);
 293 static SUNXI_CCU_GATE(apb0_spdif_clk,   "apb0-spdif",   "apb0",
 294                       0x068, BIT(1), 0);
 295 static SUNXI_CCU_GATE(apb0_i2s_clk,     "apb0-i2s",     "apb0",
 296                       0x068, BIT(3), 0);
 297 static SUNXI_CCU_GATE(apb0_pio_clk,     "apb0-pio",     "apb0",
 298                       0x068, BIT(5), 0);
 299 static SUNXI_CCU_GATE(apb0_ir_clk,      "apb0-ir",      "apb0",
 300                       0x068, BIT(6), 0);
 301 static SUNXI_CCU_GATE(apb0_keypad_clk,  "apb0-keypad",  "apb0",
 302                       0x068, BIT(10), 0);
 303
 304 static SUNXI_CCU_GATE(apb1_i2c0_clk,    "apb1-i2c0",    "apb1",
 305                       0x06c, BIT(0), 0);
 306 static SUNXI_CCU_GATE(apb1_i2c1_clk,    "apb1-i2c1",    "apb1",
 307                       0x06c, BIT(1), 0);
 308 static SUNXI_CCU_GATE(apb1_i2c2_clk,    "apb1-i2c2",    "apb1",
 309                       0x06c, BIT(2), 0);
 310 static SUNXI_CCU_GATE(apb1_uart0_clk,   "apb1-uart0",   "apb1",
 311                       0x06c, BIT(16), 0);
 312 static SUNXI_CCU_GATE(apb1_uart1_clk,   "apb1-uart1",   "apb1",
 313                       0x06c, BIT(17), 0);
 314 static SUNXI_CCU_GATE(apb1_uart2_clk,   "apb1-uart2",   "apb1",
 315                       0x06c, BIT(18), 0);
 316 static SUNXI_CCU_GATE(apb1_uart3_clk,   "apb1-uart3",   "apb1",
 317                       0x06c, BIT(19), 0);
 318
 319 static const char * const mod0_default_parents[] = { "hosc", "pll-periph",
 320                                                      "pll-ddr-other" };
 321 static SUNXI_CCU_MP_WITH_MUX_GATE(nand_clk, "nand", mod0_default_parents, 0x080,
 322                                   0, 4,         /* M */
 323                                   16, 2,        /* P */
 324                                   24, 2,        /* mux */
 325                                   BIT(31),      /* gate */
 326                                   0);
 327
 328 static SUNXI_CCU_MP_WITH_MUX_GATE(mmc0_clk, "mmc0", mod0_default_parents, 0x088,
 329                                   0, 4,         /* M */
 330                                   16, 2,        /* P */
 331                                   24, 2,        /* mux */
 332                                   BIT(31),      /* gate */
 333                                   0);
 334
 335 static SUNXI_CCU_MP_WITH_MUX_GATE(mmc1_clk, "mmc1", mod0_default_parents, 0x08c,
 336                                   0, 4,         /* M */
 337                                   16, 2,        /* P */
 338                                   24, 2,        /* mux */
 339                                   BIT(31),      /* gate */
 340                                   0);
 341
 342 static SUNXI_CCU_MP_WITH_MUX_GATE(mmc2_clk, "mmc2", mod0_default_parents, 0x090,
 343                                   0, 4,         /* M */
 344                                   16, 2,        /* P */
 345                                   24, 2,        /* mux */
 346                                   BIT(31),      /* gate */
 347                                   0);
 348
 349 static SUNXI_CCU_MP_WITH_MUX_GATE(ts_clk, "ts", mod0_default_parents, 0x098,
 350                                   0, 4,         /* M */
 351                                   16, 2,        /* P */
 352                                   24, 2,        /* mux */
 353                                   BIT(31),      /* gate */
 354                                   0);
 355
 356 static SUNXI_CCU_MP_WITH_MUX_GATE(ss_clk, "ss", mod0_default_parents, 0x09c,
 357                                   0, 4,         /* M */
 358                                   16, 2,        /* P */
 359                                   24, 2,        /* mux */
 360                                   BIT(31),      /* gate */
 361                                   0);
 362
 363 static SUNXI_CCU_MP_WITH_MUX_GATE(spi0_clk, "spi0", mod0_default_parents, 0x0a0,
 364                                   0, 4,         /* M */
 365                                   16, 2,        /* P */
 366                                   24, 2,        /* mux */
 367                                   BIT(31),      /* gate */
 368                                   0);
 369
 370 static SUNXI_CCU_MP_WITH_MUX_GATE(spi1_clk, "spi1", mod0_default_parents, 0x0a4,
 371                                   0, 4,         /* M */
 372                                   16, 2,        /* P */
 373                                   24, 2,        /* mux */
 374                                   BIT(31),      /* gate */
 375                                   0);
 376
 377 static SUNXI_CCU_MP_WITH_MUX_GATE(spi2_clk, "spi2", mod0_default_parents, 0x0a8,
 378                                   0, 4,         /* M */
 379                                   16, 2,        /* P */
 380                                   24, 2,        /* mux */
 381                                   BIT(31),      /* gate */
 382                                   0);
 383
 384 static SUNXI_CCU_MP_WITH_MUX_GATE(ir_clk, "ir", mod0_default_parents, 0x0b0,
 385                                   0, 4,         /* M */
 386                                   16, 2,        /* P */
 387                                   24, 2,        /* mux */
 388                                   BIT(31),      /* gate */
 389                                   0);
 390
 391 static const char * const i2s_parents[] = { "pll-audio-8x", "pll-audio-4x",
 392                                             "pll-audio-2x", "pll-audio" };
 393 static SUNXI_CCU_MUX_WITH_GATE(i2s_clk, "i2s", i2s_parents,
 394                                0x0b8, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
 395
 396 static const char * const spdif_parents[] = { "pll-audio-8x", "pll-audio-4x",
 397                                             "pll-audio-2x", "pll-audio" };
 398 static SUNXI_CCU_MUX_WITH_GATE(spdif_clk, "spdif", spdif_parents,
 399                                0x0c0, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
 400
 401 static const char * const keypad_parents[] = { "hosc", "losc"};
 402 static const u8 keypad_table[] = { 0, 2 };
 403 static struct ccu_mp keypad_clk = {
 404         .enable         = BIT(31),
 405         .m              = _SUNXI_CCU_DIV(8, 5),
 406         .p              = _SUNXI_CCU_DIV(20, 2),
 407         .mux            = _SUNXI_CCU_MUX_TABLE(24, 2, keypad_table),
 408
 409         .common         = {
 410                 .reg            = 0x0c4,
 411                 .hw.init        = CLK_HW_INIT_PARENTS("keypad",
 412                                                       keypad_parents,
 413                                                       &ccu_mp_ops,
 414                                                       0),
 415         },
 416 };
 417
 418 static SUNXI_CCU_GATE(usb_ohci_clk,     "usb-ohci",     "pll-periph",
 419                       0x0cc, BIT(6), 0);
 420 static SUNXI_CCU_GATE(usb_phy0_clk,     "usb-phy0",     "pll-periph",
 421                       0x0cc, BIT(8), 0);
 422 static SUNXI_CCU_GATE(usb_phy1_clk,     "usb-phy1",     "pll-periph",
 423                       0x0cc, BIT(9), 0);
 424
 425 static const char * const gps_parents[] = { "hosc", "pll-periph",
 426                                             "pll-video1", "pll-ve" };
 427 static SUNXI_CCU_M_WITH_MUX_GATE(gps_clk, "gps", gps_parents,
 428                                  0x0d0, 0, 3, 24, 2, BIT(31), 0);
 429
 430 static SUNXI_CCU_GATE(dram_ve_clk,      "dram-ve",      "pll-ddr",
 431                       0x100, BIT(0), 0);
 432 static SUNXI_CCU_GATE(dram_csi_clk,     "dram-csi",     "pll-ddr",
 433                       0x100, BIT(1), 0);
 434 static SUNXI_CCU_GATE(dram_ts_clk,      "dram-ts",      "pll-ddr",
 435                       0x100, BIT(3), 0);
 436 static SUNXI_CCU_GATE(dram_tve_clk,     "dram-tve",     "pll-ddr",
 437                       0x100, BIT(5), 0);
 438 static SUNXI_CCU_GATE(dram_de_fe_clk,   "dram-de-fe",   "pll-ddr",
 439                       0x100, BIT(25), 0);
 440 static SUNXI_CCU_GATE(dram_de_be_clk,   "dram-de-be",   "pll-ddr",
 441                       0x100, BIT(26), 0);
 442 static SUNXI_CCU_GATE(dram_ace_clk,     "dram-ace",     "pll-ddr",
 443                       0x100, BIT(29), 0);
 444 static SUNXI_CCU_GATE(dram_iep_clk,     "dram-iep",     "pll-ddr",
 445                       0x100, BIT(31), 0);
 446
 447 static const char * const de_parents[] = { "pll-video0", "pll-video1",
 448                                            "pll-ddr-other" };
 449 static SUNXI_CCU_M_WITH_MUX_GATE(de_be_clk, "de-be", de_parents,
 450                                  0x104, 0, 4, 24, 2, BIT(31), 0);
 451
 452 static SUNXI_CCU_M_WITH_MUX_GATE(de_fe_clk, "de-fe", de_parents,
 453                                  0x10c, 0, 4, 24, 2, BIT(31), 0);
 454
 455 static const char * const tcon_parents[] = { "pll-video0", "pll-video1",
 456                                              "pll-video0-2x", "pll-video1-2x" };
 457 static SUNXI_CCU_MUX_WITH_GATE(tcon_ch0_clk, "tcon-ch0-sclk", tcon_parents,
 458                                0x118, 24, 2, BIT(31), CLK_SET_RATE_PARENT);
 459
 460 static SUNXI_CCU_M_WITH_MUX_GATE(tcon_ch1_sclk2_clk, "tcon-ch1-sclk2",
 461                                  tcon_parents,
 462                                  0x12c, 0, 4, 24, 2, BIT(31), CLK_SET_RATE_PARENT);
 463
 464 static SUNXI_CCU_M_WITH_GATE(tcon_ch1_sclk1_clk, "tcon-ch1-sclk1", "tcon-ch1-sclk2",
 465                              0x12c, 11, 1, BIT(15), CLK_SET_RATE_PARENT);
 466
 467 static const char * const csi_parents[] = { "hosc", "pll-video0", "pll-video1",
 468                                             "pll-video0-2x", "pll-video1-2x" };
 469 static const u8 csi_table[] = { 0, 1, 2, 5, 6 };
 470 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(csi_clk, "csi",
 471                                        csi_parents, csi_table,
 472                                        0x134, 0, 5, 24, 3, BIT(31), 0);
 473
 474 static SUNXI_CCU_GATE(ve_clk,           "ve",           "pll-ve",
 475                       0x13c, BIT(31), CLK_SET_RATE_PARENT);
 476
 477 static SUNXI_CCU_GATE(codec_clk,        "codec",        "pll-audio",
 478                       0x140, BIT(31), CLK_SET_RATE_PARENT);
 479
 480 static SUNXI_CCU_GATE(avs_clk,          "avs",          "hosc",
 481                       0x144, BIT(31), 0);
 482
 483 static const char * const hdmi_parents[] = { "pll-video0", "pll-video0-2x" };
 484 static const u8 hdmi_table[] = { 0, 2 };
 485 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(hdmi_clk, "hdmi",
 486                                        hdmi_parents, hdmi_table,
 487                                        0x150, 0, 4, 24, 2, BIT(31),
 488                                        CLK_SET_RATE_PARENT);
 489
 490 static const char * const gpu_parents[] = { "pll-video0", "pll-ve",
 491                                             "pll-ddr-other", "pll-video1",
 492                                             "pll-video1-2x" };
 493 static SUNXI_CCU_M_WITH_MUX_GATE(gpu_clk, "gpu", gpu_parents,
 494                                  0x154, 0, 4, 24, 3, BIT(31), 0);
 495
 496 static const char * const mbus_parents[] = { "hosc", "pll-periph", "pll-ddr" };
 497 static SUNXI_CCU_MP_WITH_MUX_GATE(mbus_clk, "mbus", mbus_parents,
 498                                   0x15c, 0, 4, 16, 2, 24, 2, BIT(31), CLK_IS_CRITICAL);
 499
 500 static SUNXI_CCU_GATE(iep_clk,          "iep",          "de-be",
 501                       0x160, BIT(31), 0);
 502
 503 static struct ccu_common *sun5i_a10s_ccu_clks[] = {
 504         &hosc_clk.common,
 505         &pll_core_clk.common,
 506         &pll_audio_base_clk.common,
 507         &pll_video0_clk.common,
 508         &pll_ve_clk.common,
 509         &pll_ddr_base_clk.common,
 510         &pll_ddr_clk.common,
 511         &pll_ddr_other_clk.common,
 512         &pll_periph_clk.common,
 513         &pll_video1_clk.common,
 514         &cpu_clk.common,
 515         &axi_clk.common,
 516         &ahb_clk.common,
 517         &apb0_clk.common,
 518         &apb1_clk.common,
 519         &axi_dram_clk.common,
 520         &ahb_otg_clk.common,
 521         &ahb_ehci_clk.common,
 522         &ahb_ohci_clk.common,
 523         &ahb_ss_clk.common,
 524         &ahb_dma_clk.common,
 525         &ahb_bist_clk.common,
 526         &ahb_mmc0_clk.common,
 527         &ahb_mmc1_clk.common,
 528         &ahb_mmc2_clk.common,
 529         &ahb_nand_clk.common,
 530         &ahb_sdram_clk.common,
 531         &ahb_emac_clk.common,
 532         &ahb_ts_clk.common,
 533         &ahb_spi0_clk.common,
 534         &ahb_spi1_clk.common,
 535         &ahb_spi2_clk.common,
 536         &ahb_gps_clk.common,
 537         &ahb_hstimer_clk.common,
 538         &ahb_ve_clk.common,
 539         &ahb_tve_clk.common,
 540         &ahb_lcd_clk.common,
 541         &ahb_csi_clk.common,
 542         &ahb_hdmi_clk.common,
 543         &ahb_de_be_clk.common,
 544         &ahb_de_fe_clk.common,
 545         &ahb_iep_clk.common,
 546         &ahb_gpu_clk.common,
 547         &apb0_codec_clk.common,
 548         &apb0_spdif_clk.common,
 549         &apb0_i2s_clk.common,
 550         &apb0_pio_clk.common,
 551         &apb0_ir_clk.common,
 552         &apb0_keypad_clk.common,
 553         &apb1_i2c0_clk.common,
 554         &apb1_i2c1_clk.common,
 555         &apb1_i2c2_clk.common,
 556         &apb1_uart0_clk.common,
 557         &apb1_uart1_clk.common,
 558         &apb1_uart2_clk.common,
 559         &apb1_uart3_clk.common,
 560         &nand_clk.common,
 561         &mmc0_clk.common,
 562         &mmc1_clk.common,
 563         &mmc2_clk.common,
 564         &ts_clk.common,
 565         &ss_clk.common,
 566         &spi0_clk.common,
 567         &spi1_clk.common,
 568         &spi2_clk.common,
 569         &ir_clk.common,
 570         &i2s_clk.common,
 571         &spdif_clk.common,
 572         &keypad_clk.common,
 573         &usb_ohci_clk.common,
 574         &usb_phy0_clk.common,
 575         &usb_phy1_clk.common,
 576         &gps_clk.common,
 577         &dram_ve_clk.common,
 578         &dram_csi_clk.common,
 579         &dram_ts_clk.common,
 580         &dram_tve_clk.common,
 581         &dram_de_fe_clk.common,
 582         &dram_de_be_clk.common,
 583         &dram_ace_clk.common,
 584         &dram_iep_clk.common,
 585         &de_be_clk.common,
 586         &de_fe_clk.common,
 587         &tcon_ch0_clk.common,
 588         &tcon_ch1_sclk2_clk.common,
 589         &tcon_ch1_sclk1_clk.common,
 590         &csi_clk.common,
 591         &ve_clk.common,
 592         &codec_clk.common,
 593         &avs_clk.common,
 594         &hdmi_clk.common,
 595         &gpu_clk.common,
 596         &mbus_clk.common,
 597         &iep_clk.common,
 598 };
 599
 600 /* We hardcode the divider to 4 for now */
 601 static CLK_FIXED_FACTOR(pll_audio_clk, "pll-audio",
 602                         "pll-audio-base", 4, 1, CLK_SET_RATE_PARENT);
 603 static CLK_FIXED_FACTOR(pll_audio_2x_clk, "pll-audio-2x",
 604                         "pll-audio-base", 2, 1, CLK_SET_RATE_PARENT);
 605 static CLK_FIXED_FACTOR(pll_audio_4x_clk, "pll-audio-4x",
 606                         "pll-audio-base", 1, 1, CLK_SET_RATE_PARENT);
 607 static CLK_FIXED_FACTOR(pll_audio_8x_clk, "pll-audio-8x",
 608                         "pll-audio-base", 1, 2, CLK_SET_RATE_PARENT);
 609 static CLK_FIXED_FACTOR(pll_video0_2x_clk, "pll-video0-2x",
 610                         "pll-video0", 1, 2, CLK_SET_RATE_PARENT);
 611 static CLK_FIXED_FACTOR(pll_video1_2x_clk, "pll-video1-2x",
 612                         "pll-video1", 1, 2, CLK_SET_RATE_PARENT);
 613
 614 static struct clk_hw_onecell_data sun5i_a10s_hw_clks = {
 615         .hws    = {
 616                 [CLK_HOSC]              = &hosc_clk.common.hw,
 617                 [CLK_PLL_CORE]          = &pll_core_clk.common.hw,
 618                 [CLK_PLL_AUDIO_BASE]    = &pll_audio_base_clk.common.hw,
 619                 [CLK_PLL_AUDIO]         = &pll_audio_clk.hw,
 620                 [CLK_PLL_AUDIO_2X]      = &pll_audio_2x_clk.hw,
 621                 [CLK_PLL_AUDIO_4X]      = &pll_audio_4x_clk.hw,
 622                 [CLK_PLL_AUDIO_8X]      = &pll_audio_8x_clk.hw,
 623                 [CLK_PLL_VIDEO0]        = &pll_video0_clk.common.hw,
 624                 [CLK_PLL_VIDEO0_2X]     = &pll_video0_2x_clk.hw,
 625                 [CLK_PLL_VE]            = &pll_ve_clk.common.hw,
 626                 [CLK_PLL_DDR_BASE]      = &pll_ddr_base_clk.common.hw,
 627                 [CLK_PLL_DDR]           = &pll_ddr_clk.common.hw,
 628                 [CLK_PLL_DDR_OTHER]     = &pll_ddr_other_clk.common.hw,
 629                 [CLK_PLL_PERIPH]        = &pll_periph_clk.common.hw,
 630                 [CLK_PLL_VIDEO1]        = &pll_video1_clk.common.hw,
 631                 [CLK_PLL_VIDEO1_2X]     = &pll_video1_2x_clk.hw,
 632                 [CLK_CPU]               = &cpu_clk.common.hw,
 633                 [CLK_AXI]               = &axi_clk.common.hw,
 634                 [CLK_AHB]               = &ahb_clk.common.hw,
 635                 [CLK_APB0]              = &apb0_clk.common.hw,
 636                 [CLK_APB1]              = &apb1_clk.common.hw,
 637                 [CLK_DRAM_AXI]          = &axi_dram_clk.common.hw,
 638                 [CLK_AHB_OTG]           = &ahb_otg_clk.common.hw,
 639                 [CLK_AHB_EHCI]          = &ahb_ehci_clk.common.hw,
 640                 [CLK_AHB_OHCI]          = &ahb_ohci_clk.common.hw,
 641                 [CLK_AHB_SS]            = &ahb_ss_clk.common.hw,
 642                 [CLK_AHB_DMA]           = &ahb_dma_clk.common.hw,
 643                 [CLK_AHB_BIST]          = &ahb_bist_clk.common.hw,
 644                 [CLK_AHB_MMC0]          = &ahb_mmc0_clk.common.hw,
 645                 [CLK_AHB_MMC1]          = &ahb_mmc1_clk.common.hw,
 646                 [CLK_AHB_MMC2]          = &ahb_mmc2_clk.common.hw,
 647                 [CLK_AHB_NAND]          = &ahb_nand_clk.common.hw,
 648                 [CLK_AHB_SDRAM]         = &ahb_sdram_clk.common.hw,
 649                 [CLK_AHB_EMAC]          = &ahb_emac_clk.common.hw,
 650                 [CLK_AHB_TS]            = &ahb_ts_clk.common.hw,
 651                 [CLK_AHB_SPI0]          = &ahb_spi0_clk.common.hw,
 652                 [CLK_AHB_SPI1]          = &ahb_spi1_clk.common.hw,
 653                 [CLK_AHB_SPI2]          = &ahb_spi2_clk.common.hw,
 654                 [CLK_AHB_GPS]           = &ahb_gps_clk.common.hw,
 655                 [CLK_AHB_HSTIMER]       = &ahb_hstimer_clk.common.hw,
 656                 [CLK_AHB_VE]            = &ahb_ve_clk.common.hw,
 657                 [CLK_AHB_TVE]           = &ahb_tve_clk.common.hw,
 658                 [CLK_AHB_LCD]           = &ahb_lcd_clk.common.hw,
 659                 [CLK_AHB_CSI]           = &ahb_csi_clk.common.hw,
 660                 [CLK_AHB_HDMI]          = &ahb_hdmi_clk.common.hw,
 661                 [CLK_AHB_DE_BE]         = &ahb_de_be_clk.common.hw,
 662                 [CLK_AHB_DE_FE]         = &ahb_de_fe_clk.common.hw,
 663                 [CLK_AHB_IEP]           = &ahb_iep_clk.common.hw,
 664                 [CLK_AHB_GPU]           = &ahb_gpu_clk.common.hw,
 665                 [CLK_APB0_CODEC]        = &apb0_codec_clk.common.hw,
 666                 [CLK_APB0_I2S]          = &apb0_i2s_clk.common.hw,
 667                 [CLK_APB0_PIO]          = &apb0_pio_clk.common.hw,
 668                 [CLK_APB0_IR]           = &apb0_ir_clk.common.hw,
 669                 [CLK_APB0_KEYPAD]       = &apb0_keypad_clk.common.hw,
 670                 [CLK_APB1_I2C0]         = &apb1_i2c0_clk.common.hw,
 671                 [CLK_APB1_I2C1]         = &apb1_i2c1_clk.common.hw,
 672                 [CLK_APB1_I2C2]         = &apb1_i2c2_clk.common.hw,
 673                 [CLK_APB1_UART0]        = &apb1_uart0_clk.common.hw,
 674                 [CLK_APB1_UART1]        = &apb1_uart1_clk.common.hw,
 675                 [CLK_APB1_UART2]        = &apb1_uart2_clk.common.hw,
 676                 [CLK_APB1_UART3]        = &apb1_uart3_clk.common.hw,
 677                 [CLK_NAND]              = &nand_clk.common.hw,
 678                 [CLK_MMC0]              = &mmc0_clk.common.hw,
 679                 [CLK_MMC1]              = &mmc1_clk.common.hw,
 680                 [CLK_MMC2]              = &mmc2_clk.common.hw,
 681                 [CLK_TS]                = &ts_clk.common.hw,
 682                 [CLK_SS]                = &ss_clk.common.hw,
 683                 [CLK_SPI0]              = &spi0_clk.common.hw,
 684                 [CLK_SPI1]              = &spi1_clk.common.hw,
 685                 [CLK_SPI2]              = &spi2_clk.common.hw,
 686                 [CLK_IR]                = &ir_clk.common.hw,
 687                 [CLK_I2S]               = &i2s_clk.common.hw,
 688                 [CLK_KEYPAD]            = &keypad_clk.common.hw,
 689                 [CLK_USB_OHCI]          = &usb_ohci_clk.common.hw,
 690                 [CLK_USB_PHY0]          = &usb_phy0_clk.common.hw,
 691                 [CLK_USB_PHY1]          = &usb_phy1_clk.common.hw,
 692                 [CLK_GPS]               = &gps_clk.common.hw,
 693                 [CLK_DRAM_VE]           = &dram_ve_clk.common.hw,
 694                 [CLK_DRAM_CSI]          = &dram_csi_clk.common.hw,
 695                 [CLK_DRAM_TS]           = &dram_ts_clk.common.hw,
 696                 [CLK_DRAM_TVE]          = &dram_tve_clk.common.hw,
 697                 [CLK_DRAM_DE_FE]        = &dram_de_fe_clk.common.hw,
 698                 [CLK_DRAM_DE_BE]        = &dram_de_be_clk.common.hw,
 699                 [CLK_DRAM_ACE]          = &dram_ace_clk.common.hw,
 700                 [CLK_DRAM_IEP]          = &dram_iep_clk.common.hw,
 701                 [CLK_DE_BE]             = &de_be_clk.common.hw,
 702                 [CLK_DE_FE]             = &de_fe_clk.common.hw,
 703                 [CLK_TCON_CH0]          = &tcon_ch0_clk.common.hw,
 704                 [CLK_TCON_CH1_SCLK]     = &tcon_ch1_sclk2_clk.common.hw,
 705                 [CLK_TCON_CH1]          = &tcon_ch1_sclk1_clk.common.hw,
 706                 [CLK_CSI]               = &csi_clk.common.hw,
 707                 [CLK_VE]                = &ve_clk.common.hw,
 708                 [CLK_CODEC]             = &codec_clk.common.hw,
 709                 [CLK_AVS]               = &avs_clk.common.hw,
 710                 [CLK_HDMI]              = &hdmi_clk.common.hw,
 711                 [CLK_GPU]               = &gpu_clk.common.hw,
 712                 [CLK_MBUS]              = &mbus_clk.common.hw,
 713                 [CLK_IEP]               = &iep_clk.common.hw,
 714         },
 715         .num    = CLK_NUMBER,
 716 };
 717
 718 static struct ccu_reset_map sun5i_a10s_ccu_resets[] = {
 719         [RST_USB_PHY0]          =  { 0x0cc, BIT(0) },
 720         [RST_USB_PHY1]          =  { 0x0cc, BIT(1) },
 721
 722         [RST_GPS]               =  { 0x0d0, BIT(30) },
 723
 724         [RST_DE_BE]             =  { 0x104, BIT(30) },
 725
 726         [RST_DE_FE]             =  { 0x10c, BIT(30) },
 727
 728         [RST_TVE]               =  { 0x118, BIT(29) },
 729         [RST_LCD]               =  { 0x118, BIT(30) },
 730
 731         [RST_CSI]               =  { 0x134, BIT(30) },
 732
 733         [RST_VE]                =  { 0x13c, BIT(0) },
 734
 735         [RST_GPU]               =  { 0x154, BIT(30) },
 736
 737         [RST_IEP]               =  { 0x160, BIT(30) },
 738 };
 739
 740 static const struct sunxi_ccu_desc sun5i_a10s_ccu_desc = {
 741         .ccu_clks       = sun5i_a10s_ccu_clks,
 742         .num_ccu_clks   = ARRAY_SIZE(sun5i_a10s_ccu_clks),
 743
 744         .hw_clks        = &sun5i_a10s_hw_clks,
 745
 746         .resets         = sun5i_a10s_ccu_resets,
 747         .num_resets     = ARRAY_SIZE(sun5i_a10s_ccu_resets),
 748 };
 749
 750 /*
 751  * The A13 is the A10s minus the TS, GPS, HDMI, I2S and the keypad
 752  */
 753 static struct clk_hw_onecell_data sun5i_a13_hw_clks = {
 754         .hws    = {
 755                 [CLK_HOSC]              = &hosc_clk.common.hw,
 756                 [CLK_PLL_CORE]          = &pll_core_clk.common.hw,
 757                 [CLK_PLL_AUDIO_BASE]    = &pll_audio_base_clk.common.hw,
 758                 [CLK_PLL_AUDIO]         = &pll_audio_clk.hw,
 759                 [CLK_PLL_AUDIO_2X]      = &pll_audio_2x_clk.hw,
 760                 [CLK_PLL_AUDIO_4X]      = &pll_audio_4x_clk.hw,
 761                 [CLK_PLL_AUDIO_8X]      = &pll_audio_8x_clk.hw,
 762                 [CLK_PLL_VIDEO0]        = &pll_video0_clk.common.hw,
 763                 [CLK_PLL_VIDEO0_2X]     = &pll_video0_2x_clk.hw,
 764                 [CLK_PLL_VE]            = &pll_ve_clk.common.hw,
 765                 [CLK_PLL_DDR_BASE]      = &pll_ddr_base_clk.common.hw,
 766                 [CLK_PLL_DDR]           = &pll_ddr_clk.common.hw,
 767                 [CLK_PLL_DDR_OTHER]     = &pll_ddr_other_clk.common.hw,
 768                 [CLK_PLL_PERIPH]        = &pll_periph_clk.common.hw,
 769                 [CLK_PLL_VIDEO1]        = &pll_video1_clk.common.hw,
 770                 [CLK_PLL_VIDEO1_2X]     = &pll_video1_2x_clk.hw,
 771                 [CLK_CPU]               = &cpu_clk.common.hw,
 772                 [CLK_AXI]               = &axi_clk.common.hw,
 773                 [CLK_AHB]               = &ahb_clk.common.hw,
 774                 [CLK_APB0]              = &apb0_clk.common.hw,
 775                 [CLK_APB1]              = &apb1_clk.common.hw,
 776                 [CLK_DRAM_AXI]          = &axi_dram_clk.common.hw,
 777                 [CLK_AHB_OTG]           = &ahb_otg_clk.common.hw,
 778                 [CLK_AHB_EHCI]          = &ahb_ehci_clk.common.hw,
 779                 [CLK_AHB_OHCI]          = &ahb_ohci_clk.common.hw,
 780                 [CLK_AHB_SS]            = &ahb_ss_clk.common.hw,
 781                 [CLK_AHB_DMA]           = &ahb_dma_clk.common.hw,
 782                 [CLK_AHB_BIST]          = &ahb_bist_clk.common.hw,
 783                 [CLK_AHB_MMC0]          = &ahb_mmc0_clk.common.hw,
 784                 [CLK_AHB_MMC1]          = &ahb_mmc1_clk.common.hw,
 785                 [CLK_AHB_MMC2]          = &ahb_mmc2_clk.common.hw,
 786                 [CLK_AHB_NAND]          = &ahb_nand_clk.common.hw,
 787                 [CLK_AHB_SDRAM]         = &ahb_sdram_clk.common.hw,
 788                 [CLK_AHB_EMAC]          = &ahb_emac_clk.common.hw,
 789                 [CLK_AHB_SPI0]          = &ahb_spi0_clk.common.hw,
 790                 [CLK_AHB_SPI1]          = &ahb_spi1_clk.common.hw,
 791                 [CLK_AHB_SPI2]          = &ahb_spi2_clk.common.hw,
 792                 [CLK_AHB_HSTIMER]       = &ahb_hstimer_clk.common.hw,
 793                 [CLK_AHB_VE]            = &ahb_ve_clk.common.hw,
 794                 [CLK_AHB_TVE]           = &ahb_tve_clk.common.hw,
 795                 [CLK_AHB_LCD]           = &ahb_lcd_clk.common.hw,
 796                 [CLK_AHB_CSI]           = &ahb_csi_clk.common.hw,
 797                 [CLK_AHB_DE_BE]         = &ahb_de_be_clk.common.hw,
 798                 [CLK_AHB_DE_FE]         = &ahb_de_fe_clk.common.hw,
 799                 [CLK_AHB_IEP]           = &ahb_iep_clk.common.hw,
 800                 [CLK_AHB_GPU]           = &ahb_gpu_clk.common.hw,
 801                 [CLK_APB0_CODEC]        = &apb0_codec_clk.common.hw,
 802                 [CLK_APB0_PIO]          = &apb0_pio_clk.common.hw,
 803                 [CLK_APB0_IR]           = &apb0_ir_clk.common.hw,
 804                 [CLK_APB1_I2C0]         = &apb1_i2c0_clk.common.hw,
 805                 [CLK_APB1_I2C1]         = &apb1_i2c1_clk.common.hw,
 806                 [CLK_APB1_I2C2]         = &apb1_i2c2_clk.common.hw,
 807                 [CLK_APB1_UART0]        = &apb1_uart0_clk.common.hw,
 808                 [CLK_APB1_UART1]        = &apb1_uart1_clk.common.hw,
 809                 [CLK_APB1_UART2]        = &apb1_uart2_clk.common.hw,
 810                 [CLK_APB1_UART3]        = &apb1_uart3_clk.common.hw,
 811                 [CLK_NAND]              = &nand_clk.common.hw,
 812                 [CLK_MMC0]              = &mmc0_clk.common.hw,
 813                 [CLK_MMC1]              = &mmc1_clk.common.hw,
 814                 [CLK_MMC2]              = &mmc2_clk.common.hw,
 815                 [CLK_SS]                = &ss_clk.common.hw,
 816                 [CLK_SPI0]              = &spi0_clk.common.hw,
 817                 [CLK_SPI1]              = &spi1_clk.common.hw,
 818                 [CLK_SPI2]              = &spi2_clk.common.hw,
 819                 [CLK_IR]                = &ir_clk.common.hw,
 820                 [CLK_USB_OHCI]          = &usb_ohci_clk.common.hw,
 821                 [CLK_USB_PHY0]          = &usb_phy0_clk.common.hw,
 822                 [CLK_USB_PHY1]          = &usb_phy1_clk.common.hw,
 823                 [CLK_DRAM_VE]           = &dram_ve_clk.common.hw,
 824                 [CLK_DRAM_CSI]          = &dram_csi_clk.common.hw,
 825                 [CLK_DRAM_TVE]          = &dram_tve_clk.common.hw,
 826                 [CLK_DRAM_DE_FE]        = &dram_de_fe_clk.common.hw,
 827                 [CLK_DRAM_DE_BE]        = &dram_de_be_clk.common.hw,
 828                 [CLK_DRAM_ACE]          = &dram_ace_clk.common.hw,
 829                 [CLK_DRAM_IEP]          = &dram_iep_clk.common.hw,
 830                 [CLK_DE_BE]             = &de_be_clk.common.hw,
 831                 [CLK_DE_FE]             = &de_fe_clk.common.hw,
 832                 [CLK_TCON_CH0]          = &tcon_ch0_clk.common.hw,
 833                 [CLK_TCON_CH1_SCLK]     = &tcon_ch1_sclk2_clk.common.hw,
 834                 [CLK_TCON_CH1]          = &tcon_ch1_sclk1_clk.common.hw,
 835                 [CLK_CSI]               = &csi_clk.common.hw,
 836                 [CLK_VE]                = &ve_clk.common.hw,
 837                 [CLK_CODEC]             = &codec_clk.common.hw,
 838                 [CLK_AVS]               = &avs_clk.common.hw,
 839                 [CLK_GPU]               = &gpu_clk.common.hw,
 840                 [CLK_MBUS]              = &mbus_clk.common.hw,
 841                 [CLK_IEP]               = &iep_clk.common.hw,
 842         },
 843         .num    = CLK_NUMBER,
 844 };
 845
 846 static const struct sunxi_ccu_desc sun5i_a13_ccu_desc = {
 847         .ccu_clks       = sun5i_a10s_ccu_clks,
 848         .num_ccu_clks   = ARRAY_SIZE(sun5i_a10s_ccu_clks),
 849
 850         .hw_clks        = &sun5i_a13_hw_clks,
 851
 852         .resets         = sun5i_a10s_ccu_resets,
 853         .num_resets     = ARRAY_SIZE(sun5i_a10s_ccu_resets),
 854 };
 855
 856 /*
 857  * The GR8 is the A10s CCU minus the HDMI and keypad, plus SPDIF
 858  */
 859 static struct clk_hw_onecell_data sun5i_gr8_hw_clks = {
 860         .hws    = {
 861                 [CLK_HOSC]              = &hosc_clk.common.hw,
 862                 [CLK_PLL_CORE]          = &pll_core_clk.common.hw,
 863                 [CLK_PLL_AUDIO_BASE]    = &pll_audio_base_clk.common.hw,
 864                 [CLK_PLL_AUDIO]         = &pll_audio_clk.hw,
 865                 [CLK_PLL_AUDIO_2X]      = &pll_audio_2x_clk.hw,
 866                 [CLK_PLL_AUDIO_4X]      = &pll_audio_4x_clk.hw,
 867                 [CLK_PLL_AUDIO_8X]      = &pll_audio_8x_clk.hw,
 868                 [CLK_PLL_VIDEO0]        = &pll_video0_clk.common.hw,
 869                 [CLK_PLL_VIDEO0_2X]     = &pll_video0_2x_clk.hw,
 870                 [CLK_PLL_VE]            = &pll_ve_clk.common.hw,
 871                 [CLK_PLL_DDR_BASE]      = &pll_ddr_base_clk.common.hw,
 872                 [CLK_PLL_DDR]           = &pll_ddr_clk.common.hw,
 873                 [CLK_PLL_DDR_OTHER]     = &pll_ddr_other_clk.common.hw,
 874                 [CLK_PLL_PERIPH]        = &pll_periph_clk.common.hw,
 875                 [CLK_PLL_VIDEO1]        = &pll_video1_clk.common.hw,
 876                 [CLK_PLL_VIDEO1_2X]     = &pll_video1_2x_clk.hw,
 877                 [CLK_CPU]               = &cpu_clk.common.hw,
 878                 [CLK_AXI]               = &axi_clk.common.hw,
 879                 [CLK_AHB]               = &ahb_clk.common.hw,
 880                 [CLK_APB0]              = &apb0_clk.common.hw,
 881                 [CLK_APB1]              = &apb1_clk.common.hw,
 882                 [CLK_DRAM_AXI]          = &axi_dram_clk.common.hw,
 883                 [CLK_AHB_OTG]           = &ahb_otg_clk.common.hw,
 884                 [CLK_AHB_EHCI]          = &ahb_ehci_clk.common.hw,
 885                 [CLK_AHB_OHCI]          = &ahb_ohci_clk.common.hw,
 886                 [CLK_AHB_SS]            = &ahb_ss_clk.common.hw,
 887                 [CLK_AHB_DMA]           = &ahb_dma_clk.common.hw,
 888                 [CLK_AHB_BIST]          = &ahb_bist_clk.common.hw,
 889                 [CLK_AHB_MMC0]          = &ahb_mmc0_clk.common.hw,
 890                 [CLK_AHB_MMC1]          = &ahb_mmc1_clk.common.hw,
 891                 [CLK_AHB_MMC2]          = &ahb_mmc2_clk.common.hw,
 892                 [CLK_AHB_NAND]          = &ahb_nand_clk.common.hw,
 893                 [CLK_AHB_SDRAM]         = &ahb_sdram_clk.common.hw,
 894                 [CLK_AHB_EMAC]          = &ahb_emac_clk.common.hw,
 895                 [CLK_AHB_TS]            = &ahb_ts_clk.common.hw,
 896                 [CLK_AHB_SPI0]          = &ahb_spi0_clk.common.hw,
 897                 [CLK_AHB_SPI1]          = &ahb_spi1_clk.common.hw,
 898                 [CLK_AHB_SPI2]          = &ahb_spi2_clk.common.hw,
 899                 [CLK_AHB_GPS]           = &ahb_gps_clk.common.hw,
 900                 [CLK_AHB_HSTIMER]       = &ahb_hstimer_clk.common.hw,
 901                 [CLK_AHB_VE]            = &ahb_ve_clk.common.hw,
 902                 [CLK_AHB_TVE]           = &ahb_tve_clk.common.hw,
 903                 [CLK_AHB_LCD]           = &ahb_lcd_clk.common.hw,
 904                 [CLK_AHB_CSI]           = &ahb_csi_clk.common.hw,
 905                 [CLK_AHB_DE_BE]         = &ahb_de_be_clk.common.hw,
 906                 [CLK_AHB_DE_FE]         = &ahb_de_fe_clk.common.hw,
 907                 [CLK_AHB_IEP]           = &ahb_iep_clk.common.hw,
 908                 [CLK_AHB_GPU]           = &ahb_gpu_clk.common.hw,
 909                 [CLK_APB0_CODEC]        = &apb0_codec_clk.common.hw,
 910                 [CLK_APB0_SPDIF]        = &apb0_spdif_clk.common.hw,
 911                 [CLK_APB0_I2S]          = &apb0_i2s_clk.common.hw,
 912                 [CLK_APB0_PIO]          = &apb0_pio_clk.common.hw,
 913                 [CLK_APB0_IR]           = &apb0_ir_clk.common.hw,
 914                 [CLK_APB1_I2C0]         = &apb1_i2c0_clk.common.hw,
 915                 [CLK_APB1_I2C1]         = &apb1_i2c1_clk.common.hw,
 916                 [CLK_APB1_I2C2]         = &apb1_i2c2_clk.common.hw,
 917                 [CLK_APB1_UART0]        = &apb1_uart0_clk.common.hw,
 918                 [CLK_APB1_UART1]        = &apb1_uart1_clk.common.hw,
 919                 [CLK_APB1_UART2]        = &apb1_uart2_clk.common.hw,
 920                 [CLK_APB1_UART3]        = &apb1_uart3_clk.common.hw,
 921                 [CLK_NAND]              = &nand_clk.common.hw,
 922                 [CLK_MMC0]              = &mmc0_clk.common.hw,
 923                 [CLK_MMC1]              = &mmc1_clk.common.hw,
 924                 [CLK_MMC2]              = &mmc2_clk.common.hw,
 925                 [CLK_TS]                = &ts_clk.common.hw,
 926                 [CLK_SS]                = &ss_clk.common.hw,
 927                 [CLK_SPI0]              = &spi0_clk.common.hw,
 928                 [CLK_SPI1]              = &spi1_clk.common.hw,
 929                 [CLK_SPI2]              = &spi2_clk.common.hw,
 930                 [CLK_IR]                = &ir_clk.common.hw,
 931                 [CLK_I2S]               = &i2s_clk.common.hw,
 932                 [CLK_SPDIF]             = &spdif_clk.common.hw,
 933                 [CLK_USB_OHCI]          = &usb_ohci_clk.common.hw,
 934                 [CLK_USB_PHY0]          = &usb_phy0_clk.common.hw,
 935                 [CLK_USB_PHY1]          = &usb_phy1_clk.common.hw,
 936                 [CLK_GPS]               = &gps_clk.common.hw,
 937                 [CLK_DRAM_VE]           = &dram_ve_clk.common.hw,
 938                 [CLK_DRAM_CSI]          = &dram_csi_clk.common.hw,
 939                 [CLK_DRAM_TS]           = &dram_ts_clk.common.hw,
 940                 [CLK_DRAM_TVE]          = &dram_tve_clk.common.hw,
 941                 [CLK_DRAM_DE_FE]        = &dram_de_fe_clk.common.hw,
 942                 [CLK_DRAM_DE_BE]        = &dram_de_be_clk.common.hw,
 943                 [CLK_DRAM_ACE]          = &dram_ace_clk.common.hw,
 944                 [CLK_DRAM_IEP]          = &dram_iep_clk.common.hw,
 945                 [CLK_DE_BE]             = &de_be_clk.common.hw,
 946                 [CLK_DE_FE]             = &de_fe_clk.common.hw,
 947                 [CLK_TCON_CH0]          = &tcon_ch0_clk.common.hw,
 948                 [CLK_TCON_CH1_SCLK]     = &tcon_ch1_sclk2_clk.common.hw,
 949                 [CLK_TCON_CH1]          = &tcon_ch1_sclk1_clk.common.hw,
 950                 [CLK_CSI]               = &csi_clk.common.hw,
 951                 [CLK_VE]                = &ve_clk.common.hw,
 952                 [CLK_CODEC]             = &codec_clk.common.hw,
 953                 [CLK_AVS]               = &avs_clk.common.hw,
 954                 [CLK_GPU]               = &gpu_clk.common.hw,
 955                 [CLK_MBUS]              = &mbus_clk.common.hw,
 956                 [CLK_IEP]               = &iep_clk.common.hw,
 957         },
 958         .num    = CLK_NUMBER,
 959 };
 960
 961 static const struct sunxi_ccu_desc sun5i_gr8_ccu_desc = {
 962         .ccu_clks       = sun5i_a10s_ccu_clks,
 963         .num_ccu_clks   = ARRAY_SIZE(sun5i_a10s_ccu_clks),
 964
 965         .hw_clks        = &sun5i_gr8_hw_clks,
 966
 967         .resets         = sun5i_a10s_ccu_resets,
 968         .num_resets     = ARRAY_SIZE(sun5i_a10s_ccu_resets),
 969 };
 970
 971 static void __init sun5i_ccu_init(struct device_node *node,
 972                                   const struct sunxi_ccu_desc *desc)
 973 {
 974         void __iomem *reg;
 975         u32 val;
 976
 977         reg = of_io_request_and_map(node, 0, of_node_full_name(node));
 978         if (IS_ERR(reg)) {
 979                 pr_err("%s: Could not map the clock registers\n",
 980                        of_node_full_name(node));
 981                 return;
 982         }
 983
 984         /* Force the PLL-Audio-1x divider to 4 */
 985         val = readl(reg + SUN5I_PLL_AUDIO_REG);
 986         val &= ~GENMASK(19, 16);
 987         writel(val | (3 << 16), reg + SUN5I_PLL_AUDIO_REG);
 988
 989         /*
 990          * Use the peripheral PLL as the AHB parent, instead of CPU /
 991          * AXI which have rate changes due to cpufreq.
 992          *
 993          * This is especially a big deal for the HS timer whose parent
 994          * clock is AHB.
 995          */
 996         val = readl(reg + SUN5I_AHB_REG);
 997         val &= ~GENMASK(7, 6);
 998         writel(val | (2 << 6), reg + SUN5I_AHB_REG);
 999
1000         sunxi_ccu_probe(node, reg, desc);
1001 }
1002
1003 static void __init sun5i_a10s_ccu_setup(struct device_node *node)
1004 {
1005         sun5i_ccu_init(node, &sun5i_a10s_ccu_desc);
1006 }
1007 CLK_OF_DECLARE(sun5i_a10s_ccu, "allwinner,sun5i-a10s-ccu",
1008                sun5i_a10s_ccu_setup);
1009
1010 static void __init sun5i_a13_ccu_setup(struct device_node *node)
1011 {
1012         sun5i_ccu_init(node, &sun5i_a13_ccu_desc);
1013 }
1014 CLK_OF_DECLARE(sun5i_a13_ccu, "allwinner,sun5i-a13-ccu",
1015                sun5i_a13_ccu_setup);
1016
1017 static void __init sun5i_gr8_ccu_setup(struct device_node *node)
1018 {
1019         sun5i_ccu_init(node, &sun5i_gr8_ccu_desc);
1020 }
1021 CLK_OF_DECLARE(sun5i_gr8_ccu, "nextthing,gr8-ccu",
1022                sun5i_gr8_ccu_setup);