drivers/clk/sunxi-ng/ccu-sun20i-d1.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (c) 2020 huangzhenwei@allwinnertech.com
   4  * Copyright (C) 2021 Samuel Holland <samuel@sholland.org>
   5  */
   6
   7 #include <linux/clk-provider.h>
   8 #include <linux/io.h>
   9 #include <linux/module.h>
  10 #include <linux/platform_device.h>
  11
  12 #include "../clk.h"
  13
  14 #include "ccu_common.h"
  15 #include "ccu_reset.h"
  16
  17 #include "ccu_div.h"
  18 #include "ccu_gate.h"
  19 #include "ccu_mp.h"
  20 #include "ccu_mult.h"
  21 #include "ccu_nk.h"
  22 #include "ccu_nkm.h"
  23 #include "ccu_nkmp.h"
  24 #include "ccu_nm.h"
  25
  26 #include "ccu-sun20i-d1.h"
  27
  28 static const struct clk_parent_data osc24M[] = {
  29         { .fw_name = "hosc" }
  30 };
  31
  32 /*
  33  * For the CPU PLL, the output divider is described as "only for testing"
  34  * in the user manual. So it's not modelled and forced to 0.
  35  */
  36 #define SUN20I_D1_PLL_CPUX_REG          0x000
  37 static struct ccu_mult pll_cpux_clk = {
  38         .enable         = BIT(27),
  39         .lock           = BIT(28),
  40         .mult           = _SUNXI_CCU_MULT_MIN(8, 8, 12),
  41         .common         = {
  42                 .reg            = 0x000,
  43                 .hw.init        = CLK_HW_INIT_PARENTS_DATA("pll-cpux", osc24M,
  44                                                            &ccu_mult_ops,
  45                                                            CLK_SET_RATE_UNGATE),
  46         },
  47 };
  48
  49 /* Some PLLs are input * N / div1 / P. Model them as NKMP with no K */
  50 #define SUN20I_D1_PLL_DDR0_REG          0x010
  51 static struct ccu_nkmp pll_ddr0_clk = {
  52         .enable         = BIT(27),
  53         .lock           = BIT(28),
  54         .n              = _SUNXI_CCU_MULT_MIN(8, 8, 12),
  55         .m              = _SUNXI_CCU_DIV(1, 1), /* input divider */
  56         .p              = _SUNXI_CCU_DIV(0, 1), /* output divider */
  57         .common         = {
  58                 .reg            = 0x010,
  59                 .hw.init        = CLK_HW_INIT_PARENTS_DATA("pll-ddr0", osc24M,
  60                                                            &ccu_nkmp_ops,
  61                                                            CLK_SET_RATE_UNGATE),
  62         },
  63 };
  64
  65 #define SUN20I_D1_PLL_PERIPH0_REG       0x020
  66 static struct ccu_nm pll_periph0_4x_clk = {
  67         .enable         = BIT(27),
  68         .lock           = BIT(28),
  69         .n              = _SUNXI_CCU_MULT_MIN(8, 8, 12),
  70         .m              = _SUNXI_CCU_DIV(1, 1), /* input divider */
  71         .common         = {
  72                 .reg            = 0x020,
  73                 .hw.init        = CLK_HW_INIT_PARENTS_DATA("pll-periph0-4x", osc24M,
  74                                                            &ccu_nm_ops,
  75                                                            CLK_SET_RATE_UNGATE),
  76         },
  77 };
  78
  79 static const struct clk_hw *pll_periph0_4x_hws[] = {
  80         &pll_periph0_4x_clk.common.hw
  81 };
  82 static SUNXI_CCU_M_HWS(pll_periph0_2x_clk, "pll-periph0-2x",
  83                        pll_periph0_4x_hws, 0x020, 16, 3, 0);
  84 static SUNXI_CCU_M_HWS(pll_periph0_800M_clk, "pll-periph0-800M",
  85                        pll_periph0_4x_hws, 0x020, 20, 3, 0);
  86
  87 static const struct clk_hw *pll_periph0_2x_hws[] = {
  88         &pll_periph0_2x_clk.common.hw
  89 };
  90 static CLK_FIXED_FACTOR_HWS(pll_periph0_clk, "pll-periph0",
  91                             pll_periph0_2x_hws, 2, 1, 0);
  92
  93 static const struct clk_hw *pll_periph0_hws[] = { &pll_periph0_clk.hw };
  94 static CLK_FIXED_FACTOR_HWS(pll_periph0_div3_clk, "pll-periph0-div3",
  95                             pll_periph0_2x_hws, 6, 1, 0);
  96
  97 /*
  98  * For Video PLLs, the output divider is described as "only for testing"
  99  * in the user manual. So it's not modelled and forced to 0.
 100  */
 101 #define SUN20I_D1_PLL_VIDEO0_REG        0x040
 102 static struct ccu_nm pll_video0_4x_clk = {
 103         .enable         = BIT(27),
 104         .lock           = BIT(28),
 105         .n              = _SUNXI_CCU_MULT_MIN(8, 8, 12),
 106         .m              = _SUNXI_CCU_DIV(1, 1), /* input divider */
 107         .min_rate       = 252000000U,
 108         .max_rate       = 2400000000U,
 109         .common         = {
 110                 .reg            = 0x040,
 111                 .hw.init        = CLK_HW_INIT_PARENTS_DATA("pll-video0-4x", osc24M,
 112                                                            &ccu_nm_ops,
 113                                                            CLK_SET_RATE_UNGATE),
 114         },
 115 };
 116
 117 static const struct clk_hw *pll_video0_4x_hws[] = {
 118         &pll_video0_4x_clk.common.hw
 119 };
 120 static CLK_FIXED_FACTOR_HWS(pll_video0_2x_clk, "pll-video0-2x",
 121                             pll_video0_4x_hws, 2, 1, CLK_SET_RATE_PARENT);
 122 static CLK_FIXED_FACTOR_HWS(pll_video0_clk, "pll-video0",
 123                             pll_video0_4x_hws, 4, 1, CLK_SET_RATE_PARENT);
 124
 125 #define SUN20I_D1_PLL_VIDEO1_REG        0x048
 126 static struct ccu_nm pll_video1_4x_clk = {
 127         .enable         = BIT(27),
 128         .lock           = BIT(28),
 129         .n              = _SUNXI_CCU_MULT_MIN(8, 8, 12),
 130         .m              = _SUNXI_CCU_DIV(1, 1), /* input divider */
 131         .min_rate       = 252000000U,
 132         .max_rate       = 2400000000U,
 133         .common         = {
 134                 .reg            = 0x048,
 135                 .hw.init        = CLK_HW_INIT_PARENTS_DATA("pll-video1-4x", osc24M,
 136                                                            &ccu_nm_ops,
 137                                                            CLK_SET_RATE_UNGATE),
 138         },
 139 };
 140
 141 static const struct clk_hw *pll_video1_4x_hws[] = {
 142         &pll_video1_4x_clk.common.hw
 143 };
 144 static CLK_FIXED_FACTOR_HWS(pll_video1_2x_clk, "pll-video1-2x",
 145                             pll_video1_4x_hws, 2, 1, CLK_SET_RATE_PARENT);
 146 static CLK_FIXED_FACTOR_HWS(pll_video1_clk, "pll-video1",
 147                             pll_video1_4x_hws, 4, 1, CLK_SET_RATE_PARENT);
 148
 149 #define SUN20I_D1_PLL_VE_REG            0x058
 150 static struct ccu_nkmp pll_ve_clk = {
 151         .enable         = BIT(27),
 152         .lock           = BIT(28),
 153         .n              = _SUNXI_CCU_MULT_MIN(8, 8, 12),
 154         .m              = _SUNXI_CCU_DIV(1, 1), /* input divider */
 155         .p              = _SUNXI_CCU_DIV(0, 1), /* output divider */
 156         .common         = {
 157                 .reg            = 0x058,
 158                 .hw.init        = CLK_HW_INIT_PARENTS_DATA("pll-ve", osc24M,
 159                                                            &ccu_nkmp_ops,
 160                                                            CLK_SET_RATE_UNGATE),
 161         },
 162 };
 163
 164 /*
 165  * PLL_AUDIO0 has m0, m1 dividers in addition to the usual N, M factors.
 166  * Since we only need one frequency from this PLL (22.5792 x 4 == 90.3168 MHz),
 167  * ignore them for now. Enforce the default for them, which is m1 = 0, m0 = 0.
 168  * The M factor must be an even number to produce a 50% duty cycle output.
 169  */
 170 #define SUN20I_D1_PLL_AUDIO0_REG                0x078
 171 static struct ccu_sdm_setting pll_audio0_sdm_table[] = {
 172         { .rate = 90316800, .pattern = 0xc001288d, .m = 6, .n = 22 },
 173 };
 174
 175 static struct ccu_nm pll_audio0_4x_clk = {
 176         .enable         = BIT(27),
 177         .lock           = BIT(28),
 178         .n              = _SUNXI_CCU_MULT_MIN(8, 8, 12),
 179         .m              = _SUNXI_CCU_DIV(16, 6),
 180         .sdm            = _SUNXI_CCU_SDM(pll_audio0_sdm_table, BIT(24),
 181                                          0x178, BIT(31)),
 182         .min_rate       = 180000000U,
 183         .max_rate       = 3000000000U,
 184         .common         = {
 185                 .reg            = 0x078,
 186                 .features       = CCU_FEATURE_SIGMA_DELTA_MOD,
 187                 .hw.init        = CLK_HW_INIT_PARENTS_DATA("pll-audio0-4x", osc24M,
 188                                                            &ccu_nm_ops,
 189                                                            CLK_SET_RATE_UNGATE),
 190         },
 191 };
 192
 193 static const struct clk_hw *pll_audio0_4x_hws[] = {
 194         &pll_audio0_4x_clk.common.hw
 195 };
 196 static CLK_FIXED_FACTOR_HWS(pll_audio0_2x_clk, "pll-audio0-2x",
 197                             pll_audio0_4x_hws, 2, 1, 0);
 198 static CLK_FIXED_FACTOR_HWS(pll_audio0_clk, "pll-audio0",
 199                             pll_audio0_4x_hws, 4, 1, 0);
 200
 201 /*
 202  * PLL_AUDIO1 doesn't need Fractional-N. The output is usually 614.4 MHz for
 203  * audio. The ADC or DAC should divide the PLL output further to 24.576 MHz.
 204  */
 205 #define SUN20I_D1_PLL_AUDIO1_REG                0x080
 206 static struct ccu_nm pll_audio1_clk = {
 207         .enable         = BIT(27),
 208         .lock           = BIT(28),
 209         .n              = _SUNXI_CCU_MULT_MIN(8, 8, 12),
 210         .m              = _SUNXI_CCU_DIV(1, 1),
 211         .min_rate       = 180000000U,
 212         .max_rate       = 3000000000U,
 213         .common         = {
 214                 .reg            = 0x080,
 215                 .hw.init        = CLK_HW_INIT_PARENTS_DATA("pll-audio1", osc24M,
 216                                                            &ccu_nm_ops,
 217                                                            CLK_SET_RATE_UNGATE),
 218         },
 219 };
 220
 221 static const struct clk_hw *pll_audio1_hws[] = {
 222         &pll_audio1_clk.common.hw
 223 };
 224 static SUNXI_CCU_M_HWS(pll_audio1_div2_clk, "pll-audio1-div2",
 225                        pll_audio1_hws, 0x080, 16, 3, 0);
 226 static SUNXI_CCU_M_HWS(pll_audio1_div5_clk, "pll-audio1-div5",
 227                        pll_audio1_hws, 0x080, 20, 3, 0);
 228
 229 /*
 230  * The CPUX gate is not modelled - it is in a separate register (0x504)
 231  * and has a special key field. The clock does not need to be ungated anyway.
 232  */
 233 static const struct clk_parent_data cpux_parents[] = {
 234         { .fw_name = "hosc" },
 235         { .fw_name = "losc" },
 236         { .fw_name = "iosc" },
 237         { .hw = &pll_cpux_clk.common.hw },
 238         { .hw = &pll_periph0_clk.hw },
 239         { .hw = &pll_periph0_2x_clk.common.hw },
 240         { .hw = &pll_periph0_800M_clk.common.hw },
 241 };
 242 static SUNXI_CCU_MUX_DATA(cpux_clk, "cpux", cpux_parents,
 243                           0x500, 24, 3, CLK_SET_RATE_PARENT);
 244
 245 static const struct clk_hw *cpux_hws[] = { &cpux_clk.common.hw };
 246 static SUNXI_CCU_M_HWS(cpux_axi_clk, "cpux-axi",
 247                        cpux_hws, 0x500, 0, 2, 0);
 248 static SUNXI_CCU_M_HWS(cpux_apb_clk, "cpux-apb",
 249                        cpux_hws, 0x500, 8, 2, 0);
 250
 251 static const struct clk_parent_data psi_ahb_parents[] = {
 252         { .fw_name = "hosc" },
 253         { .fw_name = "losc" },
 254         { .fw_name = "iosc" },
 255         { .hw = &pll_periph0_clk.hw },
 256 };
 257 static SUNXI_CCU_MP_DATA_WITH_MUX(psi_ahb_clk, "psi-ahb", psi_ahb_parents, 0x510,
 258                                   0, 2,         /* M */
 259                                   8, 2,         /* P */
 260                                   24, 2,        /* mux */
 261                                   0);
 262
 263 static const struct clk_parent_data apb0_apb1_parents[] = {
 264         { .fw_name = "hosc" },
 265         { .fw_name = "losc" },
 266         { .hw = &psi_ahb_clk.common.hw },
 267         { .hw = &pll_periph0_clk.hw },
 268 };
 269 static SUNXI_CCU_MP_DATA_WITH_MUX(apb0_clk, "apb0", apb0_apb1_parents, 0x520,
 270                                   0, 5,         /* M */
 271                                   8, 2,         /* P */
 272                                   24, 2,        /* mux */
 273                                   0);
 274
 275 static SUNXI_CCU_MP_DATA_WITH_MUX(apb1_clk, "apb1", apb0_apb1_parents, 0x524,
 276                                   0, 5,         /* M */
 277                                   8, 2,         /* P */
 278                                   24, 2,        /* mux */
 279                                   0);
 280
 281 static const struct clk_hw *psi_ahb_hws[] = { &psi_ahb_clk.common.hw };
 282 static const struct clk_hw *apb0_hws[] = { &apb0_clk.common.hw };
 283 static const struct clk_hw *apb1_hws[] = { &apb1_clk.common.hw };
 284
 285 static const struct clk_hw *de_di_g2d_parents[] = {
 286         &pll_periph0_2x_clk.common.hw,
 287         &pll_video0_4x_clk.common.hw,
 288         &pll_video1_4x_clk.common.hw,
 289         &pll_audio1_div2_clk.common.hw,
 290 };
 291 static SUNXI_CCU_M_HW_WITH_MUX_GATE(de_clk, "de", de_di_g2d_parents, 0x600,
 292                                     0, 5,       /* M */
 293                                     24, 3,      /* mux */
 294                                     BIT(31),    /* gate */
 295                                     CLK_SET_RATE_PARENT);
 296
 297 static SUNXI_CCU_GATE_HWS(bus_de_clk, "bus-de", psi_ahb_hws,
 298                           0x60c, BIT(0), 0);
 299
 300 static SUNXI_CCU_M_HW_WITH_MUX_GATE(di_clk, "di", de_di_g2d_parents, 0x620,
 301                                     0, 5,       /* M */
 302                                     24, 3,      /* mux */
 303                                     BIT(31),    /* gate */
 304                                     CLK_SET_RATE_PARENT);
 305
 306 static SUNXI_CCU_GATE_HWS(bus_di_clk, "bus-di", psi_ahb_hws,
 307                           0x62c, BIT(0), 0);
 308
 309 static SUNXI_CCU_M_HW_WITH_MUX_GATE(g2d_clk, "g2d", de_di_g2d_parents, 0x630,
 310                                     0, 5,       /* M */
 311                                     24, 3,      /* mux */
 312                                     BIT(31),    /* gate */
 313                                     0);
 314
 315 static SUNXI_CCU_GATE_HWS(bus_g2d_clk, "bus-g2d", psi_ahb_hws,
 316                           0x63c, BIT(0), 0);
 317
 318 static const struct clk_parent_data ce_parents[] = {
 319         { .fw_name = "hosc" },
 320         { .hw = &pll_periph0_2x_clk.common.hw },
 321         { .hw = &pll_periph0_clk.hw },
 322 };
 323 static SUNXI_CCU_MP_DATA_WITH_MUX_GATE(ce_clk, "ce", ce_parents, 0x680,
 324                                        0, 4,    /* M */
 325                                        8, 2,    /* P */
 326                                        24, 3,   /* mux */
 327                                        BIT(31), /* gate */
 328                                        0);
 329
 330 static SUNXI_CCU_GATE_HWS(bus_ce_clk, "bus-ce", psi_ahb_hws,
 331                           0x68c, BIT(0), 0);
 332
 333 static const struct clk_hw *ve_parents[] = {
 334         &pll_ve_clk.common.hw,
 335         &pll_periph0_2x_clk.common.hw,
 336 };
 337 static SUNXI_CCU_M_HW_WITH_MUX_GATE(ve_clk, "ve", ve_parents, 0x690,
 338                                     0, 5,       /* M */
 339                                     24, 1,      /* mux */
 340                                     BIT(31),    /* gate */
 341                                     CLK_SET_RATE_PARENT);
 342
 343 static SUNXI_CCU_GATE_HWS(bus_ve_clk, "bus-ve", psi_ahb_hws,
 344                           0x69c, BIT(0), 0);
 345
 346 static SUNXI_CCU_GATE_HWS(bus_dma_clk, "bus-dma", psi_ahb_hws,
 347                           0x70c, BIT(0), 0);
 348
 349 static SUNXI_CCU_GATE_HWS(bus_msgbox0_clk, "bus-msgbox0", psi_ahb_hws,
 350                           0x71c, BIT(0), 0);
 351 static SUNXI_CCU_GATE_HWS(bus_msgbox1_clk, "bus-msgbox1", psi_ahb_hws,
 352                           0x71c, BIT(1), 0);
 353 static SUNXI_CCU_GATE_HWS(bus_msgbox2_clk, "bus-msgbox2", psi_ahb_hws,
 354                           0x71c, BIT(2), 0);
 355
 356 static SUNXI_CCU_GATE_HWS(bus_spinlock_clk, "bus-spinlock", psi_ahb_hws,
 357                           0x72c, BIT(0), 0);
 358
 359 static SUNXI_CCU_GATE_HWS(bus_hstimer_clk, "bus-hstimer", psi_ahb_hws,
 360                           0x73c, BIT(0), 0);
 361
 362 static SUNXI_CCU_GATE_DATA(avs_clk, "avs", osc24M,
 363                            0x740, BIT(31), 0);
 364
 365 static SUNXI_CCU_GATE_HWS(bus_dbg_clk, "bus-dbg", psi_ahb_hws,
 366                           0x78c, BIT(0), 0);
 367
 368 static SUNXI_CCU_GATE_HWS(bus_pwm_clk, "bus-pwm", apb0_hws,
 369                           0x7ac, BIT(0), 0);
 370
 371 static SUNXI_CCU_GATE_HWS(bus_iommu_clk, "bus-iommu", apb0_hws,
 372                           0x7bc, BIT(0), 0);
 373
 374 static const struct clk_hw *dram_parents[] = {
 375         &pll_ddr0_clk.common.hw,
 376         &pll_audio1_div2_clk.common.hw,
 377         &pll_periph0_2x_clk.common.hw,
 378         &pll_periph0_800M_clk.common.hw,
 379 };
 380 static SUNXI_CCU_MP_HW_WITH_MUX_GATE(dram_clk, "dram", dram_parents, 0x800,
 381                                      0, 2,      /* M */
 382                                      8, 2,      /* P */
 383                                      24, 2,     /* mux */
 384                                      BIT(31), CLK_IS_CRITICAL);
 385
 386 static CLK_FIXED_FACTOR_HW(mbus_clk, "mbus",
 387                            &dram_clk.common.hw, 4, 1, 0);
 388
 389 static const struct clk_hw *mbus_hws[] = { &mbus_clk.hw };
 390
 391 static SUNXI_CCU_GATE_HWS(mbus_dma_clk, "mbus-dma", mbus_hws,
 392                           0x804, BIT(0), 0);
 393 static SUNXI_CCU_GATE_HWS(mbus_ve_clk, "mbus-ve", mbus_hws,
 394                           0x804, BIT(1), 0);
 395 static SUNXI_CCU_GATE_HWS(mbus_ce_clk, "mbus-ce", mbus_hws,
 396                           0x804, BIT(2), 0);
 397 static SUNXI_CCU_GATE_HWS(mbus_tvin_clk, "mbus-tvin", mbus_hws,
 398                           0x804, BIT(7), 0);
 399 static SUNXI_CCU_GATE_HWS(mbus_csi_clk, "mbus-csi", mbus_hws,
 400                           0x804, BIT(8), 0);
 401 static SUNXI_CCU_GATE_HWS(mbus_g2d_clk, "mbus-g2d", mbus_hws,
 402                           0x804, BIT(10), 0);
 403 static SUNXI_CCU_GATE_HWS(mbus_riscv_clk, "mbus-riscv", mbus_hws,
 404                           0x804, BIT(11), 0);
 405
 406 static SUNXI_CCU_GATE_HWS(bus_dram_clk, "bus-dram", psi_ahb_hws,
 407                           0x80c, BIT(0), CLK_IS_CRITICAL);
 408
 409 static const struct clk_parent_data mmc0_mmc1_parents[] = {
 410         { .fw_name = "hosc" },
 411         { .hw = &pll_periph0_clk.hw },
 412         { .hw = &pll_periph0_2x_clk.common.hw },
 413         { .hw = &pll_audio1_div2_clk.common.hw },
 414 };
 415 static SUNXI_CCU_MP_DATA_WITH_MUX_GATE(mmc0_clk, "mmc0", mmc0_mmc1_parents, 0x830,
 416                                        0, 4,    /* M */
 417                                        8, 2,    /* P */
 418                                        24, 3,   /* mux */
 419                                        BIT(31), /* gate */
 420                                        0);
 421
 422 static SUNXI_CCU_MP_DATA_WITH_MUX_GATE(mmc1_clk, "mmc1", mmc0_mmc1_parents, 0x834,
 423                                        0, 4,    /* M */
 424                                        8, 2,    /* P */
 425                                        24, 3,   /* mux */
 426                                        BIT(31), /* gate */
 427                                        0);
 428
 429 static const struct clk_parent_data mmc2_parents[] = {
 430         { .fw_name = "hosc" },
 431         { .hw = &pll_periph0_clk.hw },
 432         { .hw = &pll_periph0_2x_clk.common.hw },
 433         { .hw = &pll_periph0_800M_clk.common.hw },
 434         { .hw = &pll_audio1_div2_clk.common.hw },
 435 };
 436 static SUNXI_CCU_MP_DATA_WITH_MUX_GATE(mmc2_clk, "mmc2", mmc2_parents, 0x838,
 437                                        0, 4,    /* M */
 438                                        8, 2,    /* P */
 439                                        24, 3,   /* mux */
 440                                        BIT(31), /* gate */
 441                                        0);
 442
 443 static SUNXI_CCU_GATE_HWS(bus_mmc0_clk, "bus-mmc0", psi_ahb_hws,
 444                           0x84c, BIT(0), 0);
 445 static SUNXI_CCU_GATE_HWS(bus_mmc1_clk, "bus-mmc1", psi_ahb_hws,
 446                           0x84c, BIT(1), 0);
 447 static SUNXI_CCU_GATE_HWS(bus_mmc2_clk, "bus-mmc2", psi_ahb_hws,
 448                           0x84c, BIT(2), 0);
 449
 450 static SUNXI_CCU_GATE_HWS(bus_uart0_clk, "bus-uart0", apb1_hws,
 451                           0x90c, BIT(0), 0);
 452 static SUNXI_CCU_GATE_HWS(bus_uart1_clk, "bus-uart1", apb1_hws,
 453                           0x90c, BIT(1), 0);
 454 static SUNXI_CCU_GATE_HWS(bus_uart2_clk, "bus-uart2", apb1_hws,
 455                           0x90c, BIT(2), 0);
 456 static SUNXI_CCU_GATE_HWS(bus_uart3_clk, "bus-uart3", apb1_hws,
 457                           0x90c, BIT(3), 0);
 458 static SUNXI_CCU_GATE_HWS(bus_uart4_clk, "bus-uart4", apb1_hws,
 459                           0x90c, BIT(4), 0);
 460 static SUNXI_CCU_GATE_HWS(bus_uart5_clk, "bus-uart5", apb1_hws,
 461                           0x90c, BIT(5), 0);
 462
 463 static SUNXI_CCU_GATE_HWS(bus_i2c0_clk, "bus-i2c0", apb1_hws,
 464                           0x91c, BIT(0), 0);
 465 static SUNXI_CCU_GATE_HWS(bus_i2c1_clk, "bus-i2c1", apb1_hws,
 466                           0x91c, BIT(1), 0);
 467 static SUNXI_CCU_GATE_HWS(bus_i2c2_clk, "bus-i2c2", apb1_hws,
 468                           0x91c, BIT(2), 0);
 469 static SUNXI_CCU_GATE_HWS(bus_i2c3_clk, "bus-i2c3", apb1_hws,
 470                           0x91c, BIT(3), 0);
 471
 472 static const struct clk_parent_data spi_parents[] = {
 473         { .fw_name = "hosc" },
 474         { .hw = &pll_periph0_clk.hw },
 475         { .hw = &pll_periph0_2x_clk.common.hw },
 476         { .hw = &pll_audio1_div2_clk.common.hw },
 477         { .hw = &pll_audio1_div5_clk.common.hw },
 478 };
 479 static SUNXI_CCU_MP_DATA_WITH_MUX_GATE(spi0_clk, "spi0", spi_parents, 0x940,
 480                                        0, 4,    /* M */
 481                                        8, 2,    /* P */
 482                                        24, 3,   /* mux */
 483                                        BIT(31), /* gate */
 484                                        0);
 485
 486 static SUNXI_CCU_MP_DATA_WITH_MUX_GATE(spi1_clk, "spi1", spi_parents, 0x944,
 487                                        0, 4,    /* M */
 488                                        8, 2,    /* P */
 489                                        24, 3,   /* mux */
 490                                        BIT(31), /* gate */
 491                                        0);
 492
 493 static SUNXI_CCU_GATE_HWS(bus_spi0_clk, "bus-spi0", psi_ahb_hws,
 494                           0x96c, BIT(0), 0);
 495 static SUNXI_CCU_GATE_HWS(bus_spi1_clk, "bus-spi1", psi_ahb_hws,
 496                           0x96c, BIT(1), 0);
 497
 498 static SUNXI_CCU_GATE_HWS_WITH_PREDIV(emac_25M_clk, "emac-25M", pll_periph0_hws,
 499                                       0x970, BIT(31) | BIT(30), 24, 0);
 500
 501 static SUNXI_CCU_GATE_HWS(bus_emac_clk, "bus-emac", psi_ahb_hws,
 502                           0x97c, BIT(0), 0);
 503
 504 static const struct clk_parent_data ir_tx_ledc_parents[] = {
 505         { .fw_name = "hosc" },
 506         { .hw = &pll_periph0_clk.hw },
 507 };
 508 static SUNXI_CCU_MP_DATA_WITH_MUX_GATE(ir_tx_clk, "ir-tx", ir_tx_ledc_parents, 0x9c0,
 509                                        0, 4,    /* M */
 510                                        8, 2,    /* P */
 511                                        24, 3,   /* mux */
 512                                        BIT(31), /* gate */
 513                                        0);
 514
 515 static SUNXI_CCU_GATE_HWS(bus_ir_tx_clk, "bus-ir-tx", apb0_hws,
 516                           0x9cc, BIT(0), 0);
 517
 518 static SUNXI_CCU_GATE_HWS(bus_gpadc_clk, "bus-gpadc", apb0_hws,
 519                           0x9ec, BIT(0), 0);
 520
 521 static SUNXI_CCU_GATE_HWS(bus_ths_clk, "bus-ths", apb0_hws,
 522                           0x9fc, BIT(0), 0);
 523
 524 static const struct clk_hw *i2s_spdif_tx_parents[] = {
 525         &pll_audio0_clk.hw,
 526         &pll_audio0_4x_clk.common.hw,
 527         &pll_audio1_div2_clk.common.hw,
 528         &pll_audio1_div5_clk.common.hw,
 529 };
 530 static SUNXI_CCU_MP_HW_WITH_MUX_GATE(i2s0_clk, "i2s0", i2s_spdif_tx_parents, 0xa10,
 531                                      0, 5,      /* M */
 532                                      8, 2,      /* P */
 533                                      24, 3,     /* mux */
 534                                      BIT(31),   /* gate */
 535                                      0);
 536
 537 static SUNXI_CCU_MP_HW_WITH_MUX_GATE(i2s1_clk, "i2s1", i2s_spdif_tx_parents, 0xa14,
 538                                      0, 5,      /* M */
 539                                      8, 2,      /* P */
 540                                      24, 3,     /* mux */
 541                                      BIT(31),   /* gate */
 542                                      0);
 543
 544 static SUNXI_CCU_MP_HW_WITH_MUX_GATE(i2s2_clk, "i2s2", i2s_spdif_tx_parents, 0xa18,
 545                                      0, 5,      /* M */
 546                                      8, 2,      /* P */
 547                                      24, 3,     /* mux */
 548                                      BIT(31),   /* gate */
 549                                      0);
 550
 551 static const struct clk_hw *i2s2_asrc_parents[] = {
 552         &pll_audio0_4x_clk.common.hw,
 553         &pll_periph0_clk.hw,
 554         &pll_audio1_div2_clk.common.hw,
 555         &pll_audio1_div5_clk.common.hw,
 556 };
 557 static SUNXI_CCU_MP_HW_WITH_MUX_GATE(i2s2_asrc_clk, "i2s2-asrc", i2s2_asrc_parents, 0xa1c,
 558                                      0, 5,      /* M */
 559                                      8, 2,      /* P */
 560                                      24, 3,     /* mux */
 561                                      BIT(31),   /* gate */
 562                                      0);
 563
 564 static SUNXI_CCU_GATE_HWS(bus_i2s0_clk, "bus-i2s0", apb0_hws,
 565                           0xa20, BIT(0), 0);
 566 static SUNXI_CCU_GATE_HWS(bus_i2s1_clk, "bus-i2s1", apb0_hws,
 567                           0xa20, BIT(1), 0);
 568 static SUNXI_CCU_GATE_HWS(bus_i2s2_clk, "bus-i2s2", apb0_hws,
 569                           0xa20, BIT(2), 0);
 570
 571 static SUNXI_CCU_MP_HW_WITH_MUX_GATE(spdif_tx_clk, "spdif-tx", i2s_spdif_tx_parents, 0xa24,
 572                                      0, 5,      /* M */
 573                                      8, 2,      /* P */
 574                                      24, 3,     /* mux */
 575                                      BIT(31),   /* gate */
 576                                      0);
 577
 578 static const struct clk_hw *spdif_rx_parents[] = {
 579         &pll_periph0_clk.hw,
 580         &pll_audio1_div2_clk.common.hw,
 581         &pll_audio1_div5_clk.common.hw,
 582 };
 583 static SUNXI_CCU_MP_HW_WITH_MUX_GATE(spdif_rx_clk, "spdif-rx", spdif_rx_parents, 0xa28,
 584                                      0, 5,      /* M */
 585                                      8, 2,      /* P */
 586                                      24, 3,     /* mux */
 587                                      BIT(31),   /* gate */
 588                                      0);
 589
 590 static SUNXI_CCU_GATE_HWS(bus_spdif_clk, "bus-spdif", apb0_hws,
 591                           0xa2c, BIT(0), 0);
 592
 593 static const struct clk_hw *dmic_codec_parents[] = {
 594         &pll_audio0_clk.hw,
 595         &pll_audio1_div2_clk.common.hw,
 596         &pll_audio1_div5_clk.common.hw,
 597 };
 598 static SUNXI_CCU_MP_HW_WITH_MUX_GATE(dmic_clk, "dmic", dmic_codec_parents, 0xa40,
 599                                      0, 5,      /* M */
 600                                      8, 2,      /* P */
 601                                      24, 3,     /* mux */
 602                                      BIT(31),   /* gate */
 603                                      0);
 604
 605 static SUNXI_CCU_GATE_HWS(bus_dmic_clk, "bus-dmic", apb0_hws,
 606                           0xa4c, BIT(0), 0);
 607
 608 static SUNXI_CCU_MP_HW_WITH_MUX_GATE(audio_dac_clk, "audio-dac", dmic_codec_parents, 0xa50,
 609                                      0, 5,      /* M */
 610                                      8, 2,      /* P */
 611                                      24, 3,     /* mux */
 612                                      BIT(31),   /* gate */
 613                                      0);
 614
 615 static SUNXI_CCU_MP_HW_WITH_MUX_GATE(audio_adc_clk, "audio-adc", dmic_codec_parents, 0xa54,
 616                                      0, 5,      /* M */
 617                                      8, 2,      /* P */
 618                                      24, 3,     /* mux */
 619                                      BIT(31),   /* gate */
 620                                      0);
 621
 622 static SUNXI_CCU_GATE_HWS(bus_audio_clk, "bus-audio", apb0_hws,
 623                           0xa5c, BIT(0), 0);
 624
 625
 626 /*
 627  * The first parent is a 48 MHz input clock divided by 4. That 48 MHz clock is
 628  * a 2x multiplier from osc24M synchronized by pll-periph0, and is also used by
 629  * the OHCI module.
 630  */
 631 static const struct clk_parent_data usb_ohci_parents[] = {
 632         { .hw = &pll_periph0_clk.hw },
 633         { .fw_name = "hosc" },
 634         { .fw_name = "losc" },
 635 };
 636 static const struct ccu_mux_fixed_prediv usb_ohci_predivs[] = {
 637         { .index = 0, .div = 50 },
 638         { .index = 1, .div = 2 },
 639 };
 640
 641 static struct ccu_mux usb_ohci0_clk = {
 642         .enable         = BIT(31),
 643         .mux            = {
 644                 .shift          = 24,
 645                 .width          = 2,
 646                 .fixed_predivs  = usb_ohci_predivs,
 647                 .n_predivs      = ARRAY_SIZE(usb_ohci_predivs),
 648         },
 649         .common         = {
 650                 .reg            = 0xa70,
 651                 .features       = CCU_FEATURE_FIXED_PREDIV,
 652                 .hw.init        = CLK_HW_INIT_PARENTS_DATA("usb-ohci0",
 653                                                            usb_ohci_parents,
 654                                                            &ccu_mux_ops,
 655                                                            0),
 656         },
 657 };
 658
 659 static struct ccu_mux usb_ohci1_clk = {
 660         .enable         = BIT(31),
 661         .mux            = {
 662                 .shift          = 24,
 663                 .width          = 2,
 664                 .fixed_predivs  = usb_ohci_predivs,
 665                 .n_predivs      = ARRAY_SIZE(usb_ohci_predivs),
 666         },
 667         .common         = {
 668                 .reg            = 0xa74,
 669                 .features       = CCU_FEATURE_FIXED_PREDIV,
 670                 .hw.init        = CLK_HW_INIT_PARENTS_DATA("usb-ohci1",
 671                                                            usb_ohci_parents,
 672                                                            &ccu_mux_ops,
 673                                                            0),
 674         },
 675 };
 676
 677 static SUNXI_CCU_GATE_HWS(bus_ohci0_clk, "bus-ohci0", psi_ahb_hws,
 678                           0xa8c, BIT(0), 0);
 679 static SUNXI_CCU_GATE_HWS(bus_ohci1_clk, "bus-ohci1", psi_ahb_hws,
 680                           0xa8c, BIT(1), 0);
 681 static SUNXI_CCU_GATE_HWS(bus_ehci0_clk, "bus-ehci0", psi_ahb_hws,
 682                           0xa8c, BIT(4), 0);
 683 static SUNXI_CCU_GATE_HWS(bus_ehci1_clk, "bus-ehci1", psi_ahb_hws,
 684                           0xa8c, BIT(5), 0);
 685 static SUNXI_CCU_GATE_HWS(bus_otg_clk, "bus-otg", psi_ahb_hws,
 686                           0xa8c, BIT(8), 0);
 687
 688 static SUNXI_CCU_GATE_HWS(bus_lradc_clk, "bus-lradc", apb0_hws,
 689                           0xa9c, BIT(0), 0);
 690
 691 static SUNXI_CCU_GATE_HWS(bus_dpss_top_clk, "bus-dpss-top", psi_ahb_hws,
 692                           0xabc, BIT(0), 0);
 693
 694 static SUNXI_CCU_GATE_DATA(hdmi_24M_clk, "hdmi-24M", osc24M,
 695                            0xb04, BIT(31), 0);
 696
 697 static SUNXI_CCU_GATE_HWS_WITH_PREDIV(hdmi_cec_32k_clk, "hdmi-cec-32k",
 698                                       pll_periph0_2x_hws,
 699                                       0xb10, BIT(30), 36621, 0);
 700
 701 static const struct clk_parent_data hdmi_cec_parents[] = {
 702         { .fw_name = "losc" },
 703         { .hw = &hdmi_cec_32k_clk.common.hw },
 704 };
 705 static SUNXI_CCU_MUX_DATA_WITH_GATE(hdmi_cec_clk, "hdmi-cec", hdmi_cec_parents, 0xb10,
 706                                     24, 1,      /* mux */
 707                                     BIT(31),    /* gate */
 708                                     0);
 709
 710 static SUNXI_CCU_GATE_HWS(bus_hdmi_clk, "bus-hdmi", psi_ahb_hws,
 711                           0xb1c, BIT(0), 0);
 712
 713 static const struct clk_parent_data mipi_dsi_parents[] = {
 714         { .fw_name = "hosc" },
 715         { .hw = &pll_periph0_clk.hw },
 716         { .hw = &pll_video0_2x_clk.hw },
 717         { .hw = &pll_video1_2x_clk.hw },
 718         { .hw = &pll_audio1_div2_clk.common.hw },
 719 };
 720 static SUNXI_CCU_M_DATA_WITH_MUX_GATE(mipi_dsi_clk, "mipi-dsi", mipi_dsi_parents, 0xb24,
 721                                       0, 4,     /* M */
 722                                       24, 3,    /* mux */
 723                                       BIT(31),  /* gate */
 724                                       CLK_SET_RATE_PARENT);
 725
 726 static SUNXI_CCU_GATE_HWS(bus_mipi_dsi_clk, "bus-mipi-dsi", psi_ahb_hws,
 727                           0xb4c, BIT(0), 0);
 728
 729 static const struct clk_hw *tcon_tve_parents[] = {
 730         &pll_video0_clk.hw,
 731         &pll_video0_4x_clk.common.hw,
 732         &pll_video1_clk.hw,
 733         &pll_video1_4x_clk.common.hw,
 734         &pll_periph0_2x_clk.common.hw,
 735         &pll_audio1_div2_clk.common.hw,
 736 };
 737 static SUNXI_CCU_MP_HW_WITH_MUX_GATE(tcon_lcd0_clk, "tcon-lcd0", tcon_tve_parents, 0xb60,
 738                                      0, 4,      /* M */
 739                                      8, 2,      /* P */
 740                                      24, 3,     /* mux */
 741                                      BIT(31),   /* gate */
 742                                      CLK_SET_RATE_PARENT);
 743
 744 static SUNXI_CCU_GATE_HWS(bus_tcon_lcd0_clk, "bus-tcon-lcd0", psi_ahb_hws,
 745                           0xb7c, BIT(0), 0);
 746
 747 static SUNXI_CCU_MP_HW_WITH_MUX_GATE(tcon_tv_clk, "tcon-tv", tcon_tve_parents, 0xb80,
 748                                      0, 4,      /* M */
 749                                      8, 2,      /* P */
 750                                      24, 3,     /* mux */
 751                                      BIT(31),   /* gate */
 752                                      CLK_SET_RATE_PARENT);
 753
 754 static SUNXI_CCU_GATE_HWS(bus_tcon_tv_clk, "bus-tcon-tv", psi_ahb_hws,
 755                           0xb9c, BIT(0), 0);
 756
 757 static SUNXI_CCU_MP_HW_WITH_MUX_GATE(tve_clk, "tve", tcon_tve_parents, 0xbb0,
 758                                      0, 4,      /* M */
 759                                      8, 2,      /* P */
 760                                      24, 3,     /* mux */
 761                                      BIT(31),   /* gate */
 762                                      0);
 763
 764 static SUNXI_CCU_GATE_HWS(bus_tve_top_clk, "bus-tve-top", psi_ahb_hws,
 765                           0xbbc, BIT(0), 0);
 766 static SUNXI_CCU_GATE_HWS(bus_tve_clk, "bus-tve", psi_ahb_hws,
 767                           0xbbc, BIT(1), 0);
 768
 769 static const struct clk_parent_data tvd_parents[] = {
 770         { .fw_name = "hosc" },
 771         { .hw = &pll_video0_clk.hw },
 772         { .hw = &pll_video1_clk.hw },
 773         { .hw = &pll_periph0_clk.hw },
 774 };
 775 static SUNXI_CCU_M_DATA_WITH_MUX_GATE(tvd_clk, "tvd", tvd_parents, 0xbc0,
 776                                       0, 5,     /* M */
 777                                       24, 3,    /* mux */
 778                                       BIT(31),  /* gate */
 779                                       0);
 780
 781 static SUNXI_CCU_GATE_HWS(bus_tvd_top_clk, "bus-tvd-top", psi_ahb_hws,
 782                           0xbdc, BIT(0), 0);
 783 static SUNXI_CCU_GATE_HWS(bus_tvd_clk, "bus-tvd", psi_ahb_hws,
 784                           0xbdc, BIT(1), 0);
 785
 786 static SUNXI_CCU_MP_DATA_WITH_MUX_GATE(ledc_clk, "ledc", ir_tx_ledc_parents, 0xbf0,
 787                                        0, 4,    /* M */
 788                                        8, 2,    /* P */
 789                                        24, 1,   /* mux */
 790                                        BIT(31), /* gate */
 791                                        0);
 792
 793 static SUNXI_CCU_GATE_HWS(bus_ledc_clk, "bus-ledc", psi_ahb_hws,
 794                           0xbfc, BIT(0), 0);
 795
 796 static const struct clk_hw *csi_top_parents[] = {
 797         &pll_periph0_2x_clk.common.hw,
 798         &pll_video0_2x_clk.hw,
 799         &pll_video1_2x_clk.hw,
 800 };
 801 static SUNXI_CCU_M_HW_WITH_MUX_GATE(csi_top_clk, "csi-top", csi_top_parents, 0xc04,
 802                                     0, 4,       /* M */
 803                                     24, 3,      /* mux */
 804                                     BIT(31),    /* gate */
 805                                     0);
 806
 807 static const struct clk_parent_data csi_mclk_parents[] = {
 808         { .fw_name = "hosc" },
 809         { .hw = &pll_periph0_clk.hw },
 810         { .hw = &pll_video0_clk.hw },
 811         { .hw = &pll_video1_clk.hw },
 812         { .hw = &pll_audio1_div2_clk.common.hw },
 813         { .hw = &pll_audio1_div5_clk.common.hw },
 814 };
 815 static SUNXI_CCU_M_DATA_WITH_MUX_GATE(csi_mclk_clk, "csi-mclk", csi_mclk_parents, 0xc08,
 816                                       0, 5,     /* M */
 817                                       24, 3,    /* mux */
 818                                       BIT(31),  /* gate */
 819                                       0);
 820
 821 static SUNXI_CCU_GATE_HWS(bus_csi_clk, "bus-csi", psi_ahb_hws,
 822                           0xc1c, BIT(0), 0);
 823
 824 static const struct clk_parent_data tpadc_parents[] = {
 825         { .fw_name = "hosc" },
 826         { .hw = &pll_audio0_clk.hw },
 827 };
 828 static SUNXI_CCU_MUX_DATA_WITH_GATE(tpadc_clk, "tpadc", tpadc_parents, 0xc50,
 829                                     24, 3,      /* mux */
 830                                     BIT(31),    /* gate */
 831                                     0);
 832
 833 static SUNXI_CCU_GATE_HWS(bus_tpadc_clk, "bus-tpadc", apb0_hws,
 834                           0xc5c, BIT(0), 0);
 835
 836 static SUNXI_CCU_GATE_HWS(bus_tzma_clk, "bus-tzma", apb0_hws,
 837                           0xc6c, BIT(0), 0);
 838
 839 static const struct clk_parent_data dsp_parents[] = {
 840         { .fw_name = "hosc" },
 841         { .fw_name = "losc" },
 842         { .fw_name = "iosc" },
 843         { .hw = &pll_periph0_2x_clk.common.hw },
 844         { .hw = &pll_audio1_div2_clk.common.hw },
 845 };
 846 static SUNXI_CCU_M_DATA_WITH_MUX_GATE(dsp_clk, "dsp", dsp_parents, 0xc70,
 847                                       0, 5,     /* M */
 848                                       24, 3,    /* mux */
 849                                       BIT(31),  /* gate */
 850                                       0);
 851
 852 static SUNXI_CCU_GATE_HWS(bus_dsp_cfg_clk, "bus-dsp-cfg", psi_ahb_hws,
 853                           0xc7c, BIT(1), 0);
 854
 855 /*
 856  * The RISC-V gate is not modelled - it is in a separate register (0xd04)
 857  * and has a special key field. The clock is critical anyway.
 858  */
 859 static const struct clk_parent_data riscv_parents[] = {
 860         { .fw_name = "hosc" },
 861         { .fw_name = "losc" },
 862         { .fw_name = "iosc" },
 863         { .hw = &pll_periph0_800M_clk.common.hw },
 864         { .hw = &pll_periph0_clk.hw },
 865         { .hw = &pll_cpux_clk.common.hw },
 866         { .hw = &pll_audio1_div2_clk.common.hw },
 867 };
 868 static SUNXI_CCU_M_DATA_WITH_MUX(riscv_clk, "riscv", riscv_parents, 0xd00,
 869                                  0, 5,  /* M */
 870                                  24, 3, /* mux */
 871                                  CLK_SET_RATE_PARENT | CLK_IS_CRITICAL);
 872
 873 /* The riscv-axi clk must be divided by at least 2. */
 874 static struct clk_div_table riscv_axi_table[] = {
 875         { .val = 1, .div = 2 },
 876         { .val = 2, .div = 3 },
 877         { .val = 3, .div = 4 },
 878         { /* Sentinel */ }
 879 };
 880 static SUNXI_CCU_DIV_TABLE_HW(riscv_axi_clk, "riscv-axi", &riscv_clk.common.hw,
 881                               0xd00, 8, 2, riscv_axi_table, 0);
 882
 883 static SUNXI_CCU_GATE_HWS(bus_riscv_cfg_clk, "bus-riscv-cfg", psi_ahb_hws,
 884                           0xd0c, BIT(0), CLK_IS_CRITICAL);
 885
 886 static SUNXI_CCU_GATE_DATA(fanout_24M_clk, "fanout-24M", osc24M,
 887                            0xf30, BIT(0), 0);
 888 static SUNXI_CCU_GATE_DATA_WITH_PREDIV(fanout_12M_clk, "fanout-12M", osc24M,
 889                                        0xf30, BIT(1), 2, 0);
 890 static SUNXI_CCU_GATE_HWS_WITH_PREDIV(fanout_16M_clk, "fanout-16M", pll_periph0_2x_hws,
 891                                       0xf30, BIT(2), 75, 0);
 892 static SUNXI_CCU_GATE_HWS_WITH_PREDIV(fanout_25M_clk, "fanout-25M", pll_periph0_hws,
 893                                       0xf30, BIT(3), 24, 0);
 894 static SUNXI_CCU_GATE_HWS_WITH_PREDIV(fanout_32k_clk, "fanout-32k", pll_periph0_2x_hws,
 895                                       0xf30, BIT(4), 36621, 0);
 896
 897 /* This clock has a second divider that is not modelled and forced to 0. */
 898 #define SUN20I_D1_FANOUT_27M_REG        0xf34
 899 static const struct clk_hw *fanout_27M_parents[] = {
 900         &pll_video0_clk.hw,
 901         &pll_video1_clk.hw,
 902 };
 903 static SUNXI_CCU_M_HW_WITH_MUX_GATE(fanout_27M_clk, "fanout-27M", fanout_27M_parents, 0xf34,
 904                                     0, 5,       /* M */
 905                                     24, 2,      /* mux */
 906                                     BIT(31),    /* gate */
 907                                     0);
 908
 909 static SUNXI_CCU_M_HWS_WITH_GATE(fanout_pclk_clk, "fanout-pclk", apb0_hws, 0xf38,
 910                                  0, 5,          /* M */
 911                                  BIT(31),       /* gate */
 912                                  0);
 913
 914 static const struct clk_hw *fanout_parents[] = {
 915         &fanout_32k_clk.common.hw,
 916         &fanout_12M_clk.common.hw,
 917         &fanout_16M_clk.common.hw,
 918         &fanout_24M_clk.common.hw,
 919         &fanout_25M_clk.common.hw,
 920         &fanout_27M_clk.common.hw,
 921         &fanout_pclk_clk.common.hw,
 922 };
 923 static SUNXI_CCU_MUX_HW_WITH_GATE(fanout0_clk, "fanout0", fanout_parents, 0xf3c,
 924                                   0, 3,         /* mux */
 925                                   BIT(21),      /* gate */
 926                                   0);
 927 static SUNXI_CCU_MUX_HW_WITH_GATE(fanout1_clk, "fanout1", fanout_parents, 0xf3c,
 928                                   3, 3,         /* mux */
 929                                   BIT(22),      /* gate */
 930                                   0);
 931 static SUNXI_CCU_MUX_HW_WITH_GATE(fanout2_clk, "fanout2", fanout_parents, 0xf3c,
 932                                   6, 3,         /* mux */
 933                                   BIT(23),      /* gate */
 934                                   0);
 935
 936 static struct ccu_common *sun20i_d1_ccu_clks[] = {
 937         &pll_cpux_clk.common,
 938         &pll_ddr0_clk.common,
 939         &pll_periph0_4x_clk.common,
 940         &pll_periph0_2x_clk.common,
 941         &pll_periph0_800M_clk.common,
 942         &pll_video0_4x_clk.common,
 943         &pll_video1_4x_clk.common,
 944         &pll_ve_clk.common,
 945         &pll_audio0_4x_clk.common,
 946         &pll_audio1_clk.common,
 947         &pll_audio1_div2_clk.common,
 948         &pll_audio1_div5_clk.common,
 949         &cpux_clk.common,
 950         &cpux_axi_clk.common,
 951         &cpux_apb_clk.common,
 952         &psi_ahb_clk.common,
 953         &apb0_clk.common,
 954         &apb1_clk.common,
 955         &de_clk.common,
 956         &bus_de_clk.common,
 957         &di_clk.common,
 958         &bus_di_clk.common,
 959         &g2d_clk.common,
 960         &bus_g2d_clk.common,
 961         &ce_clk.common,
 962         &bus_ce_clk.common,
 963         &ve_clk.common,
 964         &bus_ve_clk.common,
 965         &bus_dma_clk.common,
 966         &bus_msgbox0_clk.common,
 967         &bus_msgbox1_clk.common,
 968         &bus_msgbox2_clk.common,
 969         &bus_spinlock_clk.common,
 970         &bus_hstimer_clk.common,
 971         &avs_clk.common,
 972         &bus_dbg_clk.common,
 973         &bus_pwm_clk.common,
 974         &bus_iommu_clk.common,
 975         &dram_clk.common,
 976         &mbus_dma_clk.common,
 977         &mbus_ve_clk.common,
 978         &mbus_ce_clk.common,
 979         &mbus_tvin_clk.common,
 980         &mbus_csi_clk.common,
 981         &mbus_g2d_clk.common,
 982         &mbus_riscv_clk.common,
 983         &bus_dram_clk.common,
 984         &mmc0_clk.common,
 985         &mmc1_clk.common,
 986         &mmc2_clk.common,
 987         &bus_mmc0_clk.common,
 988         &bus_mmc1_clk.common,
 989         &bus_mmc2_clk.common,
 990         &bus_uart0_clk.common,
 991         &bus_uart1_clk.common,
 992         &bus_uart2_clk.common,
 993         &bus_uart3_clk.common,
 994         &bus_uart4_clk.common,
 995         &bus_uart5_clk.common,
 996         &bus_i2c0_clk.common,
 997         &bus_i2c1_clk.common,
 998         &bus_i2c2_clk.common,
 999         &bus_i2c3_clk.common,
1000         &spi0_clk.common,
1001         &spi1_clk.common,
1002         &bus_spi0_clk.common,
1003         &bus_spi1_clk.common,
1004         &emac_25M_clk.common,
1005         &bus_emac_clk.common,
1006         &ir_tx_clk.common,
1007         &bus_ir_tx_clk.common,
1008         &bus_gpadc_clk.common,
1009         &bus_ths_clk.common,
1010         &i2s0_clk.common,
1011         &i2s1_clk.common,
1012         &i2s2_clk.common,
1013         &i2s2_asrc_clk.common,
1014         &bus_i2s0_clk.common,
1015         &bus_i2s1_clk.common,
1016         &bus_i2s2_clk.common,
1017         &spdif_tx_clk.common,
1018         &spdif_rx_clk.common,
1019         &bus_spdif_clk.common,
1020         &dmic_clk.common,
1021         &bus_dmic_clk.common,
1022         &audio_dac_clk.common,
1023         &audio_adc_clk.common,
1024         &bus_audio_clk.common,
1025         &usb_ohci0_clk.common,
1026         &usb_ohci1_clk.common,
1027         &bus_ohci0_clk.common,
1028         &bus_ohci1_clk.common,
1029         &bus_ehci0_clk.common,
1030         &bus_ehci1_clk.common,
1031         &bus_otg_clk.common,
1032         &bus_lradc_clk.common,
1033         &bus_dpss_top_clk.common,
1034         &hdmi_24M_clk.common,
1035         &hdmi_cec_32k_clk.common,
1036         &hdmi_cec_clk.common,
1037         &bus_hdmi_clk.common,
1038         &mipi_dsi_clk.common,
1039         &bus_mipi_dsi_clk.common,
1040         &tcon_lcd0_clk.common,
1041         &bus_tcon_lcd0_clk.common,
1042         &tcon_tv_clk.common,
1043         &bus_tcon_tv_clk.common,
1044         &tve_clk.common,
1045         &bus_tve_top_clk.common,
1046         &bus_tve_clk.common,
1047         &tvd_clk.common,
1048         &bus_tvd_top_clk.common,
1049         &bus_tvd_clk.common,
1050         &ledc_clk.common,
1051         &bus_ledc_clk.common,
1052         &csi_top_clk.common,
1053         &csi_mclk_clk.common,
1054         &bus_csi_clk.common,
1055         &tpadc_clk.common,
1056         &bus_tpadc_clk.common,
1057         &bus_tzma_clk.common,
1058         &dsp_clk.common,
1059         &bus_dsp_cfg_clk.common,
1060         &riscv_clk.common,
1061         &riscv_axi_clk.common,
1062         &bus_riscv_cfg_clk.common,
1063         &fanout_24M_clk.common,
1064         &fanout_12M_clk.common,
1065         &fanout_16M_clk.common,
1066         &fanout_25M_clk.common,
1067         &fanout_32k_clk.common,
1068         &fanout_27M_clk.common,
1069         &fanout_pclk_clk.common,
1070         &fanout0_clk.common,
1071         &fanout1_clk.common,
1072         &fanout2_clk.common,
1073 };
1074
1075 static struct clk_hw_onecell_data sun20i_d1_hw_clks = {
1076         .num    = CLK_NUMBER,
1077         .hws    = {
1078                 [CLK_PLL_CPUX]          = &pll_cpux_clk.common.hw,
1079                 [CLK_PLL_DDR0]          = &pll_ddr0_clk.common.hw,
1080                 [CLK_PLL_PERIPH0_4X]    = &pll_periph0_4x_clk.common.hw,
1081                 [CLK_PLL_PERIPH0_2X]    = &pll_periph0_2x_clk.common.hw,
1082                 [CLK_PLL_PERIPH0_800M]  = &pll_periph0_800M_clk.common.hw,
1083                 [CLK_PLL_PERIPH0]       = &pll_periph0_clk.hw,
1084                 [CLK_PLL_PERIPH0_DIV3]  = &pll_periph0_div3_clk.hw,
1085                 [CLK_PLL_VIDEO0_4X]     = &pll_video0_4x_clk.common.hw,
1086                 [CLK_PLL_VIDEO0_2X]     = &pll_video0_2x_clk.hw,
1087                 [CLK_PLL_VIDEO0]        = &pll_video0_clk.hw,
1088                 [CLK_PLL_VIDEO1_4X]     = &pll_video1_4x_clk.common.hw,
1089                 [CLK_PLL_VIDEO1_2X]     = &pll_video1_2x_clk.hw,
1090                 [CLK_PLL_VIDEO1]        = &pll_video1_clk.hw,
1091                 [CLK_PLL_VE]            = &pll_ve_clk.common.hw,
1092                 [CLK_PLL_AUDIO0_4X]     = &pll_audio0_4x_clk.common.hw,
1093                 [CLK_PLL_AUDIO0_2X]     = &pll_audio0_2x_clk.hw,
1094                 [CLK_PLL_AUDIO0]        = &pll_audio0_clk.hw,
1095                 [CLK_PLL_AUDIO1]        = &pll_audio1_clk.common.hw,
1096                 [CLK_PLL_AUDIO1_DIV2]   = &pll_audio1_div2_clk.common.hw,
1097                 [CLK_PLL_AUDIO1_DIV5]   = &pll_audio1_div5_clk.common.hw,
1098                 [CLK_CPUX]              = &cpux_clk.common.hw,
1099                 [CLK_CPUX_AXI]          = &cpux_axi_clk.common.hw,
1100                 [CLK_CPUX_APB]          = &cpux_apb_clk.common.hw,
1101                 [CLK_PSI_AHB]           = &psi_ahb_clk.common.hw,
1102                 [CLK_APB0]              = &apb0_clk.common.hw,
1103                 [CLK_APB1]              = &apb1_clk.common.hw,
1104                 [CLK_MBUS]              = &mbus_clk.hw,
1105                 [CLK_DE]                = &de_clk.common.hw,
1106                 [CLK_BUS_DE]            = &bus_de_clk.common.hw,
1107                 [CLK_DI]                = &di_clk.common.hw,
1108                 [CLK_BUS_DI]            = &bus_di_clk.common.hw,
1109                 [CLK_G2D]               = &g2d_clk.common.hw,
1110                 [CLK_BUS_G2D]           = &bus_g2d_clk.common.hw,
1111                 [CLK_CE]                = &ce_clk.common.hw,
1112                 [CLK_BUS_CE]            = &bus_ce_clk.common.hw,
1113                 [CLK_VE]                = &ve_clk.common.hw,
1114                 [CLK_BUS_VE]            = &bus_ve_clk.common.hw,
1115                 [CLK_BUS_DMA]           = &bus_dma_clk.common.hw,
1116                 [CLK_BUS_MSGBOX0]       = &bus_msgbox0_clk.common.hw,
1117                 [CLK_BUS_MSGBOX1]       = &bus_msgbox1_clk.common.hw,
1118                 [CLK_BUS_MSGBOX2]       = &bus_msgbox2_clk.common.hw,
1119                 [CLK_BUS_SPINLOCK]      = &bus_spinlock_clk.common.hw,
1120                 [CLK_BUS_HSTIMER]       = &bus_hstimer_clk.common.hw,
1121                 [CLK_AVS]               = &avs_clk.common.hw,
1122                 [CLK_BUS_DBG]           = &bus_dbg_clk.common.hw,
1123                 [CLK_BUS_PWM]           = &bus_pwm_clk.common.hw,
1124                 [CLK_BUS_IOMMU]         = &bus_iommu_clk.common.hw,
1125                 [CLK_DRAM]              = &dram_clk.common.hw,
1126                 [CLK_MBUS_DMA]          = &mbus_dma_clk.common.hw,
1127                 [CLK_MBUS_VE]           = &mbus_ve_clk.common.hw,
1128                 [CLK_MBUS_CE]           = &mbus_ce_clk.common.hw,
1129                 [CLK_MBUS_TVIN]         = &mbus_tvin_clk.common.hw,
1130                 [CLK_MBUS_CSI]          = &mbus_csi_clk.common.hw,
1131                 [CLK_MBUS_G2D]          = &mbus_g2d_clk.common.hw,
1132                 [CLK_MBUS_RISCV]        = &mbus_riscv_clk.common.hw,
1133                 [CLK_BUS_DRAM]          = &bus_dram_clk.common.hw,
1134                 [CLK_MMC0]              = &mmc0_clk.common.hw,
1135                 [CLK_MMC1]              = &mmc1_clk.common.hw,
1136                 [CLK_MMC2]              = &mmc2_clk.common.hw,
1137                 [CLK_BUS_MMC0]          = &bus_mmc0_clk.common.hw,
1138                 [CLK_BUS_MMC1]          = &bus_mmc1_clk.common.hw,
1139                 [CLK_BUS_MMC2]          = &bus_mmc2_clk.common.hw,
1140                 [CLK_BUS_UART0]         = &bus_uart0_clk.common.hw,
1141                 [CLK_BUS_UART1]         = &bus_uart1_clk.common.hw,
1142                 [CLK_BUS_UART2]         = &bus_uart2_clk.common.hw,
1143                 [CLK_BUS_UART3]         = &bus_uart3_clk.common.hw,
1144                 [CLK_BUS_UART4]         = &bus_uart4_clk.common.hw,
1145                 [CLK_BUS_UART5]         = &bus_uart5_clk.common.hw,
1146                 [CLK_BUS_I2C0]          = &bus_i2c0_clk.common.hw,
1147                 [CLK_BUS_I2C1]          = &bus_i2c1_clk.common.hw,
1148                 [CLK_BUS_I2C2]          = &bus_i2c2_clk.common.hw,
1149                 [CLK_BUS_I2C3]          = &bus_i2c3_clk.common.hw,
1150                 [CLK_SPI0]              = &spi0_clk.common.hw,
1151                 [CLK_SPI1]              = &spi1_clk.common.hw,
1152                 [CLK_BUS_SPI0]          = &bus_spi0_clk.common.hw,
1153                 [CLK_BUS_SPI1]          = &bus_spi1_clk.common.hw,
1154                 [CLK_EMAC_25M]          = &emac_25M_clk.common.hw,
1155                 [CLK_BUS_EMAC]          = &bus_emac_clk.common.hw,
1156                 [CLK_IR_TX]             = &ir_tx_clk.common.hw,
1157                 [CLK_BUS_IR_TX]         = &bus_ir_tx_clk.common.hw,
1158                 [CLK_BUS_GPADC]         = &bus_gpadc_clk.common.hw,
1159                 [CLK_BUS_THS]           = &bus_ths_clk.common.hw,
1160                 [CLK_I2S0]              = &i2s0_clk.common.hw,
1161                 [CLK_I2S1]              = &i2s1_clk.common.hw,
1162                 [CLK_I2S2]              = &i2s2_clk.common.hw,
1163                 [CLK_I2S2_ASRC]         = &i2s2_asrc_clk.common.hw,
1164                 [CLK_BUS_I2S0]          = &bus_i2s0_clk.common.hw,
1165                 [CLK_BUS_I2S1]          = &bus_i2s1_clk.common.hw,
1166                 [CLK_BUS_I2S2]          = &bus_i2s2_clk.common.hw,
1167                 [CLK_SPDIF_TX]          = &spdif_tx_clk.common.hw,
1168                 [CLK_SPDIF_RX]          = &spdif_rx_clk.common.hw,
1169                 [CLK_BUS_SPDIF]         = &bus_spdif_clk.common.hw,
1170                 [CLK_DMIC]              = &dmic_clk.common.hw,
1171                 [CLK_BUS_DMIC]          = &bus_dmic_clk.common.hw,
1172                 [CLK_AUDIO_DAC]         = &audio_dac_clk.common.hw,
1173                 [CLK_AUDIO_ADC]         = &audio_adc_clk.common.hw,
1174                 [CLK_BUS_AUDIO]         = &bus_audio_clk.common.hw,
1175                 [CLK_USB_OHCI0]         = &usb_ohci0_clk.common.hw,
1176                 [CLK_USB_OHCI1]         = &usb_ohci1_clk.common.hw,
1177                 [CLK_BUS_OHCI0]         = &bus_ohci0_clk.common.hw,
1178                 [CLK_BUS_OHCI1]         = &bus_ohci1_clk.common.hw,
1179                 [CLK_BUS_EHCI0]         = &bus_ehci0_clk.common.hw,
1180                 [CLK_BUS_EHCI1]         = &bus_ehci1_clk.common.hw,
1181                 [CLK_BUS_OTG]           = &bus_otg_clk.common.hw,
1182                 [CLK_BUS_LRADC]         = &bus_lradc_clk.common.hw,
1183                 [CLK_BUS_DPSS_TOP]      = &bus_dpss_top_clk.common.hw,
1184                 [CLK_HDMI_24M]          = &hdmi_24M_clk.common.hw,
1185                 [CLK_HDMI_CEC_32K]      = &hdmi_cec_32k_clk.common.hw,
1186                 [CLK_HDMI_CEC]          = &hdmi_cec_clk.common.hw,
1187                 [CLK_BUS_HDMI]          = &bus_hdmi_clk.common.hw,
1188                 [CLK_MIPI_DSI]          = &mipi_dsi_clk.common.hw,
1189                 [CLK_BUS_MIPI_DSI]      = &bus_mipi_dsi_clk.common.hw,
1190                 [CLK_TCON_LCD0]         = &tcon_lcd0_clk.common.hw,
1191                 [CLK_BUS_TCON_LCD0]     = &bus_tcon_lcd0_clk.common.hw,
1192                 [CLK_TCON_TV]           = &tcon_tv_clk.common.hw,
1193                 [CLK_BUS_TCON_TV]       = &bus_tcon_tv_clk.common.hw,
1194                 [CLK_TVE]               = &tve_clk.common.hw,
1195                 [CLK_BUS_TVE_TOP]       = &bus_tve_top_clk.common.hw,
1196                 [CLK_BUS_TVE]           = &bus_tve_clk.common.hw,
1197                 [CLK_TVD]               = &tvd_clk.common.hw,
1198                 [CLK_BUS_TVD_TOP]       = &bus_tvd_top_clk.common.hw,
1199                 [CLK_BUS_TVD]           = &bus_tvd_clk.common.hw,
1200                 [CLK_LEDC]              = &ledc_clk.common.hw,
1201                 [CLK_BUS_LEDC]          = &bus_ledc_clk.common.hw,
1202                 [CLK_CSI_TOP]           = &csi_top_clk.common.hw,
1203                 [CLK_CSI_MCLK]          = &csi_mclk_clk.common.hw,
1204                 [CLK_BUS_CSI]           = &bus_csi_clk.common.hw,
1205                 [CLK_TPADC]             = &tpadc_clk.common.hw,
1206                 [CLK_BUS_TPADC]         = &bus_tpadc_clk.common.hw,
1207                 [CLK_BUS_TZMA]          = &bus_tzma_clk.common.hw,
1208                 [CLK_DSP]               = &dsp_clk.common.hw,
1209                 [CLK_BUS_DSP_CFG]       = &bus_dsp_cfg_clk.common.hw,
1210                 [CLK_RISCV]             = &riscv_clk.common.hw,
1211                 [CLK_RISCV_AXI]         = &riscv_axi_clk.common.hw,
1212                 [CLK_BUS_RISCV_CFG]     = &bus_riscv_cfg_clk.common.hw,
1213                 [CLK_FANOUT_24M]        = &fanout_24M_clk.common.hw,
1214                 [CLK_FANOUT_12M]        = &fanout_12M_clk.common.hw,
1215                 [CLK_FANOUT_16M]        = &fanout_16M_clk.common.hw,
1216                 [CLK_FANOUT_25M]        = &fanout_25M_clk.common.hw,
1217                 [CLK_FANOUT_32K]        = &fanout_32k_clk.common.hw,
1218                 [CLK_FANOUT_27M]        = &fanout_27M_clk.common.hw,
1219                 [CLK_FANOUT_PCLK]       = &fanout_pclk_clk.common.hw,
1220                 [CLK_FANOUT0]           = &fanout0_clk.common.hw,
1221                 [CLK_FANOUT1]           = &fanout1_clk.common.hw,
1222                 [CLK_FANOUT2]           = &fanout2_clk.common.hw,
1223         },
1224 };
1225
1226 static struct ccu_reset_map sun20i_d1_ccu_resets[] = {
1227         [RST_MBUS]              = { 0x540, BIT(30) },
1228         [RST_BUS_DE]            = { 0x60c, BIT(16) },
1229         [RST_BUS_DI]            = { 0x62c, BIT(16) },
1230         [RST_BUS_G2D]           = { 0x63c, BIT(16) },
1231         [RST_BUS_CE]            = { 0x68c, BIT(16) },
1232         [RST_BUS_VE]            = { 0x69c, BIT(16) },
1233         [RST_BUS_DMA]           = { 0x70c, BIT(16) },
1234         [RST_BUS_MSGBOX0]       = { 0x71c, BIT(16) },
1235         [RST_BUS_MSGBOX1]       = { 0x71c, BIT(17) },
1236         [RST_BUS_MSGBOX2]       = { 0x71c, BIT(18) },
1237         [RST_BUS_SPINLOCK]      = { 0x72c, BIT(16) },
1238         [RST_BUS_HSTIMER]       = { 0x73c, BIT(16) },
1239         [RST_BUS_DBG]           = { 0x78c, BIT(16) },
1240         [RST_BUS_PWM]           = { 0x7ac, BIT(16) },
1241         [RST_BUS_DRAM]          = { 0x80c, BIT(16) },
1242         [RST_BUS_MMC0]          = { 0x84c, BIT(16) },
1243         [RST_BUS_MMC1]          = { 0x84c, BIT(17) },
1244         [RST_BUS_MMC2]          = { 0x84c, BIT(18) },
1245         [RST_BUS_UART0]         = { 0x90c, BIT(16) },
1246         [RST_BUS_UART1]         = { 0x90c, BIT(17) },
1247         [RST_BUS_UART2]         = { 0x90c, BIT(18) },
1248         [RST_BUS_UART3]         = { 0x90c, BIT(19) },
1249         [RST_BUS_UART4]         = { 0x90c, BIT(20) },
1250         [RST_BUS_UART5]         = { 0x90c, BIT(21) },
1251         [RST_BUS_I2C0]          = { 0x91c, BIT(16) },
1252         [RST_BUS_I2C1]          = { 0x91c, BIT(17) },
1253         [RST_BUS_I2C2]          = { 0x91c, BIT(18) },
1254         [RST_BUS_I2C3]          = { 0x91c, BIT(19) },
1255         [RST_BUS_SPI0]          = { 0x96c, BIT(16) },
1256         [RST_BUS_SPI1]          = { 0x96c, BIT(17) },
1257         [RST_BUS_EMAC]          = { 0x97c, BIT(16) },
1258         [RST_BUS_IR_TX]         = { 0x9cc, BIT(16) },
1259         [RST_BUS_GPADC]         = { 0x9ec, BIT(16) },
1260         [RST_BUS_THS]           = { 0x9fc, BIT(16) },
1261         [RST_BUS_I2S0]          = { 0xa20, BIT(16) },
1262         [RST_BUS_I2S1]          = { 0xa20, BIT(17) },
1263         [RST_BUS_I2S2]          = { 0xa20, BIT(18) },
1264         [RST_BUS_SPDIF]         = { 0xa2c, BIT(16) },
1265         [RST_BUS_DMIC]          = { 0xa4c, BIT(16) },
1266         [RST_BUS_AUDIO]         = { 0xa5c, BIT(16) },
1267         [RST_USB_PHY0]          = { 0xa70, BIT(30) },
1268         [RST_USB_PHY1]          = { 0xa74, BIT(30) },
1269         [RST_BUS_OHCI0]         = { 0xa8c, BIT(16) },
1270         [RST_BUS_OHCI1]         = { 0xa8c, BIT(17) },
1271         [RST_BUS_EHCI0]         = { 0xa8c, BIT(20) },
1272         [RST_BUS_EHCI1]         = { 0xa8c, BIT(21) },
1273         [RST_BUS_OTG]           = { 0xa8c, BIT(24) },
1274         [RST_BUS_LRADC]         = { 0xa9c, BIT(16) },
1275         [RST_BUS_DPSS_TOP]      = { 0xabc, BIT(16) },
1276         [RST_BUS_HDMI_MAIN]     = { 0xb1c, BIT(16) },
1277         [RST_BUS_HDMI_SUB]      = { 0xb1c, BIT(17) },
1278         [RST_BUS_MIPI_DSI]      = { 0xb4c, BIT(16) },
1279         [RST_BUS_TCON_LCD0]     = { 0xb7c, BIT(16) },
1280         [RST_BUS_TCON_TV]       = { 0xb9c, BIT(16) },
1281         [RST_BUS_LVDS0]         = { 0xbac, BIT(16) },
1282         [RST_BUS_TVE_TOP]       = { 0xbbc, BIT(16) },
1283         [RST_BUS_TVE]           = { 0xbbc, BIT(17) },
1284         [RST_BUS_TVD_TOP]       = { 0xbdc, BIT(16) },
1285         [RST_BUS_TVD]           = { 0xbdc, BIT(17) },
1286         [RST_BUS_LEDC]          = { 0xbfc, BIT(16) },
1287         [RST_BUS_CSI]           = { 0xc1c, BIT(16) },
1288         [RST_BUS_TPADC]         = { 0xc5c, BIT(16) },
1289         [RST_DSP]               = { 0xc7c, BIT(16) },
1290         [RST_BUS_DSP_CFG]       = { 0xc7c, BIT(17) },
1291         [RST_BUS_DSP_DBG]       = { 0xc7c, BIT(18) },
1292         [RST_BUS_RISCV_CFG]     = { 0xd0c, BIT(16) },
1293 };
1294
1295 static const struct sunxi_ccu_desc sun20i_d1_ccu_desc = {
1296         .ccu_clks       = sun20i_d1_ccu_clks,
1297         .num_ccu_clks   = ARRAY_SIZE(sun20i_d1_ccu_clks),
1298
1299         .hw_clks        = &sun20i_d1_hw_clks,
1300
1301         .resets         = sun20i_d1_ccu_resets,
1302         .num_resets     = ARRAY_SIZE(sun20i_d1_ccu_resets),
1303 };
1304
1305 static const u32 pll_regs[] = {
1306         SUN20I_D1_PLL_CPUX_REG,
1307         SUN20I_D1_PLL_DDR0_REG,
1308         SUN20I_D1_PLL_PERIPH0_REG,
1309         SUN20I_D1_PLL_VIDEO0_REG,
1310         SUN20I_D1_PLL_VIDEO1_REG,
1311         SUN20I_D1_PLL_VE_REG,
1312         SUN20I_D1_PLL_AUDIO0_REG,
1313         SUN20I_D1_PLL_AUDIO1_REG,
1314 };
1315
1316 static const u32 pll_video_regs[] = {
1317         SUN20I_D1_PLL_VIDEO0_REG,
1318         SUN20I_D1_PLL_VIDEO1_REG,
1319 };
1320
1321 static struct ccu_mux_nb sun20i_d1_riscv_nb = {
1322         .common         = &riscv_clk.common,
1323         .cm             = &riscv_clk.mux,
1324         .delay_us       = 1,
1325         .bypass_index   = 4, /* index of pll-periph0 */
1326 };
1327
1328 static int sun20i_d1_ccu_probe(struct platform_device *pdev)
1329 {
1330         void __iomem *reg;
1331         u32 val;
1332         int i, ret;
1333
1334         reg = devm_platform_ioremap_resource(pdev, 0);
1335         if (IS_ERR(reg))
1336                 return PTR_ERR(reg);
1337
1338         /* Enable the enable, LDO, and lock bits on all PLLs. */
1339         for (i = 0; i < ARRAY_SIZE(pll_regs); i++) {
1340                 val = readl(reg + pll_regs[i]);
1341                 val |= BIT(31) | BIT(30) | BIT(29);
1342                 writel(val, reg + pll_regs[i]);
1343         }
1344
1345         /* Force PLL_CPUX factor M to 0. */
1346         val = readl(reg + SUN20I_D1_PLL_CPUX_REG);
1347         val &= ~GENMASK(1, 0);
1348         writel(val, reg + SUN20I_D1_PLL_CPUX_REG);
1349
1350         /*
1351          * Force the output divider of video PLLs to 0.
1352          *
1353          * See the comment before pll-video0 definition for the reason.
1354          */
1355         for (i = 0; i < ARRAY_SIZE(pll_video_regs); i++) {
1356                 val = readl(reg + pll_video_regs[i]);
1357                 val &= ~BIT(0);
1358                 writel(val, reg + pll_video_regs[i]);
1359         }
1360
1361         /* Enforce m1 = 0, m0 = 0 for PLL_AUDIO0 */
1362         val = readl(reg + SUN20I_D1_PLL_AUDIO0_REG);
1363         val &= ~BIT(1) | BIT(0);
1364         writel(val, reg + SUN20I_D1_PLL_AUDIO0_REG);
1365
1366         /* Force fanout-27M factor N to 0. */
1367         val = readl(reg + SUN20I_D1_FANOUT_27M_REG);
1368         val &= ~GENMASK(9, 8);
1369         writel(val, reg + SUN20I_D1_FANOUT_27M_REG);
1370
1371         ret = devm_sunxi_ccu_probe(&pdev->dev, reg, &sun20i_d1_ccu_desc);
1372         if (ret)
1373                 return ret;
1374
1375         /* Reparent CPU during PLL CPUX rate changes */
1376         ccu_mux_notifier_register(pll_cpux_clk.common.hw.clk,
1377                                   &sun20i_d1_riscv_nb);
1378
1379         return 0;
1380 }
1381
1382 static const struct of_device_id sun20i_d1_ccu_ids[] = {
1383         { .compatible = "allwinner,sun20i-d1-ccu" },
1384         { }
1385 };
1386
1387 static struct platform_driver sun20i_d1_ccu_driver = {
1388         .probe  = sun20i_d1_ccu_probe,
1389         .driver = {
1390                 .name                   = "sun20i-d1-ccu",
1391                 .suppress_bind_attrs    = true,
1392                 .of_match_table         = sun20i_d1_ccu_ids,
1393         },
1394 };
1395 module_platform_driver(sun20i_d1_ccu_driver);
1396
1397 MODULE_IMPORT_NS(SUNXI_CCU);
1398 MODULE_LICENSE("GPL");