drivers/clk/sunxi/clk_h6.c

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Copyright (C) 2018 Amarula Solutions.
   4  * Author: Jagan Teki <jagan@amarulasolutions.com>
   5  */
   6
   7 #include <common.h>
   8 #include <clk-uclass.h>
   9 #include <dm.h>
  10 #include <errno.h>
  11 #include <clk/sunxi.h>
  12 #include <dt-bindings/clock/sun50i-h6-ccu.h>
  13 #include <dt-bindings/reset/sun50i-h6-ccu.h>
  14 #include <linux/bitops.h>
  15
  16 static struct ccu_clk_gate h6_gates[] = {
  17         [CLK_PLL_PERIPH0]       = GATE(0x020, BIT(31)),
  18
  19         [CLK_APB1]              = GATE_DUMMY,
  20
  21         [CLK_DE]                = GATE(0x600, BIT(31)),
  22         [CLK_BUS_DE]            = GATE(0x60c, BIT(0)),
  23
  24         [CLK_NAND0]             = GATE(0x810, BIT(31)),
  25         [CLK_NAND1]             = GATE(0x814, BIT(31)),
  26         [CLK_BUS_NAND]          = GATE(0x82c, BIT(0)),
  27
  28         [CLK_BUS_MMC0]          = GATE(0x84c, BIT(0)),
  29         [CLK_BUS_MMC1]          = GATE(0x84c, BIT(1)),
  30         [CLK_BUS_MMC2]          = GATE(0x84c, BIT(2)),
  31         [CLK_BUS_UART0]         = GATE(0x90c, BIT(0)),
  32         [CLK_BUS_UART1]         = GATE(0x90c, BIT(1)),
  33         [CLK_BUS_UART2]         = GATE(0x90c, BIT(2)),
  34         [CLK_BUS_UART3]         = GATE(0x90c, BIT(3)),
  35
  36         [CLK_BUS_I2C0]          = GATE(0x91c, BIT(0)),
  37         [CLK_BUS_I2C1]          = GATE(0x91c, BIT(1)),
  38         [CLK_BUS_I2C2]          = GATE(0x91c, BIT(2)),
  39         [CLK_BUS_I2C3]          = GATE(0x91c, BIT(3)),
  40
  41         [CLK_SPI0]              = GATE(0x940, BIT(31)),
  42         [CLK_SPI1]              = GATE(0x944, BIT(31)),
  43
  44         [CLK_BUS_SPI0]          = GATE(0x96c, BIT(0)),
  45         [CLK_BUS_SPI1]          = GATE(0x96c, BIT(1)),
  46
  47         [CLK_BUS_EMAC]          = GATE(0x97c, BIT(0)),
  48
  49         [CLK_USB_PHY0]          = GATE(0xa70, BIT(29)),
  50         [CLK_USB_OHCI0]         = GATE(0xa70, BIT(31)),
  51
  52         [CLK_USB_PHY1]          = GATE(0xa74, BIT(29)),
  53
  54         [CLK_USB_HSIC]          = GATE(0xa7c, BIT(26)),
  55         [CLK_USB_HSIC_12M]      = GATE(0xa7c, BIT(27)),
  56         [CLK_USB_PHY3]          = GATE(0xa7c, BIT(29)),
  57         [CLK_USB_OHCI3]         = GATE(0xa7c, BIT(31)),
  58
  59         [CLK_BUS_OHCI0]         = GATE(0xa8c, BIT(0)),
  60         [CLK_BUS_OHCI3]         = GATE(0xa8c, BIT(3)),
  61         [CLK_BUS_EHCI0]         = GATE(0xa8c, BIT(4)),
  62         [CLK_BUS_XHCI]          = GATE(0xa8c, BIT(5)),
  63         [CLK_BUS_EHCI3]         = GATE(0xa8c, BIT(7)),
  64         [CLK_BUS_OTG]           = GATE(0xa8c, BIT(8)),
  65
  66         [CLK_HDMI]              = GATE(0xb00, BIT(31)),
  67         [CLK_HDMI_SLOW]         = GATE(0xb04, BIT(31)),
  68         [CLK_HDMI_CEC]          = GATE(0xb10, BIT(31)),
  69         [CLK_BUS_HDMI]          = GATE(0xb1c, BIT(0)),
  70         [CLK_BUS_TCON_TOP]      = GATE(0xb5c, BIT(0)),
  71         [CLK_TCON_LCD0]         = GATE(0xb60, BIT(31)),
  72         [CLK_BUS_TCON_LCD0]     = GATE(0xb7c, BIT(0)),
  73         [CLK_TCON_TV0]          = GATE(0xb80, BIT(31)),
  74         [CLK_BUS_TCON_TV0]      = GATE(0xb9c, BIT(0)),
  75 };
  76
  77 static struct ccu_reset h6_resets[] = {
  78         [RST_BUS_DE]            = RESET(0x60c, BIT(16)),
  79         [RST_BUS_NAND]          = RESET(0x82c, BIT(16)),
  80
  81         [RST_BUS_MMC0]          = RESET(0x84c, BIT(16)),
  82         [RST_BUS_MMC1]          = RESET(0x84c, BIT(17)),
  83         [RST_BUS_MMC2]          = RESET(0x84c, BIT(18)),
  84         [RST_BUS_UART0]         = RESET(0x90c, BIT(16)),
  85         [RST_BUS_UART1]         = RESET(0x90c, BIT(17)),
  86         [RST_BUS_UART2]         = RESET(0x90c, BIT(18)),
  87         [RST_BUS_UART3]         = RESET(0x90c, BIT(19)),
  88
  89         [RST_BUS_I2C0]          = RESET(0x91c, BIT(16)),
  90         [RST_BUS_I2C1]          = RESET(0x91c, BIT(17)),
  91         [RST_BUS_I2C2]          = RESET(0x91c, BIT(18)),
  92         [RST_BUS_I2C3]          = RESET(0x91c, BIT(19)),
  93
  94         [RST_BUS_SPI0]          = RESET(0x96c, BIT(16)),
  95         [RST_BUS_SPI1]          = RESET(0x96c, BIT(17)),
  96
  97         [RST_BUS_EMAC]          = RESET(0x97c, BIT(16)),
  98
  99         [RST_USB_PHY0]          = RESET(0xa70, BIT(30)),
 100
 101         [RST_USB_PHY1]          = RESET(0xa74, BIT(30)),
 102
 103         [RST_USB_HSIC]          = RESET(0xa7c, BIT(28)),
 104         [RST_USB_PHY3]          = RESET(0xa7c, BIT(30)),
 105
 106         [RST_BUS_OHCI0]         = RESET(0xa8c, BIT(16)),
 107         [RST_BUS_OHCI3]         = RESET(0xa8c, BIT(19)),
 108         [RST_BUS_EHCI0]         = RESET(0xa8c, BIT(20)),
 109         [RST_BUS_XHCI]          = RESET(0xa8c, BIT(21)),
 110         [RST_BUS_EHCI3]         = RESET(0xa8c, BIT(23)),
 111         [RST_BUS_OTG]           = RESET(0xa8c, BIT(24)),
 112
 113         [RST_BUS_HDMI]          = RESET(0xb1c, BIT(16)),
 114         [RST_BUS_HDMI_SUB]      = RESET(0xb1c, BIT(17)),
 115         [RST_BUS_TCON_TOP]      = RESET(0xb5c, BIT(16)),
 116         [RST_BUS_TCON_LCD0]     = RESET(0xb7c, BIT(16)),
 117         [RST_BUS_TCON_TV0]      = RESET(0xb9c, BIT(16)),
 118 };
 119
 120 const struct ccu_desc h6_ccu_desc = {
 121         .gates = h6_gates,
 122         .resets = h6_resets,
 123         .num_gates = ARRAY_SIZE(h6_gates),
 124         .num_resets = ARRAY_SIZE(h6_resets),
 125 };