2 * Copyright 2013 Emilio López
4 * Emilio López <emilio@elopez.com.ar>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
17 #include <linux/clk-provider.h>
18 #include <linux/clkdev.h>
20 #include <linux/of_address.h>
22 #include "clk-factors.h"
24 static DEFINE_SPINLOCK(clk_lock);
27 * sun4i_osc_clk_setup() - Setup function for gatable oscillator
30 #define SUNXI_OSC24M_GATE 0
32 static void __init sun4i_osc_clk_setup(struct device_node *node)
35 struct clk_fixed_rate *fixed;
36 struct clk_gate *gate;
37 const char *clk_name = node->name;
40 if (of_property_read_u32(node, "clock-frequency", &rate))
43 /* allocate fixed-rate and gate clock structs */
44 fixed = kzalloc(sizeof(struct clk_fixed_rate), GFP_KERNEL);
47 gate = kzalloc(sizeof(struct clk_gate), GFP_KERNEL);
51 /* set up gate and fixed rate properties */
52 gate->reg = of_iomap(node, 0);
53 gate->bit_idx = SUNXI_OSC24M_GATE;
54 gate->lock = &clk_lock;
55 fixed->fixed_rate = rate;
57 clk = clk_register_composite(NULL, clk_name,
60 &fixed->hw, &clk_fixed_rate_ops,
61 &gate->hw, &clk_gate_ops,
67 of_clk_add_provider(node, of_clk_src_simple_get, clk);
68 clk_register_clkdev(clk, clk_name, NULL);
77 CLK_OF_DECLARE(sun4i_osc, "allwinner,sun4i-osc-clk", sun4i_osc_clk_setup);
82 * sun4i_get_pll1_factors() - calculates n, k, m, p factors for PLL1
83 * PLL1 rate is calculated as follows
84 * rate = (parent_rate * n * (k + 1) >> p) / (m + 1);
85 * parent_rate is always 24Mhz
88 static void sun4i_get_pll1_factors(u32 *freq, u32 parent_rate,
89 u8 *n, u8 *k, u8 *m, u8 *p)
93 /* Normalize value to a 6M multiple */
94 div = *freq / 6000000;
95 *freq = 6000000 * div;
97 /* we were called to round the frequency, we can now return */
101 /* m is always zero for pll1 */
104 /* k is 1 only on these cases */
105 if (*freq >= 768000000 || *freq == 42000000 || *freq == 54000000)
110 /* p will be 3 for divs under 10 */
114 /* p will be 2 for divs between 10 - 20 and odd divs under 32 */
115 else if (div < 20 || (div < 32 && (div & 1)))
118 /* p will be 1 for even divs under 32, divs under 40 and odd pairs
119 * of divs between 40-62 */
120 else if (div < 40 || (div < 64 && (div & 2)))
123 /* any other entries have p = 0 */
127 /* calculate a suitable n based on k and p */
134 * sun6i_a31_get_pll1_factors() - calculates n, k and m factors for PLL1
135 * PLL1 rate is calculated as follows
136 * rate = parent_rate * (n + 1) * (k + 1) / (m + 1);
137 * parent_rate should always be 24MHz
139 static void sun6i_a31_get_pll1_factors(u32 *freq, u32 parent_rate,
140 u8 *n, u8 *k, u8 *m, u8 *p)
143 * We can operate only on MHz, this will make our life easier
146 u32 freq_mhz = *freq / 1000000;
147 u32 parent_freq_mhz = parent_rate / 1000000;
150 * Round down the frequency to the closest multiple of either
153 u32 round_freq_6 = round_down(freq_mhz, 6);
154 u32 round_freq_16 = round_down(freq_mhz, 16);
156 if (round_freq_6 > round_freq_16)
157 freq_mhz = round_freq_6;
159 freq_mhz = round_freq_16;
161 *freq = freq_mhz * 1000000;
164 * If the factors pointer are null, we were just called to
165 * round down the frequency.
171 /* If the frequency is a multiple of 32 MHz, k is always 3 */
172 if (!(freq_mhz % 32))
174 /* If the frequency is a multiple of 9 MHz, k is always 2 */
175 else if (!(freq_mhz % 9))
177 /* If the frequency is a multiple of 8 MHz, k is always 1 */
178 else if (!(freq_mhz % 8))
180 /* Otherwise, we don't use the k factor */
185 * If the frequency is a multiple of 2 but not a multiple of
186 * 3, m is 3. This is the first time we use 6 here, yet we
187 * will use it on several other places.
188 * We use this number because it's the lowest frequency we can
189 * generate (with n = 0, k = 0, m = 3), so every other frequency
190 * somehow relates to this frequency.
192 if ((freq_mhz % 6) == 2 || (freq_mhz % 6) == 4)
195 * If the frequency is a multiple of 6MHz, but the factor is
198 else if ((freq_mhz / 6) & 1)
200 /* Otherwise, we end up with m = 1 */
204 /* Calculate n thanks to the above factors we already got */
205 *n = freq_mhz * (*m + 1) / ((*k + 1) * parent_freq_mhz) - 1;
208 * If n end up being outbound, and that we can still decrease
211 if ((*n + 1) > 31 && (*m + 1) > 1) {
212 *n = (*n + 1) / 2 - 1;
213 *m = (*m + 1) / 2 - 1;
218 * sun4i_get_apb1_factors() - calculates m, p factors for APB1
219 * APB1 rate is calculated as follows
220 * rate = (parent_rate >> p) / (m + 1);
223 static void sun4i_get_apb1_factors(u32 *freq, u32 parent_rate,
224 u8 *n, u8 *k, u8 *m, u8 *p)
228 if (parent_rate < *freq)
231 parent_rate = (parent_rate + (*freq - 1)) / *freq;
234 if (parent_rate > 32)
237 if (parent_rate <= 4)
239 else if (parent_rate <= 8)
241 else if (parent_rate <= 16)
246 calcm = (parent_rate >> calcp) - 1;
248 *freq = (parent_rate >> calcp) / (calcm + 1);
250 /* we were called to round the frequency, we can now return */
261 * sunxi_factors_clk_setup() - Setup function for factor clocks
264 struct factors_data {
265 struct clk_factors_config *table;
266 void (*getter) (u32 *rate, u32 parent_rate, u8 *n, u8 *k, u8 *m, u8 *p);
269 static struct clk_factors_config sun4i_pll1_config = {
280 static struct clk_factors_config sun6i_a31_pll1_config = {
289 static struct clk_factors_config sun4i_apb1_config = {
296 static const struct factors_data sun4i_pll1_data __initconst = {
297 .table = &sun4i_pll1_config,
298 .getter = sun4i_get_pll1_factors,
301 static const struct factors_data sun6i_a31_pll1_data __initconst = {
302 .table = &sun6i_a31_pll1_config,
303 .getter = sun6i_a31_get_pll1_factors,
306 static const struct factors_data sun4i_apb1_data __initconst = {
307 .table = &sun4i_apb1_config,
308 .getter = sun4i_get_apb1_factors,
311 static void __init sunxi_factors_clk_setup(struct device_node *node,
312 struct factors_data *data)
315 const char *clk_name = node->name;
319 reg = of_iomap(node, 0);
321 parent = of_clk_get_parent_name(node, 0);
323 clk = clk_register_factors(NULL, clk_name, parent, 0, reg,
324 data->table, data->getter, &clk_lock);
327 of_clk_add_provider(node, of_clk_src_simple_get, clk);
328 clk_register_clkdev(clk, clk_name, NULL);
335 * sunxi_mux_clk_setup() - Setup function for muxes
338 #define SUNXI_MUX_GATE_WIDTH 2
344 static const struct mux_data sun4i_cpu_mux_data __initconst = {
348 static const struct mux_data sun6i_a31_ahb1_mux_data __initconst = {
352 static const struct mux_data sun4i_apb1_mux_data __initconst = {
356 static void __init sunxi_mux_clk_setup(struct device_node *node,
357 struct mux_data *data)
360 const char *clk_name = node->name;
361 const char *parents[5];
365 reg = of_iomap(node, 0);
367 while (i < 5 && (parents[i] = of_clk_get_parent_name(node, i)) != NULL)
370 clk = clk_register_mux(NULL, clk_name, parents, i,
371 CLK_SET_RATE_NO_REPARENT, reg,
372 data->shift, SUNXI_MUX_GATE_WIDTH,
376 of_clk_add_provider(node, of_clk_src_simple_get, clk);
377 clk_register_clkdev(clk, clk_name, NULL);
384 * sunxi_divider_clk_setup() - Setup function for simple divider clocks
393 static const struct div_data sun4i_axi_data __initconst = {
399 static const struct div_data sun4i_ahb_data __initconst = {
405 static const struct div_data sun4i_apb0_data __initconst = {
411 static const struct div_data sun6i_a31_apb2_div_data __initconst = {
417 static void __init sunxi_divider_clk_setup(struct device_node *node,
418 struct div_data *data)
421 const char *clk_name = node->name;
422 const char *clk_parent;
425 reg = of_iomap(node, 0);
427 clk_parent = of_clk_get_parent_name(node, 0);
429 clk = clk_register_divider(NULL, clk_name, clk_parent, 0,
430 reg, data->shift, data->width,
431 data->pow ? CLK_DIVIDER_POWER_OF_TWO : 0,
434 of_clk_add_provider(node, of_clk_src_simple_get, clk);
435 clk_register_clkdev(clk, clk_name, NULL);
442 * sunxi_gates_clk_setup() - Setup function for leaf gates on clocks
445 #define SUNXI_GATES_MAX_SIZE 64
448 DECLARE_BITMAP(mask, SUNXI_GATES_MAX_SIZE);
451 static const struct gates_data sun4i_axi_gates_data __initconst = {
455 static const struct gates_data sun4i_ahb_gates_data __initconst = {
456 .mask = {0x7F77FFF, 0x14FB3F},
459 static const struct gates_data sun5i_a10s_ahb_gates_data __initconst = {
460 .mask = {0x147667e7, 0x185915},
463 static const struct gates_data sun5i_a13_ahb_gates_data __initconst = {
464 .mask = {0x107067e7, 0x185111},
467 static const struct gates_data sun6i_a31_ahb1_gates_data __initconst = {
468 .mask = {0xEDFE7F62, 0x794F931},
471 static const struct gates_data sun7i_a20_ahb_gates_data __initconst = {
472 .mask = { 0x12f77fff, 0x16ff3f },
475 static const struct gates_data sun4i_apb0_gates_data __initconst = {
479 static const struct gates_data sun5i_a10s_apb0_gates_data __initconst = {
483 static const struct gates_data sun5i_a13_apb0_gates_data __initconst = {
487 static const struct gates_data sun7i_a20_apb0_gates_data __initconst = {
491 static const struct gates_data sun4i_apb1_gates_data __initconst = {
495 static const struct gates_data sun5i_a10s_apb1_gates_data __initconst = {
499 static const struct gates_data sun5i_a13_apb1_gates_data __initconst = {
503 static const struct gates_data sun6i_a31_apb1_gates_data __initconst = {
507 static const struct gates_data sun6i_a31_apb2_gates_data __initconst = {
511 static const struct gates_data sun7i_a20_apb1_gates_data __initconst = {
512 .mask = { 0xff80ff },
515 static void __init sunxi_gates_clk_setup(struct device_node *node,
516 struct gates_data *data)
518 struct clk_onecell_data *clk_data;
519 const char *clk_parent;
520 const char *clk_name;
527 reg = of_iomap(node, 0);
529 clk_parent = of_clk_get_parent_name(node, 0);
531 /* Worst-case size approximation and memory allocation */
532 qty = find_last_bit(data->mask, SUNXI_GATES_MAX_SIZE);
533 clk_data = kmalloc(sizeof(struct clk_onecell_data), GFP_KERNEL);
536 clk_data->clks = kzalloc((qty+1) * sizeof(struct clk *), GFP_KERNEL);
537 if (!clk_data->clks) {
542 for_each_set_bit(i, data->mask, SUNXI_GATES_MAX_SIZE) {
543 of_property_read_string_index(node, "clock-output-names",
546 /* No driver claims this clock, but it should remain gated */
547 ignore = !strcmp("ahb_sdram", clk_name) ? CLK_IGNORE_UNUSED : 0;
549 clk_data->clks[i] = clk_register_gate(NULL, clk_name,
551 reg + 4 * (i/32), i % 32,
553 WARN_ON(IS_ERR(clk_data->clks[i]));
558 /* Adjust to the real max */
559 clk_data->clk_num = i;
561 of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
564 /* Matches for factors clocks */
565 static const struct of_device_id clk_factors_match[] __initconst = {
566 {.compatible = "allwinner,sun4i-pll1-clk", .data = &sun4i_pll1_data,},
567 {.compatible = "allwinner,sun6i-a31-pll1-clk", .data = &sun6i_a31_pll1_data,},
568 {.compatible = "allwinner,sun4i-apb1-clk", .data = &sun4i_apb1_data,},
572 /* Matches for divider clocks */
573 static const struct of_device_id clk_div_match[] __initconst = {
574 {.compatible = "allwinner,sun4i-axi-clk", .data = &sun4i_axi_data,},
575 {.compatible = "allwinner,sun4i-ahb-clk", .data = &sun4i_ahb_data,},
576 {.compatible = "allwinner,sun4i-apb0-clk", .data = &sun4i_apb0_data,},
577 {.compatible = "allwinner,sun6i-a31-apb2-div-clk", .data = &sun6i_a31_apb2_div_data,},
581 /* Matches for mux clocks */
582 static const struct of_device_id clk_mux_match[] __initconst = {
583 {.compatible = "allwinner,sun4i-cpu-clk", .data = &sun4i_cpu_mux_data,},
584 {.compatible = "allwinner,sun4i-apb1-mux-clk", .data = &sun4i_apb1_mux_data,},
585 {.compatible = "allwinner,sun6i-a31-ahb1-mux-clk", .data = &sun6i_a31_ahb1_mux_data,},
589 /* Matches for gate clocks */
590 static const struct of_device_id clk_gates_match[] __initconst = {
591 {.compatible = "allwinner,sun4i-axi-gates-clk", .data = &sun4i_axi_gates_data,},
592 {.compatible = "allwinner,sun4i-ahb-gates-clk", .data = &sun4i_ahb_gates_data,},
593 {.compatible = "allwinner,sun5i-a10s-ahb-gates-clk", .data = &sun5i_a10s_ahb_gates_data,},
594 {.compatible = "allwinner,sun5i-a13-ahb-gates-clk", .data = &sun5i_a13_ahb_gates_data,},
595 {.compatible = "allwinner,sun6i-a31-ahb1-gates-clk", .data = &sun6i_a31_ahb1_gates_data,},
596 {.compatible = "allwinner,sun7i-a20-ahb-gates-clk", .data = &sun7i_a20_ahb_gates_data,},
597 {.compatible = "allwinner,sun4i-apb0-gates-clk", .data = &sun4i_apb0_gates_data,},
598 {.compatible = "allwinner,sun5i-a10s-apb0-gates-clk", .data = &sun5i_a10s_apb0_gates_data,},
599 {.compatible = "allwinner,sun5i-a13-apb0-gates-clk", .data = &sun5i_a13_apb0_gates_data,},
600 {.compatible = "allwinner,sun7i-a20-apb0-gates-clk", .data = &sun7i_a20_apb0_gates_data,},
601 {.compatible = "allwinner,sun4i-apb1-gates-clk", .data = &sun4i_apb1_gates_data,},
602 {.compatible = "allwinner,sun5i-a10s-apb1-gates-clk", .data = &sun5i_a10s_apb1_gates_data,},
603 {.compatible = "allwinner,sun5i-a13-apb1-gates-clk", .data = &sun5i_a13_apb1_gates_data,},
604 {.compatible = "allwinner,sun6i-a31-apb1-gates-clk", .data = &sun6i_a31_apb1_gates_data,},
605 {.compatible = "allwinner,sun7i-a20-apb1-gates-clk", .data = &sun7i_a20_apb1_gates_data,},
606 {.compatible = "allwinner,sun6i-a31-apb2-gates-clk", .data = &sun6i_a31_apb2_gates_data,},
610 static void __init of_sunxi_table_clock_setup(const struct of_device_id *clk_match,
613 struct device_node *np;
614 const struct div_data *data;
615 const struct of_device_id *match;
616 void (*setup_function)(struct device_node *, const void *) = function;
618 for_each_matching_node(np, clk_match) {
619 match = of_match_node(clk_match, np);
621 setup_function(np, data);
626 * System clock protection
628 * By enabling these critical clocks, we prevent their accidental gating
631 static void __init sunxi_clock_protect(void)
635 /* memory bus clock - sun5i+ */
636 clk = clk_get(NULL, "mbus");
638 clk_prepare_enable(clk);
642 /* DDR clock - sun4i+ */
643 clk = clk_get(NULL, "pll5_ddr");
645 clk_prepare_enable(clk);
650 static void __init sunxi_init_clocks(void)
652 /* Register factor clocks */
653 of_sunxi_table_clock_setup(clk_factors_match, sunxi_factors_clk_setup);
655 /* Register divider clocks */
656 of_sunxi_table_clock_setup(clk_div_match, sunxi_divider_clk_setup);
658 /* Register mux clocks */
659 of_sunxi_table_clock_setup(clk_mux_match, sunxi_mux_clk_setup);
661 /* Register gate clocks */
662 of_sunxi_table_clock_setup(clk_gates_match, sunxi_gates_clk_setup);
664 /* Enable core system clocks */
665 sunxi_clock_protect();
667 CLK_OF_DECLARE(sun4i_a10_clk_init, "allwinner,sun4i-a10", sunxi_init_clocks);
668 CLK_OF_DECLARE(sun5i_a10s_clk_init, "allwinner,sun5i-a10s", sunxi_init_clocks);
669 CLK_OF_DECLARE(sun5i_a13_clk_init, "allwinner,sun5i-a13", sunxi_init_clocks);
670 CLK_OF_DECLARE(sun6i_a31_clk_init, "allwinner,sun6i-a31", sunxi_init_clocks);
671 CLK_OF_DECLARE(sun7i_a20_clk_init, "allwinner,sun7i-a20", sunxi_init_clocks);