2 * Copyright 2013 Emilio López
4 * Emilio López <emilio@elopez.com.ar>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
17 #include <linux/clk-provider.h>
18 #include <linux/clkdev.h>
20 #include <linux/of_address.h>
22 #include "clk-factors.h"
24 static DEFINE_SPINLOCK(clk_lock);
26 /* Maximum number of parents our clocks have */
27 #define SUNXI_MAX_PARENTS 5
30 * sun4i_osc_clk_setup() - Setup function for gatable oscillator
33 #define SUNXI_OSC24M_GATE 0
35 static void __init sun4i_osc_clk_setup(struct device_node *node)
38 struct clk_fixed_rate *fixed;
39 struct clk_gate *gate;
40 const char *clk_name = node->name;
43 if (of_property_read_u32(node, "clock-frequency", &rate))
46 /* allocate fixed-rate and gate clock structs */
47 fixed = kzalloc(sizeof(struct clk_fixed_rate), GFP_KERNEL);
50 gate = kzalloc(sizeof(struct clk_gate), GFP_KERNEL);
54 /* set up gate and fixed rate properties */
55 gate->reg = of_iomap(node, 0);
56 gate->bit_idx = SUNXI_OSC24M_GATE;
57 gate->lock = &clk_lock;
58 fixed->fixed_rate = rate;
60 clk = clk_register_composite(NULL, clk_name,
63 &fixed->hw, &clk_fixed_rate_ops,
64 &gate->hw, &clk_gate_ops,
70 of_clk_add_provider(node, of_clk_src_simple_get, clk);
71 clk_register_clkdev(clk, clk_name, NULL);
80 CLK_OF_DECLARE(sun4i_osc, "allwinner,sun4i-osc-clk", sun4i_osc_clk_setup);
85 * sun4i_get_pll1_factors() - calculates n, k, m, p factors for PLL1
86 * PLL1 rate is calculated as follows
87 * rate = (parent_rate * n * (k + 1) >> p) / (m + 1);
88 * parent_rate is always 24Mhz
91 static void sun4i_get_pll1_factors(u32 *freq, u32 parent_rate,
92 u8 *n, u8 *k, u8 *m, u8 *p)
96 /* Normalize value to a 6M multiple */
97 div = *freq / 6000000;
98 *freq = 6000000 * div;
100 /* we were called to round the frequency, we can now return */
104 /* m is always zero for pll1 */
107 /* k is 1 only on these cases */
108 if (*freq >= 768000000 || *freq == 42000000 || *freq == 54000000)
113 /* p will be 3 for divs under 10 */
117 /* p will be 2 for divs between 10 - 20 and odd divs under 32 */
118 else if (div < 20 || (div < 32 && (div & 1)))
121 /* p will be 1 for even divs under 32, divs under 40 and odd pairs
122 * of divs between 40-62 */
123 else if (div < 40 || (div < 64 && (div & 2)))
126 /* any other entries have p = 0 */
130 /* calculate a suitable n based on k and p */
137 * sun6i_a31_get_pll1_factors() - calculates n, k and m factors for PLL1
138 * PLL1 rate is calculated as follows
139 * rate = parent_rate * (n + 1) * (k + 1) / (m + 1);
140 * parent_rate should always be 24MHz
142 static void sun6i_a31_get_pll1_factors(u32 *freq, u32 parent_rate,
143 u8 *n, u8 *k, u8 *m, u8 *p)
146 * We can operate only on MHz, this will make our life easier
149 u32 freq_mhz = *freq / 1000000;
150 u32 parent_freq_mhz = parent_rate / 1000000;
153 * Round down the frequency to the closest multiple of either
156 u32 round_freq_6 = round_down(freq_mhz, 6);
157 u32 round_freq_16 = round_down(freq_mhz, 16);
159 if (round_freq_6 > round_freq_16)
160 freq_mhz = round_freq_6;
162 freq_mhz = round_freq_16;
164 *freq = freq_mhz * 1000000;
167 * If the factors pointer are null, we were just called to
168 * round down the frequency.
174 /* If the frequency is a multiple of 32 MHz, k is always 3 */
175 if (!(freq_mhz % 32))
177 /* If the frequency is a multiple of 9 MHz, k is always 2 */
178 else if (!(freq_mhz % 9))
180 /* If the frequency is a multiple of 8 MHz, k is always 1 */
181 else if (!(freq_mhz % 8))
183 /* Otherwise, we don't use the k factor */
188 * If the frequency is a multiple of 2 but not a multiple of
189 * 3, m is 3. This is the first time we use 6 here, yet we
190 * will use it on several other places.
191 * We use this number because it's the lowest frequency we can
192 * generate (with n = 0, k = 0, m = 3), so every other frequency
193 * somehow relates to this frequency.
195 if ((freq_mhz % 6) == 2 || (freq_mhz % 6) == 4)
198 * If the frequency is a multiple of 6MHz, but the factor is
201 else if ((freq_mhz / 6) & 1)
203 /* Otherwise, we end up with m = 1 */
207 /* Calculate n thanks to the above factors we already got */
208 *n = freq_mhz * (*m + 1) / ((*k + 1) * parent_freq_mhz) - 1;
211 * If n end up being outbound, and that we can still decrease
214 if ((*n + 1) > 31 && (*m + 1) > 1) {
215 *n = (*n + 1) / 2 - 1;
216 *m = (*m + 1) / 2 - 1;
221 * sun4i_get_apb1_factors() - calculates m, p factors for APB1
222 * APB1 rate is calculated as follows
223 * rate = (parent_rate >> p) / (m + 1);
226 static void sun4i_get_apb1_factors(u32 *freq, u32 parent_rate,
227 u8 *n, u8 *k, u8 *m, u8 *p)
231 if (parent_rate < *freq)
234 parent_rate = (parent_rate + (*freq - 1)) / *freq;
237 if (parent_rate > 32)
240 if (parent_rate <= 4)
242 else if (parent_rate <= 8)
244 else if (parent_rate <= 16)
249 calcm = (parent_rate >> calcp) - 1;
251 *freq = (parent_rate >> calcp) / (calcm + 1);
253 /* we were called to round the frequency, we can now return */
264 * sunxi_factors_clk_setup() - Setup function for factor clocks
267 #define SUNXI_FACTORS_MUX_MASK 0x3
269 struct factors_data {
272 struct clk_factors_config *table;
273 void (*getter) (u32 *rate, u32 parent_rate, u8 *n, u8 *k, u8 *m, u8 *p);
276 static struct clk_factors_config sun4i_pll1_config = {
287 static struct clk_factors_config sun6i_a31_pll1_config = {
296 static struct clk_factors_config sun4i_apb1_config = {
303 static const struct factors_data sun4i_pll1_data __initconst = {
304 .table = &sun4i_pll1_config,
305 .getter = sun4i_get_pll1_factors,
308 static const struct factors_data sun6i_a31_pll1_data __initconst = {
309 .table = &sun6i_a31_pll1_config,
310 .getter = sun6i_a31_get_pll1_factors,
313 static const struct factors_data sun4i_apb1_data __initconst = {
314 .table = &sun4i_apb1_config,
315 .getter = sun4i_get_apb1_factors,
318 static void __init sunxi_factors_clk_setup(struct device_node *node,
319 struct factors_data *data)
322 struct clk_factors *factors;
323 struct clk_gate *gate = NULL;
324 struct clk_mux *mux = NULL;
325 struct clk_hw *gate_hw = NULL;
326 struct clk_hw *mux_hw = NULL;
327 const char *clk_name = node->name;
328 const char *parents[SUNXI_MAX_PARENTS];
332 reg = of_iomap(node, 0);
334 /* if we have a mux, we will have >1 parents */
335 while (i < SUNXI_MAX_PARENTS &&
336 (parents[i] = of_clk_get_parent_name(node, i)) != NULL)
339 factors = kzalloc(sizeof(struct clk_factors), GFP_KERNEL);
343 /* Add a gate if this factor clock can be gated */
345 gate = kzalloc(sizeof(struct clk_gate), GFP_KERNEL);
351 /* set up gate properties */
353 gate->bit_idx = data->enable;
354 gate->lock = &clk_lock;
358 /* Add a mux if this factor clock can be muxed */
360 mux = kzalloc(sizeof(struct clk_mux), GFP_KERNEL);
367 /* set up gate properties */
369 mux->shift = data->mux;
370 mux->mask = SUNXI_FACTORS_MUX_MASK;
371 mux->lock = &clk_lock;
375 /* set up factors properties */
377 factors->config = data->table;
378 factors->get_factors = data->getter;
379 factors->lock = &clk_lock;
381 clk = clk_register_composite(NULL, clk_name,
383 mux_hw, &clk_mux_ops,
384 &factors->hw, &clk_factors_ops,
385 gate_hw, &clk_gate_ops,
386 i ? 0 : CLK_IS_ROOT);
389 of_clk_add_provider(node, of_clk_src_simple_get, clk);
390 clk_register_clkdev(clk, clk_name, NULL);
397 * sunxi_mux_clk_setup() - Setup function for muxes
400 #define SUNXI_MUX_GATE_WIDTH 2
406 static const struct mux_data sun4i_cpu_mux_data __initconst = {
410 static const struct mux_data sun6i_a31_ahb1_mux_data __initconst = {
414 static const struct mux_data sun4i_apb1_mux_data __initconst = {
418 static void __init sunxi_mux_clk_setup(struct device_node *node,
419 struct mux_data *data)
422 const char *clk_name = node->name;
423 const char *parents[5];
427 reg = of_iomap(node, 0);
429 while (i < 5 && (parents[i] = of_clk_get_parent_name(node, i)) != NULL)
432 clk = clk_register_mux(NULL, clk_name, parents, i,
433 CLK_SET_RATE_NO_REPARENT, reg,
434 data->shift, SUNXI_MUX_GATE_WIDTH,
438 of_clk_add_provider(node, of_clk_src_simple_get, clk);
439 clk_register_clkdev(clk, clk_name, NULL);
446 * sunxi_divider_clk_setup() - Setup function for simple divider clocks
455 static const struct div_data sun4i_axi_data __initconst = {
461 static const struct div_data sun4i_ahb_data __initconst = {
467 static const struct div_data sun4i_apb0_data __initconst = {
473 static const struct div_data sun6i_a31_apb2_div_data __initconst = {
479 static void __init sunxi_divider_clk_setup(struct device_node *node,
480 struct div_data *data)
483 const char *clk_name = node->name;
484 const char *clk_parent;
487 reg = of_iomap(node, 0);
489 clk_parent = of_clk_get_parent_name(node, 0);
491 clk = clk_register_divider(NULL, clk_name, clk_parent, 0,
492 reg, data->shift, data->width,
493 data->pow ? CLK_DIVIDER_POWER_OF_TWO : 0,
496 of_clk_add_provider(node, of_clk_src_simple_get, clk);
497 clk_register_clkdev(clk, clk_name, NULL);
504 * sunxi_gates_clk_setup() - Setup function for leaf gates on clocks
507 #define SUNXI_GATES_MAX_SIZE 64
510 DECLARE_BITMAP(mask, SUNXI_GATES_MAX_SIZE);
513 static const struct gates_data sun4i_axi_gates_data __initconst = {
517 static const struct gates_data sun4i_ahb_gates_data __initconst = {
518 .mask = {0x7F77FFF, 0x14FB3F},
521 static const struct gates_data sun5i_a10s_ahb_gates_data __initconst = {
522 .mask = {0x147667e7, 0x185915},
525 static const struct gates_data sun5i_a13_ahb_gates_data __initconst = {
526 .mask = {0x107067e7, 0x185111},
529 static const struct gates_data sun6i_a31_ahb1_gates_data __initconst = {
530 .mask = {0xEDFE7F62, 0x794F931},
533 static const struct gates_data sun7i_a20_ahb_gates_data __initconst = {
534 .mask = { 0x12f77fff, 0x16ff3f },
537 static const struct gates_data sun4i_apb0_gates_data __initconst = {
541 static const struct gates_data sun5i_a10s_apb0_gates_data __initconst = {
545 static const struct gates_data sun5i_a13_apb0_gates_data __initconst = {
549 static const struct gates_data sun7i_a20_apb0_gates_data __initconst = {
553 static const struct gates_data sun4i_apb1_gates_data __initconst = {
557 static const struct gates_data sun5i_a10s_apb1_gates_data __initconst = {
561 static const struct gates_data sun5i_a13_apb1_gates_data __initconst = {
565 static const struct gates_data sun6i_a31_apb1_gates_data __initconst = {
569 static const struct gates_data sun6i_a31_apb2_gates_data __initconst = {
573 static const struct gates_data sun7i_a20_apb1_gates_data __initconst = {
574 .mask = { 0xff80ff },
577 static void __init sunxi_gates_clk_setup(struct device_node *node,
578 struct gates_data *data)
580 struct clk_onecell_data *clk_data;
581 const char *clk_parent;
582 const char *clk_name;
589 reg = of_iomap(node, 0);
591 clk_parent = of_clk_get_parent_name(node, 0);
593 /* Worst-case size approximation and memory allocation */
594 qty = find_last_bit(data->mask, SUNXI_GATES_MAX_SIZE);
595 clk_data = kmalloc(sizeof(struct clk_onecell_data), GFP_KERNEL);
598 clk_data->clks = kzalloc((qty+1) * sizeof(struct clk *), GFP_KERNEL);
599 if (!clk_data->clks) {
604 for_each_set_bit(i, data->mask, SUNXI_GATES_MAX_SIZE) {
605 of_property_read_string_index(node, "clock-output-names",
608 /* No driver claims this clock, but it should remain gated */
609 ignore = !strcmp("ahb_sdram", clk_name) ? CLK_IGNORE_UNUSED : 0;
611 clk_data->clks[i] = clk_register_gate(NULL, clk_name,
613 reg + 4 * (i/32), i % 32,
615 WARN_ON(IS_ERR(clk_data->clks[i]));
620 /* Adjust to the real max */
621 clk_data->clk_num = i;
623 of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
626 /* Matches for factors clocks */
627 static const struct of_device_id clk_factors_match[] __initconst = {
628 {.compatible = "allwinner,sun4i-pll1-clk", .data = &sun4i_pll1_data,},
629 {.compatible = "allwinner,sun6i-a31-pll1-clk", .data = &sun6i_a31_pll1_data,},
630 {.compatible = "allwinner,sun4i-apb1-clk", .data = &sun4i_apb1_data,},
634 /* Matches for divider clocks */
635 static const struct of_device_id clk_div_match[] __initconst = {
636 {.compatible = "allwinner,sun4i-axi-clk", .data = &sun4i_axi_data,},
637 {.compatible = "allwinner,sun4i-ahb-clk", .data = &sun4i_ahb_data,},
638 {.compatible = "allwinner,sun4i-apb0-clk", .data = &sun4i_apb0_data,},
639 {.compatible = "allwinner,sun6i-a31-apb2-div-clk", .data = &sun6i_a31_apb2_div_data,},
643 /* Matches for mux clocks */
644 static const struct of_device_id clk_mux_match[] __initconst = {
645 {.compatible = "allwinner,sun4i-cpu-clk", .data = &sun4i_cpu_mux_data,},
646 {.compatible = "allwinner,sun4i-apb1-mux-clk", .data = &sun4i_apb1_mux_data,},
647 {.compatible = "allwinner,sun6i-a31-ahb1-mux-clk", .data = &sun6i_a31_ahb1_mux_data,},
651 /* Matches for gate clocks */
652 static const struct of_device_id clk_gates_match[] __initconst = {
653 {.compatible = "allwinner,sun4i-axi-gates-clk", .data = &sun4i_axi_gates_data,},
654 {.compatible = "allwinner,sun4i-ahb-gates-clk", .data = &sun4i_ahb_gates_data,},
655 {.compatible = "allwinner,sun5i-a10s-ahb-gates-clk", .data = &sun5i_a10s_ahb_gates_data,},
656 {.compatible = "allwinner,sun5i-a13-ahb-gates-clk", .data = &sun5i_a13_ahb_gates_data,},
657 {.compatible = "allwinner,sun6i-a31-ahb1-gates-clk", .data = &sun6i_a31_ahb1_gates_data,},
658 {.compatible = "allwinner,sun7i-a20-ahb-gates-clk", .data = &sun7i_a20_ahb_gates_data,},
659 {.compatible = "allwinner,sun4i-apb0-gates-clk", .data = &sun4i_apb0_gates_data,},
660 {.compatible = "allwinner,sun5i-a10s-apb0-gates-clk", .data = &sun5i_a10s_apb0_gates_data,},
661 {.compatible = "allwinner,sun5i-a13-apb0-gates-clk", .data = &sun5i_a13_apb0_gates_data,},
662 {.compatible = "allwinner,sun7i-a20-apb0-gates-clk", .data = &sun7i_a20_apb0_gates_data,},
663 {.compatible = "allwinner,sun4i-apb1-gates-clk", .data = &sun4i_apb1_gates_data,},
664 {.compatible = "allwinner,sun5i-a10s-apb1-gates-clk", .data = &sun5i_a10s_apb1_gates_data,},
665 {.compatible = "allwinner,sun5i-a13-apb1-gates-clk", .data = &sun5i_a13_apb1_gates_data,},
666 {.compatible = "allwinner,sun6i-a31-apb1-gates-clk", .data = &sun6i_a31_apb1_gates_data,},
667 {.compatible = "allwinner,sun7i-a20-apb1-gates-clk", .data = &sun7i_a20_apb1_gates_data,},
668 {.compatible = "allwinner,sun6i-a31-apb2-gates-clk", .data = &sun6i_a31_apb2_gates_data,},
672 static void __init of_sunxi_table_clock_setup(const struct of_device_id *clk_match,
675 struct device_node *np;
676 const struct div_data *data;
677 const struct of_device_id *match;
678 void (*setup_function)(struct device_node *, const void *) = function;
680 for_each_matching_node(np, clk_match) {
681 match = of_match_node(clk_match, np);
683 setup_function(np, data);
688 * System clock protection
690 * By enabling these critical clocks, we prevent their accidental gating
693 static void __init sunxi_clock_protect(void)
697 /* memory bus clock - sun5i+ */
698 clk = clk_get(NULL, "mbus");
700 clk_prepare_enable(clk);
704 /* DDR clock - sun4i+ */
705 clk = clk_get(NULL, "pll5_ddr");
707 clk_prepare_enable(clk);
712 static void __init sunxi_init_clocks(void)
714 /* Register factor clocks */
715 of_sunxi_table_clock_setup(clk_factors_match, sunxi_factors_clk_setup);
717 /* Register divider clocks */
718 of_sunxi_table_clock_setup(clk_div_match, sunxi_divider_clk_setup);
720 /* Register mux clocks */
721 of_sunxi_table_clock_setup(clk_mux_match, sunxi_mux_clk_setup);
723 /* Register gate clocks */
724 of_sunxi_table_clock_setup(clk_gates_match, sunxi_gates_clk_setup);
726 /* Enable core system clocks */
727 sunxi_clock_protect();
729 CLK_OF_DECLARE(sun4i_a10_clk_init, "allwinner,sun4i-a10", sunxi_init_clocks);
730 CLK_OF_DECLARE(sun5i_a10s_clk_init, "allwinner,sun5i-a10s", sunxi_init_clocks);
731 CLK_OF_DECLARE(sun5i_a13_clk_init, "allwinner,sun5i-a13", sunxi_init_clocks);
732 CLK_OF_DECLARE(sun6i_a31_clk_init, "allwinner,sun6i-a31", sunxi_init_clocks);
733 CLK_OF_DECLARE(sun7i_a20_clk_init, "allwinner,sun7i-a20", sunxi_init_clocks);