drivers/clk/stm32/clk-stm32-core.h

   1 /* SPDX-License-Identifier: GPL-2.0  */
   2 /*
   3  * Copyright (C) STMicroelectronics 2022 - All Rights Reserved
   4  * Author: Gabriel Fernandez <gabriel.fernandez@foss.st.com> for STMicroelectronics.
   5  */
   6
   7 #include <linux/clk-provider.h>
   8
   9 struct stm32_rcc_match_data;
  10
  11 struct stm32_mux_cfg {
  12         u16     offset;
  13         u8      shift;
  14         u8      width;
  15         u8      flags;
  16         u32     *table;
  17         u8      ready;
  18 };
  19
  20 struct stm32_gate_cfg {
  21         u16     offset;
  22         u8      bit_idx;
  23         u8      set_clr;
  24 };
  25
  26 struct stm32_div_cfg {
  27         u16     offset;
  28         u8      shift;
  29         u8      width;
  30         u8      flags;
  31         u8      ready;
  32         const struct clk_div_table *table;
  33 };
  34
  35 struct stm32_composite_cfg {
  36         int     mux;
  37         int     gate;
  38         int     div;
  39 };
  40
  41 #define NO_ID 0xFFFFFFFF
  42
  43 #define NO_STM32_MUX            0xFFFF
  44 #define NO_STM32_DIV            0xFFFF
  45 #define NO_STM32_GATE           0xFFFF
  46
  47 struct clock_config {
  48         unsigned long   id;
  49         int             sec_id;
  50         void            *clock_cfg;
  51
  52         struct clk_hw *(*func)(struct device *dev,
  53                                const struct stm32_rcc_match_data *data,
  54                                void __iomem *base,
  55                                spinlock_t *lock,
  56                                const struct clock_config *cfg);
  57 };
  58
  59 struct clk_stm32_clock_data {
  60         u16 *gate_cpt;
  61         const struct stm32_gate_cfg     *gates;
  62         const struct stm32_mux_cfg      *muxes;
  63         const struct stm32_div_cfg      *dividers;
  64         struct clk_hw *(*is_multi_mux)(struct clk_hw *hw);
  65 };
  66
  67 struct stm32_rcc_match_data {
  68         struct clk_hw_onecell_data      *hw_clks;
  69         unsigned int                    num_clocks;
  70         const struct clock_config       *tab_clocks;
  71         unsigned int                    maxbinding;
  72         struct clk_stm32_clock_data     *clock_data;
  73         u32                             clear_offset;
  74         int (*check_security)(void __iomem *base,
  75                               const struct clock_config *cfg);
  76         int (*multi_mux)(void __iomem *base, const struct clock_config *cfg);
  77 };
  78
  79 int stm32_rcc_reset_init(struct device *dev, const struct of_device_id *match,
  80                          void __iomem *base);
  81
  82 int stm32_rcc_init(struct device *dev, const struct of_device_id *match_data,
  83                    void __iomem *base);
  84
  85 /* MUX define */
  86 #define MUX_NO_RDY              0xFF
  87
  88 /* DIV define */
  89 #define DIV_NO_RDY              0xFF
  90
  91 /* Definition of clock structure */
  92 struct clk_stm32_mux {
  93         u16 mux_id;
  94         struct clk_hw hw;
  95         void __iomem *base;
  96         struct clk_stm32_clock_data *clock_data;
  97         spinlock_t *lock; /* spin lock */
  98 };
  99
 100 #define to_clk_stm32_mux(_hw) container_of(_hw, struct clk_stm32_mux, hw)
 101
 102 struct clk_stm32_gate {
 103         u16 gate_id;
 104         struct clk_hw hw;
 105         void __iomem *base;
 106         struct clk_stm32_clock_data *clock_data;
 107         spinlock_t *lock; /* spin lock */
 108 };
 109
 110 #define to_clk_stm32_gate(_hw) container_of(_hw, struct clk_stm32_gate, hw)
 111
 112 struct clk_stm32_div {
 113         u16 div_id;
 114         struct clk_hw hw;
 115         void __iomem *base;
 116         struct clk_stm32_clock_data *clock_data;
 117         spinlock_t *lock; /* spin lock */
 118 };
 119
 120 #define to_clk_stm32_divider(_hw) container_of(_hw, struct clk_stm32_div, hw)
 121
 122 struct clk_stm32_composite {
 123         u16 gate_id;
 124         u16 mux_id;
 125         u16 div_id;
 126         struct clk_hw hw;
 127         void __iomem *base;
 128         struct clk_stm32_clock_data *clock_data;
 129         spinlock_t *lock; /* spin lock */
 130 };
 131
 132 #define to_clk_stm32_composite(_hw) container_of(_hw, struct clk_stm32_composite, hw)
 133
 134 /* Clock operators */
 135 extern const struct clk_ops clk_stm32_mux_ops;
 136 extern const struct clk_ops clk_stm32_gate_ops;
 137 extern const struct clk_ops clk_stm32_divider_ops;
 138 extern const struct clk_ops clk_stm32_composite_ops;
 139
 140 /* Clock registering */
 141 struct clk_hw *clk_stm32_mux_register(struct device *dev,
 142                                       const struct stm32_rcc_match_data *data,
 143                                       void __iomem *base,
 144                                       spinlock_t *lock,
 145                                       const struct clock_config *cfg);
 146
 147 struct clk_hw *clk_stm32_gate_register(struct device *dev,
 148                                        const struct stm32_rcc_match_data *data,
 149                                        void __iomem *base,
 150                                        spinlock_t *lock,
 151                                        const struct clock_config *cfg);
 152
 153 struct clk_hw *clk_stm32_div_register(struct device *dev,
 154                                       const struct stm32_rcc_match_data *data,
 155                                       void __iomem *base,
 156                                       spinlock_t *lock,
 157                                       const struct clock_config *cfg);
 158
 159 struct clk_hw *clk_stm32_composite_register(struct device *dev,
 160                                             const struct stm32_rcc_match_data *data,
 161                                             void __iomem *base,
 162                                             spinlock_t *lock,
 163                                             const struct clock_config *cfg);
 164
 165 #define STM32_CLOCK_CFG(_binding, _clk, _sec_id, _struct, _register)\
 166 {\
 167         .id             = (_binding),\
 168         .sec_id         = (_sec_id),\
 169         .clock_cfg      = (_struct) {_clk},\
 170         .func           = (_register),\
 171 }
 172
 173 #define STM32_MUX_CFG(_binding, _clk, _sec_id)\
 174         STM32_CLOCK_CFG(_binding, &(_clk), _sec_id, struct clk_stm32_mux *,\
 175                         &clk_stm32_mux_register)
 176
 177 #define STM32_GATE_CFG(_binding, _clk, _sec_id)\
 178         STM32_CLOCK_CFG(_binding, &(_clk), _sec_id, struct clk_stm32_gate *,\
 179                         &clk_stm32_gate_register)
 180
 181 #define STM32_DIV_CFG(_binding, _clk, _sec_id)\
 182         STM32_CLOCK_CFG(_binding, &(_clk), _sec_id, struct clk_stm32_div *,\
 183                         &clk_stm32_div_register)
 184
 185 #define STM32_COMPOSITE_CFG(_binding, _clk, _sec_id)\
 186         STM32_CLOCK_CFG(_binding, &(_clk), _sec_id, struct clk_stm32_composite *,\
 187                         &clk_stm32_composite_register)