1 // SPDX-License-Identifier: GPL-2.0
3 * StarFive JH71X0 Clock Generator Driver
5 * Copyright (C) 2021-2022 Emil Renner Berthing <kernel@esmil.dk>
8 #include <linux/auxiliary_bus.h>
9 #include <linux/clk-provider.h>
10 #include <linux/debugfs.h>
11 #include <linux/device.h>
14 #include "clk-starfive-jh71x0.h"
16 static struct jh71x0_clk *jh71x0_clk_from(struct clk_hw *hw)
18 return container_of(hw, struct jh71x0_clk, hw);
21 static struct jh71x0_clk_priv *jh71x0_priv_from(struct jh71x0_clk *clk)
23 return container_of(clk, struct jh71x0_clk_priv, reg[clk->idx]);
26 static u32 jh71x0_clk_reg_get(struct jh71x0_clk *clk)
28 struct jh71x0_clk_priv *priv = jh71x0_priv_from(clk);
29 void __iomem *reg = priv->base + 4 * clk->idx;
31 return readl_relaxed(reg);
34 static void jh71x0_clk_reg_rmw(struct jh71x0_clk *clk, u32 mask, u32 value)
36 struct jh71x0_clk_priv *priv = jh71x0_priv_from(clk);
37 void __iomem *reg = priv->base + 4 * clk->idx;
40 spin_lock_irqsave(&priv->rmw_lock, flags);
41 value |= readl_relaxed(reg) & ~mask;
42 writel_relaxed(value, reg);
43 spin_unlock_irqrestore(&priv->rmw_lock, flags);
46 static int jh71x0_clk_enable(struct clk_hw *hw)
48 struct jh71x0_clk *clk = jh71x0_clk_from(hw);
50 jh71x0_clk_reg_rmw(clk, JH71X0_CLK_ENABLE, JH71X0_CLK_ENABLE);
54 static void jh71x0_clk_disable(struct clk_hw *hw)
56 struct jh71x0_clk *clk = jh71x0_clk_from(hw);
58 jh71x0_clk_reg_rmw(clk, JH71X0_CLK_ENABLE, 0);
61 static int jh71x0_clk_is_enabled(struct clk_hw *hw)
63 struct jh71x0_clk *clk = jh71x0_clk_from(hw);
65 return !!(jh71x0_clk_reg_get(clk) & JH71X0_CLK_ENABLE);
68 static unsigned long jh71x0_clk_recalc_rate(struct clk_hw *hw,
69 unsigned long parent_rate)
71 struct jh71x0_clk *clk = jh71x0_clk_from(hw);
72 u32 div = jh71x0_clk_reg_get(clk) & JH71X0_CLK_DIV_MASK;
74 return div ? parent_rate / div : 0;
77 static int jh71x0_clk_determine_rate(struct clk_hw *hw,
78 struct clk_rate_request *req)
80 struct jh71x0_clk *clk = jh71x0_clk_from(hw);
81 unsigned long parent = req->best_parent_rate;
82 unsigned long rate = clamp(req->rate, req->min_rate, req->max_rate);
83 unsigned long div = min_t(unsigned long, DIV_ROUND_UP(parent, rate), clk->max_div);
84 unsigned long result = parent / div;
87 * we want the result clamped by min_rate and max_rate if possible:
88 * case 1: div hits the max divider value, which means it's less than
89 * parent / rate, so the result is greater than rate and min_rate in
90 * particular. we can't do anything about result > max_rate because the
91 * divider doesn't go any further.
92 * case 2: div = DIV_ROUND_UP(parent, rate) which means the result is
93 * always lower or equal to rate and max_rate. however the result may
94 * turn out lower than min_rate, but then the next higher rate is fine:
95 * div - 1 = ceil(parent / rate) - 1 < parent / rate
97 * min_rate <= rate < parent / (div - 1)
99 if (result < req->min_rate && div > 1)
100 result = parent / (div - 1);
106 static int jh71x0_clk_set_rate(struct clk_hw *hw,
108 unsigned long parent_rate)
110 struct jh71x0_clk *clk = jh71x0_clk_from(hw);
111 unsigned long div = clamp(DIV_ROUND_CLOSEST(parent_rate, rate),
112 1UL, (unsigned long)clk->max_div);
114 jh71x0_clk_reg_rmw(clk, JH71X0_CLK_DIV_MASK, div);
118 static unsigned long jh71x0_clk_frac_recalc_rate(struct clk_hw *hw,
119 unsigned long parent_rate)
121 struct jh71x0_clk *clk = jh71x0_clk_from(hw);
122 u32 reg = jh71x0_clk_reg_get(clk);
123 unsigned long div100 = 100 * (reg & JH71X0_CLK_INT_MASK) +
124 ((reg & JH71X0_CLK_FRAC_MASK) >> JH71X0_CLK_FRAC_SHIFT);
126 return (div100 >= JH71X0_CLK_FRAC_MIN) ? 100 * parent_rate / div100 : 0;
129 static int jh71x0_clk_frac_determine_rate(struct clk_hw *hw,
130 struct clk_rate_request *req)
132 unsigned long parent100 = 100 * req->best_parent_rate;
133 unsigned long rate = clamp(req->rate, req->min_rate, req->max_rate);
134 unsigned long div100 = clamp(DIV_ROUND_CLOSEST(parent100, rate),
135 JH71X0_CLK_FRAC_MIN, JH71X0_CLK_FRAC_MAX);
136 unsigned long result = parent100 / div100;
138 /* clamp the result as in jh71x0_clk_determine_rate() above */
139 if (result > req->max_rate && div100 < JH71X0_CLK_FRAC_MAX)
140 result = parent100 / (div100 + 1);
141 if (result < req->min_rate && div100 > JH71X0_CLK_FRAC_MIN)
142 result = parent100 / (div100 - 1);
148 static int jh71x0_clk_frac_set_rate(struct clk_hw *hw,
150 unsigned long parent_rate)
152 struct jh71x0_clk *clk = jh71x0_clk_from(hw);
153 unsigned long div100 = clamp(DIV_ROUND_CLOSEST(100 * parent_rate, rate),
154 JH71X0_CLK_FRAC_MIN, JH71X0_CLK_FRAC_MAX);
155 u32 value = ((div100 % 100) << JH71X0_CLK_FRAC_SHIFT) | (div100 / 100);
157 jh71x0_clk_reg_rmw(clk, JH71X0_CLK_DIV_MASK, value);
161 static u8 jh71x0_clk_get_parent(struct clk_hw *hw)
163 struct jh71x0_clk *clk = jh71x0_clk_from(hw);
164 u32 value = jh71x0_clk_reg_get(clk);
166 return (value & JH71X0_CLK_MUX_MASK) >> JH71X0_CLK_MUX_SHIFT;
169 static int jh71x0_clk_set_parent(struct clk_hw *hw, u8 index)
171 struct jh71x0_clk *clk = jh71x0_clk_from(hw);
172 u32 value = (u32)index << JH71X0_CLK_MUX_SHIFT;
174 jh71x0_clk_reg_rmw(clk, JH71X0_CLK_MUX_MASK, value);
178 static int jh71x0_clk_mux_determine_rate(struct clk_hw *hw,
179 struct clk_rate_request *req)
181 return clk_mux_determine_rate_flags(hw, req, 0);
184 static int jh71x0_clk_get_phase(struct clk_hw *hw)
186 struct jh71x0_clk *clk = jh71x0_clk_from(hw);
187 u32 value = jh71x0_clk_reg_get(clk);
189 return (value & JH71X0_CLK_INVERT) ? 180 : 0;
192 static int jh71x0_clk_set_phase(struct clk_hw *hw, int degrees)
194 struct jh71x0_clk *clk = jh71x0_clk_from(hw);
199 else if (degrees == 180)
200 value = JH71X0_CLK_INVERT;
204 jh71x0_clk_reg_rmw(clk, JH71X0_CLK_INVERT, value);
208 #ifdef CONFIG_DEBUG_FS
209 static void jh71x0_clk_debug_init(struct clk_hw *hw, struct dentry *dentry)
211 static const struct debugfs_reg32 jh71x0_clk_reg = {
215 struct jh71x0_clk *clk = jh71x0_clk_from(hw);
216 struct jh71x0_clk_priv *priv = jh71x0_priv_from(clk);
217 struct debugfs_regset32 *regset;
219 regset = devm_kzalloc(priv->dev, sizeof(*regset), GFP_KERNEL);
223 regset->regs = &jh71x0_clk_reg;
225 regset->base = priv->base + 4 * clk->idx;
227 debugfs_create_regset32("registers", 0400, dentry, regset);
230 #define jh71x0_clk_debug_init NULL
233 static const struct clk_ops jh71x0_clk_gate_ops = {
234 .enable = jh71x0_clk_enable,
235 .disable = jh71x0_clk_disable,
236 .is_enabled = jh71x0_clk_is_enabled,
237 .debug_init = jh71x0_clk_debug_init,
240 static const struct clk_ops jh71x0_clk_div_ops = {
241 .recalc_rate = jh71x0_clk_recalc_rate,
242 .determine_rate = jh71x0_clk_determine_rate,
243 .set_rate = jh71x0_clk_set_rate,
244 .debug_init = jh71x0_clk_debug_init,
247 static const struct clk_ops jh71x0_clk_fdiv_ops = {
248 .recalc_rate = jh71x0_clk_frac_recalc_rate,
249 .determine_rate = jh71x0_clk_frac_determine_rate,
250 .set_rate = jh71x0_clk_frac_set_rate,
251 .debug_init = jh71x0_clk_debug_init,
254 static const struct clk_ops jh71x0_clk_gdiv_ops = {
255 .enable = jh71x0_clk_enable,
256 .disable = jh71x0_clk_disable,
257 .is_enabled = jh71x0_clk_is_enabled,
258 .recalc_rate = jh71x0_clk_recalc_rate,
259 .determine_rate = jh71x0_clk_determine_rate,
260 .set_rate = jh71x0_clk_set_rate,
261 .debug_init = jh71x0_clk_debug_init,
264 static const struct clk_ops jh71x0_clk_mux_ops = {
265 .determine_rate = jh71x0_clk_mux_determine_rate,
266 .set_parent = jh71x0_clk_set_parent,
267 .get_parent = jh71x0_clk_get_parent,
268 .debug_init = jh71x0_clk_debug_init,
271 static const struct clk_ops jh71x0_clk_gmux_ops = {
272 .enable = jh71x0_clk_enable,
273 .disable = jh71x0_clk_disable,
274 .is_enabled = jh71x0_clk_is_enabled,
275 .determine_rate = jh71x0_clk_mux_determine_rate,
276 .set_parent = jh71x0_clk_set_parent,
277 .get_parent = jh71x0_clk_get_parent,
278 .debug_init = jh71x0_clk_debug_init,
281 static const struct clk_ops jh71x0_clk_mdiv_ops = {
282 .recalc_rate = jh71x0_clk_recalc_rate,
283 .determine_rate = jh71x0_clk_determine_rate,
284 .get_parent = jh71x0_clk_get_parent,
285 .set_parent = jh71x0_clk_set_parent,
286 .set_rate = jh71x0_clk_set_rate,
287 .debug_init = jh71x0_clk_debug_init,
290 static const struct clk_ops jh71x0_clk_gmd_ops = {
291 .enable = jh71x0_clk_enable,
292 .disable = jh71x0_clk_disable,
293 .is_enabled = jh71x0_clk_is_enabled,
294 .recalc_rate = jh71x0_clk_recalc_rate,
295 .determine_rate = jh71x0_clk_determine_rate,
296 .get_parent = jh71x0_clk_get_parent,
297 .set_parent = jh71x0_clk_set_parent,
298 .set_rate = jh71x0_clk_set_rate,
299 .debug_init = jh71x0_clk_debug_init,
302 static const struct clk_ops jh71x0_clk_inv_ops = {
303 .get_phase = jh71x0_clk_get_phase,
304 .set_phase = jh71x0_clk_set_phase,
305 .debug_init = jh71x0_clk_debug_init,
308 const struct clk_ops *starfive_jh71x0_clk_ops(u32 max)
310 if (max & JH71X0_CLK_DIV_MASK) {
311 if (max & JH71X0_CLK_MUX_MASK) {
312 if (max & JH71X0_CLK_ENABLE)
313 return &jh71x0_clk_gmd_ops;
314 return &jh71x0_clk_mdiv_ops;
316 if (max & JH71X0_CLK_ENABLE)
317 return &jh71x0_clk_gdiv_ops;
318 if (max == JH71X0_CLK_FRAC_MAX)
319 return &jh71x0_clk_fdiv_ops;
320 return &jh71x0_clk_div_ops;
323 if (max & JH71X0_CLK_MUX_MASK) {
324 if (max & JH71X0_CLK_ENABLE)
325 return &jh71x0_clk_gmux_ops;
326 return &jh71x0_clk_mux_ops;
329 if (max & JH71X0_CLK_ENABLE)
330 return &jh71x0_clk_gate_ops;
332 return &jh71x0_clk_inv_ops;
334 EXPORT_SYMBOL_GPL(starfive_jh71x0_clk_ops);
336 #if IS_ENABLED(CONFIG_CLK_STARFIVE_JH7110_SYS)
338 static void jh7110_reset_unregister_adev(void *_adev)
340 struct auxiliary_device *adev = _adev;
342 auxiliary_device_delete(adev);
345 static void jh7110_reset_adev_release(struct device *dev)
347 struct auxiliary_device *adev = to_auxiliary_dev(dev);
349 auxiliary_device_uninit(adev);
354 int jh7110_reset_controller_register(struct jh71x0_clk_priv *priv,
355 const char *adev_name,
358 struct auxiliary_device *adev;
361 adev = kzalloc(sizeof(*adev), GFP_KERNEL);
365 adev->name = adev_name;
366 adev->dev.parent = priv->dev;
367 adev->dev.release = jh7110_reset_adev_release;
370 ret = auxiliary_device_init(adev);
376 ret = auxiliary_device_add(adev);
378 auxiliary_device_uninit(adev);
382 return devm_add_action_or_reset(priv->dev,
383 jh7110_reset_unregister_adev, adev);
385 EXPORT_SYMBOL_GPL(jh7110_reset_controller_register);