1 // SPDX-License-Identifier: GPL-2.0
3 * StarFive JH7110 sys Clock Generator Driver
5 * Copyright (C) 2022 Xingyu Wu <xingyu.wu@starfivetech.com>
9 #include <linux/clk-provider.h>
10 #include <linux/init.h>
11 #include <linux/platform_device.h>
14 #include <dt-bindings/clock/starfive-jh7110-clkgen.h>
15 #include "clk-starfive-jh7110.h"
17 static const struct jh7110_clk_data jh7110_clk_sys_data[] __initconst = {
19 JH7110__MUX(JH7110_CPU_ROOT, "cpu_root", PARENT_NUMS_2,
22 JH7110__DIV(JH7110_CPU_CORE, "cpu_core", 7, JH7110_CPU_ROOT),
23 JH7110__DIV(JH7110_CPU_BUS, "cpu_bus", 2, JH7110_CPU_CORE),
24 JH7110__MUX(JH7110_GPU_ROOT, "gpu_root", PARENT_NUMS_2,
27 JH7110_MDIV(JH7110_PERH_ROOT, "perh_root", 2, PARENT_NUMS_2,
30 JH7110__MUX(JH7110_BUS_ROOT, "bus_root", PARENT_NUMS_2,
33 JH7110__DIV(JH7110_NOCSTG_BUS, "nocstg_bus", 3, JH7110_BUS_ROOT),
34 JH7110__DIV(JH7110_AXI_CFG0, "axi_cfg0", 3, JH7110_BUS_ROOT),
35 JH7110__DIV(JH7110_STG_AXIAHB, "stg_axiahb", 2, JH7110_AXI_CFG0),
36 JH7110_GATE(JH7110_AHB0, "ahb0", CLK_IS_CRITICAL, JH7110_STG_AXIAHB),
37 JH7110_GATE(JH7110_AHB1, "ahb1", CLK_IS_CRITICAL, JH7110_STG_AXIAHB),
38 JH7110__DIV(JH7110_APB_BUS_FUNC, "apb_bus_func",
39 8, JH7110_STG_AXIAHB),
40 JH7110_GATE(JH7110_APB0, "apb0", CLK_IGNORE_UNUSED, JH7110_APB_BUS),
41 JH7110__DIV(JH7110_PLL0_DIV2, "pll0_div2", 2, JH7110_PLL0_OUT),
42 JH7110__DIV(JH7110_PLL1_DIV2, "pll1_div2", 2, JH7110_PLL1_OUT),
43 JH7110__DIV(JH7110_PLL2_DIV2, "pll2_div2", 2, JH7110_PLL2_OUT),
44 JH7110__DIV(JH7110_AUDIO_ROOT, "audio_root", 8, JH7110_PLL2_OUT),
45 JH7110__DIV(JH7110_MCLK_INNER, "mclk_inner", 64, JH7110_AUDIO_ROOT),
46 JH7110__MUX(JH7110_MCLK, "mclk", PARENT_NUMS_2,
49 JH7110_GATE(JH7110_MCLK_OUT, "mclk_out", GATE_FLAG_NORMAL,
51 JH7110_MDIV(JH7110_ISP_2X, "isp_2x", 8, PARENT_NUMS_2,
54 JH7110__DIV(JH7110_ISP_AXI, "isp_axi", 4, JH7110_ISP_2X),
55 JH7110_GDIV(JH7110_GCLK0, "gclk0", GATE_FLAG_NORMAL,
56 62, JH7110_PLL0_DIV2),
57 JH7110_GDIV(JH7110_GCLK1, "gclk1", GATE_FLAG_NORMAL,
58 62, JH7110_PLL1_DIV2),
59 JH7110_GDIV(JH7110_GCLK2, "gclk2", GATE_FLAG_NORMAL,
60 62, JH7110_PLL2_DIV2),
62 JH7110_GATE(JH7110_U7_CORE_CLK, "u0_u7mc_sft7110_core_clk",
63 CLK_IGNORE_UNUSED, JH7110_CPU_CORE),
64 JH7110_GATE(JH7110_U7_CORE_CLK1, "u0_u7mc_sft7110_core_clk1",
65 CLK_IGNORE_UNUSED, JH7110_CPU_CORE),
66 JH7110_GATE(JH7110_U7_CORE_CLK2, "u0_u7mc_sft7110_core_clk2",
67 CLK_IGNORE_UNUSED, JH7110_CPU_CORE),
68 JH7110_GATE(JH7110_U7_CORE_CLK3, "u0_u7mc_sft7110_core_clk3",
69 CLK_IGNORE_UNUSED, JH7110_CPU_CORE),
70 JH7110_GATE(JH7110_U7_CORE_CLK4, "u0_u7mc_sft7110_core_clk4",
71 CLK_IGNORE_UNUSED, JH7110_CPU_CORE),
72 JH7110_GATE(JH7110_U7_DEBUG_CLK, "u0_u7mc_sft7110_debug_clk",
73 CLK_IGNORE_UNUSED, JH7110_CPU_BUS),
74 JH7110__DIV(JH7110_U7_RTC_TOGGLE, "u0_u7mc_sft7110_rtc_toggle",
76 JH7110_GATE(JH7110_U7_TRACE_CLK0, "u0_u7mc_sft7110_trace_clk0",
77 CLK_IGNORE_UNUSED, JH7110_CPU_CORE),
78 JH7110_GATE(JH7110_U7_TRACE_CLK1, "u0_u7mc_sft7110_trace_clk1",
79 CLK_IGNORE_UNUSED, JH7110_CPU_CORE),
80 JH7110_GATE(JH7110_U7_TRACE_CLK2, "u0_u7mc_sft7110_trace_clk2",
81 CLK_IGNORE_UNUSED, JH7110_CPU_CORE),
82 JH7110_GATE(JH7110_U7_TRACE_CLK3, "u0_u7mc_sft7110_trace_clk3",
83 CLK_IGNORE_UNUSED, JH7110_CPU_CORE),
84 JH7110_GATE(JH7110_U7_TRACE_CLK4, "u0_u7mc_sft7110_trace_clk4",
85 CLK_IGNORE_UNUSED, JH7110_CPU_CORE),
86 JH7110_GATE(JH7110_U7_TRACE_COM_CLK, "u0_u7mc_sft7110_trace_com_clk",
87 CLK_IGNORE_UNUSED, JH7110_CPU_BUS),
89 JH7110_GATE(JH7110_NOC_BUS_CLK_CPU_AXI,
90 "u0_sft7110_noc_bus_clk_cpu_axi",
91 CLK_IS_CRITICAL, JH7110_CPU_BUS),
92 JH7110_GATE(JH7110_NOC_BUS_CLK_AXICFG0_AXI,
93 "u0_sft7110_noc_bus_clk_axicfg0_axi",
94 CLK_IS_CRITICAL, JH7110_AXI_CFG0),
96 JH7110__DIV(JH7110_OSC_DIV2, "osc_div2", 2, JH7110_OSC),
97 JH7110__DIV(JH7110_PLL1_DIV4, "pll1_div4", 2, JH7110_PLL1_DIV2),
98 JH7110__DIV(JH7110_PLL1_DIV8, "pll1_div8", 2, JH7110_PLL1_DIV4),
99 JH7110__MUX(JH7110_DDR_BUS, "ddr_bus", PARENT_NUMS_4,
104 JH7110_GATE(JH7110_DDR_CLK_AXI, "u0_ddr_sft7110_clk_axi",
105 CLK_IGNORE_UNUSED, JH7110_DDR_BUS),
107 JH7110__DIV(JH7110_GPU_CORE, "gpu_core", 7, JH7110_GPU_ROOT),
108 JH7110_GATE(JH7110_GPU_CORE_CLK, "u0_img_gpu_core_clk",
109 GATE_FLAG_NORMAL, JH7110_GPU_CORE),
110 JH7110_GATE(JH7110_GPU_SYS_CLK, "u0_img_gpu_sys_clk",
111 GATE_FLAG_NORMAL, JH7110_AXI_CFG1),
112 JH7110_GATE(JH7110_GPU_CLK_APB, "u0_img_gpu_clk_apb",
113 GATE_FLAG_NORMAL, JH7110_APB12),
114 JH7110_GDIV(JH7110_GPU_RTC_TOGGLE, "u0_img_gpu_rtc_toggle",
115 GATE_FLAG_NORMAL, 12, JH7110_OSC),
116 JH7110_GATE(JH7110_NOC_BUS_CLK_GPU_AXI,
117 "u0_sft7110_noc_bus_clk_gpu_axi",
118 GATE_FLAG_NORMAL, JH7110_GPU_CORE),
120 JH7110_GATE(JH7110_ISP_TOP_CLK_ISPCORE_2X,
121 "u0_dom_isp_top_clk_dom_isp_top_clk_ispcore_2x",
122 GATE_FLAG_NORMAL, JH7110_ISP_2X),
123 JH7110_GATE(JH7110_ISP_TOP_CLK_ISP_AXI,
124 "u0_dom_isp_top_clk_dom_isp_top_clk_isp_axi",
125 GATE_FLAG_NORMAL, JH7110_ISP_AXI),
126 JH7110_GATE(JH7110_NOC_BUS_CLK_ISP_AXI,
127 "u0_sft7110_noc_bus_clk_isp_axi",
128 CLK_IGNORE_UNUSED, JH7110_ISP_AXI),
130 JH7110__DIV(JH7110_HIFI4_CORE, "hifi4_core", 15, JH7110_BUS_ROOT),
131 JH7110__DIV(JH7110_HIFI4_AXI, "hifi4_axi", 2, JH7110_HIFI4_CORE),
133 JH7110_GATE(JH7110_AXI_CFG1_DEC_CLK_MAIN, "u0_axi_cfg1_dec_clk_main",
134 CLK_IGNORE_UNUSED, JH7110_AXI_CFG1),
135 JH7110_GATE(JH7110_AXI_CFG1_DEC_CLK_AHB, "u0_axi_cfg1_dec_clk_ahb",
136 CLK_IGNORE_UNUSED, JH7110_AHB0),
138 JH7110_GATE(JH7110_VOUT_SRC,
139 "u0_dom_vout_top_clk_dom_vout_top_clk_vout_src",
140 GATE_FLAG_NORMAL, JH7110_VOUT_ROOT),
141 JH7110__DIV(JH7110_VOUT_AXI, "vout_axi", 7, JH7110_VOUT_ROOT),
142 JH7110_GATE(JH7110_NOC_BUS_CLK_DISP_AXI,
143 "u0_sft7110_noc_bus_clk_disp_axi",
144 GATE_FLAG_NORMAL, JH7110_VOUT_AXI),
145 JH7110_GATE(JH7110_VOUT_TOP_CLK_VOUT_AHB,
146 "u0_dom_vout_top_clk_dom_vout_top_clk_vout_ahb",
147 GATE_FLAG_NORMAL, JH7110_AHB1),
148 JH7110_GATE(JH7110_VOUT_TOP_CLK_VOUT_AXI,
149 "u0_dom_vout_top_clk_dom_vout_top_clk_vout_axi",
150 GATE_FLAG_NORMAL, JH7110_VOUT_AXI),
151 JH7110_GATE(JH7110_VOUT_TOP_CLK_HDMITX0_MCLK,
152 "u0_dom_vout_top_clk_dom_vout_top_clk_hdmitx0_mclk",
153 GATE_FLAG_NORMAL, JH7110_MCLK),
154 JH7110__DIV(JH7110_VOUT_TOP_CLK_MIPIPHY_REF,
155 "u0_dom_vout_top_clk_dom_vout_top_clk_mipiphy_ref",
158 JH7110__DIV(JH7110_JPEGC_AXI, "jpegc_axi", 16, JH7110_VENC_ROOT),
159 JH7110_GATE(JH7110_CODAJ12_CLK_AXI, "u0_CODAJ12_clk_axi",
160 GATE_FLAG_NORMAL, JH7110_JPEGC_AXI),
161 JH7110_GDIV(JH7110_CODAJ12_CLK_CORE, "u0_CODAJ12_clk_core",
162 GATE_FLAG_NORMAL, 16, JH7110_VENC_ROOT),
163 JH7110_GATE(JH7110_CODAJ12_CLK_APB, "u0_CODAJ12_clk_apb",
164 GATE_FLAG_NORMAL, JH7110_APB12),
166 JH7110__DIV(JH7110_VDEC_AXI, "vdec_axi", 7, JH7110_BUS_ROOT),
167 JH7110_GATE(JH7110_WAVE511_CLK_AXI, "u0_WAVE511_clk_axi",
168 GATE_FLAG_NORMAL, JH7110_VDEC_AXI),
169 JH7110_GDIV(JH7110_WAVE511_CLK_BPU, "u0_WAVE511_clk_bpu",
170 GATE_FLAG_NORMAL, 7, JH7110_BUS_ROOT),
171 JH7110_GDIV(JH7110_WAVE511_CLK_VCE, "u0_WAVE511_clk_vce",
172 GATE_FLAG_NORMAL, 7, JH7110_VDEC_ROOT),
173 JH7110_GATE(JH7110_WAVE511_CLK_APB, "u0_WAVE511_clk_apb",
174 GATE_FLAG_NORMAL, JH7110_APB12),
175 JH7110_GATE(JH7110_VDEC_JPG_ARB_JPGCLK, "u0_vdec_jpg_arb_jpgclk",
176 CLK_IGNORE_UNUSED, JH7110_JPEGC_AXI),
177 JH7110_GATE(JH7110_VDEC_JPG_ARB_MAINCLK, "u0_vdec_jpg_arb_mainclk",
178 CLK_IGNORE_UNUSED, JH7110_VDEC_AXI),
179 JH7110_GATE(JH7110_NOC_BUS_CLK_VDEC_AXI,
180 "u0_sft7110_noc_bus_clk_vdec_axi",
181 GATE_FLAG_NORMAL, JH7110_VDEC_AXI),
183 JH7110__DIV(JH7110_VENC_AXI, "venc_axi", 15, JH7110_VENC_ROOT),
184 JH7110_GATE(JH7110_WAVE420L_CLK_AXI, "u0_wave420l_clk_axi",
185 GATE_FLAG_NORMAL, JH7110_VENC_AXI),
186 JH7110_GDIV(JH7110_WAVE420L_CLK_BPU, "u0_wave420l_clk_bpu",
187 GATE_FLAG_NORMAL, 15, JH7110_VENC_ROOT),
188 JH7110_GDIV(JH7110_WAVE420L_CLK_VCE, "u0_wave420l_clk_vce",
189 GATE_FLAG_NORMAL, 15, JH7110_VENC_ROOT),
190 JH7110_GATE(JH7110_WAVE420L_CLK_APB, "u0_wave420l_clk_apb",
191 GATE_FLAG_NORMAL, JH7110_APB12),
192 JH7110_GATE(JH7110_NOC_BUS_CLK_VENC_AXI,
193 "u0_sft7110_noc_bus_clk_venc_axi",
194 GATE_FLAG_NORMAL, JH7110_VENC_AXI),
196 JH7110_GATE(JH7110_AXI_CFG0_DEC_CLK_MAIN_DIV,
197 "u0_axi_cfg0_dec_clk_main_div",
198 CLK_IGNORE_UNUSED, JH7110_AHB1),
199 JH7110_GATE(JH7110_AXI_CFG0_DEC_CLK_MAIN, "u0_axi_cfg0_dec_clk_main",
200 CLK_IGNORE_UNUSED, JH7110_AXI_CFG0),
201 JH7110_GATE(JH7110_AXI_CFG0_DEC_CLK_HIFI4, "u0_axi_cfg0_dec_clk_hifi4",
202 CLK_IGNORE_UNUSED, JH7110_HIFI4_AXI),
203 JH7110_GATE(JH7110_AXIMEM2_128B_CLK_AXI, "u2_aximem_128b_clk_axi",
204 CLK_IGNORE_UNUSED, JH7110_AXI_CFG0),
206 JH7110_GATE(JH7110_QSPI_CLK_AHB, "u0_cdns_qspi_clk_ahb",
207 CLK_IGNORE_UNUSED, JH7110_AHB1),
208 JH7110_GATE(JH7110_QSPI_CLK_APB, "u0_cdns_qspi_clk_apb",
209 CLK_IGNORE_UNUSED, JH7110_APB12),
210 JH7110__DIV(JH7110_QSPI_REF_SRC, "u0_cdns_qspi_ref_src",
211 16, JH7110_GMACUSB_ROOT),
212 JH7110_GMUX(JH7110_QSPI_CLK_REF, "u0_cdns_qspi_clk_ref",
213 CLK_IGNORE_UNUSED, PARENT_NUMS_2,
215 JH7110_QSPI_REF_SRC),
217 JH7110_GATE(JH7110_SDIO0_CLK_AHB, "u0_dw_sdio_clk_ahb",
218 CLK_IGNORE_UNUSED, JH7110_AHB0),
219 JH7110_GATE(JH7110_SDIO1_CLK_AHB, "u1_dw_sdio_clk_ahb",
220 CLK_IGNORE_UNUSED, JH7110_AHB0),
221 JH7110_GDIV(JH7110_SDIO0_CLK_SDCARD, "u0_dw_sdio_clk_sdcard",
222 CLK_IGNORE_UNUSED, 15, JH7110_AXI_CFG0),
223 JH7110_GDIV(JH7110_SDIO1_CLK_SDCARD, "u1_dw_sdio_clk_sdcard",
224 CLK_IGNORE_UNUSED, 15, JH7110_AXI_CFG0),
226 JH7110__DIV(JH7110_USB_125M, "usb_125m", 15, JH7110_GMACUSB_ROOT),
227 JH7110_GATE(JH7110_NOC_BUS_CLK_STG_AXI,
228 "u0_sft7110_noc_bus_clk_stg_axi",
229 CLK_IGNORE_UNUSED, JH7110_NOCSTG_BUS),
231 JH7110_GATE(JH7110_GMAC5_CLK_AHB, "u1_dw_gmac5_axi64_clk_ahb",
232 GATE_FLAG_NORMAL, JH7110_AHB0),
233 JH7110_GATE(JH7110_GMAC5_CLK_AXI, "u1_dw_gmac5_axi64_clk_axi",
234 GATE_FLAG_NORMAL, JH7110_STG_AXIAHB),
235 JH7110__DIV(JH7110_GMAC_SRC, "gmac_src", 7, JH7110_GMACUSB_ROOT),
236 JH7110__DIV(JH7110_GMAC1_GTXCLK, "gmac1_gtxclk",
237 15, JH7110_GMACUSB_ROOT),
238 JH7110__DIV(JH7110_GMAC1_RMII_RTX, "gmac1_rmii_rtx",
239 30, JH7110_GMAC1_RMII_REFIN),
240 JH7110_GDIV(JH7110_GMAC5_CLK_PTP, "u1_dw_gmac5_axi64_clk_ptp",
241 GATE_FLAG_NORMAL, 31, JH7110_GMAC_SRC),
242 JH7110__MUX(JH7110_GMAC5_CLK_RX, "u1_dw_gmac5_axi64_clk_rx",
244 JH7110_GMAC1_RGMII_RXIN,
245 JH7110_GMAC1_RMII_RTX),
246 JH7110__INV(JH7110_GMAC5_CLK_RX_INV, "u1_dw_gmac5_axi64_clk_rx_inv",
247 JH7110_GMAC5_CLK_RX),
248 JH7110_GMUX(JH7110_GMAC5_CLK_TX, "u1_dw_gmac5_axi64_clk_tx",
249 GATE_FLAG_NORMAL, PARENT_NUMS_2,
251 JH7110_GMAC1_RMII_RTX),
252 JH7110__INV(JH7110_GMAC5_CLK_TX_INV, "u1_dw_gmac5_axi64_clk_tx_inv",
253 JH7110_GMAC5_CLK_TX),
254 JH7110_GATE(JH7110_GMAC1_GTXC, "gmac1_gtxc",
255 GATE_FLAG_NORMAL, JH7110_GMAC1_GTXCLK),
257 JH7110_GDIV(JH7110_GMAC0_GTXCLK, "gmac0_gtxclk",
258 GATE_FLAG_NORMAL, 15, JH7110_GMACUSB_ROOT),
259 JH7110_GDIV(JH7110_GMAC0_PTP, "gmac0_ptp",
260 GATE_FLAG_NORMAL, 31, JH7110_GMAC_SRC),
261 JH7110_GDIV(JH7110_GMAC_PHY, "gmac_phy",
262 GATE_FLAG_NORMAL, 31, JH7110_GMAC_SRC),
263 JH7110_GATE(JH7110_GMAC0_GTXC, "gmac0_gtxc",
264 GATE_FLAG_NORMAL, JH7110_GMAC0_GTXCLK),
266 JH7110_GATE(JH7110_SYS_IOMUX_PCLK, "u0_sys_iomux_pclk",
267 CLK_IGNORE_UNUSED, JH7110_APB12),
268 JH7110_GATE(JH7110_MAILBOX_CLK_APB, "u0_mailbox_clk_apb",
269 CLK_IGNORE_UNUSED, JH7110_APB12),
270 JH7110_GATE(JH7110_INT_CTRL_CLK_APB, "u0_int_ctrl_clk_apb",
271 CLK_IGNORE_UNUSED, JH7110_APB12),
273 JH7110_GATE(JH7110_CAN0_CTRL_CLK_APB, "u0_can_ctrl_clk_apb",
274 GATE_FLAG_NORMAL, JH7110_APB12),
275 JH7110_GDIV(JH7110_CAN0_CTRL_CLK_TIMER, "u0_can_ctrl_clk_timer",
276 GATE_FLAG_NORMAL, 24, JH7110_OSC),
277 JH7110_GDIV(JH7110_CAN0_CTRL_CLK_CAN, "u0_can_ctrl_clk_can",
278 GATE_FLAG_NORMAL, 63, JH7110_PERH_ROOT),
279 JH7110_GATE(JH7110_CAN1_CTRL_CLK_APB, "u1_can_ctrl_clk_apb",
280 GATE_FLAG_NORMAL, JH7110_APB12),
281 JH7110_GDIV(JH7110_CAN1_CTRL_CLK_TIMER, "u1_can_ctrl_clk_timer",
282 GATE_FLAG_NORMAL, 24, JH7110_OSC),
283 JH7110_GDIV(JH7110_CAN1_CTRL_CLK_CAN, "u1_can_ctrl_clk_can",
284 GATE_FLAG_NORMAL, 63, JH7110_PERH_ROOT),
286 JH7110_GATE(JH7110_PWM_CLK_APB, "u0_pwm_8ch_clk_apb",
287 GATE_FLAG_NORMAL, JH7110_APB12),
289 JH7110_GATE(JH7110_DSKIT_WDT_CLK_APB, "u0_dskit_wdt_clk_apb",
290 CLK_IGNORE_UNUSED, JH7110_APB12),
291 JH7110_GATE(JH7110_DSKIT_WDT_CLK_WDT, "u0_dskit_wdt_clk_wdt",
292 CLK_IGNORE_UNUSED, JH7110_OSC),
294 JH7110_GATE(JH7110_TIMER_CLK_APB, "u0_si5_timer_clk_apb",
295 CLK_IGNORE_UNUSED, JH7110_APB12),
296 JH7110_GATE(JH7110_TIMER_CLK_TIMER0, "u0_si5_timer_clk_timer0",
297 CLK_IGNORE_UNUSED, JH7110_OSC),
298 JH7110_GATE(JH7110_TIMER_CLK_TIMER1, "u0_si5_timer_clk_timer1",
299 CLK_IGNORE_UNUSED, JH7110_OSC),
300 JH7110_GATE(JH7110_TIMER_CLK_TIMER2, "u0_si5_timer_clk_timer2",
301 CLK_IGNORE_UNUSED, JH7110_OSC),
302 JH7110_GATE(JH7110_TIMER_CLK_TIMER3, "u0_si5_timer_clk_timer3",
303 CLK_IGNORE_UNUSED, JH7110_OSC),
305 JH7110_GATE(JH7110_TEMP_SENSOR_CLK_APB, "u0_temp_sensor_clk_apb",
306 GATE_FLAG_NORMAL, JH7110_APB12),
307 JH7110_GDIV(JH7110_TEMP_SENSOR_CLK_TEMP, "u0_temp_sensor_clk_temp",
308 GATE_FLAG_NORMAL, 24, JH7110_OSC),
310 JH7110_GATE(JH7110_SPI0_CLK_APB, "u0_ssp_spi_clk_apb",
311 GATE_FLAG_NORMAL, JH7110_APB0),
312 JH7110_GATE(JH7110_SPI1_CLK_APB, "u1_ssp_spi_clk_apb",
313 GATE_FLAG_NORMAL, JH7110_APB0),
314 JH7110_GATE(JH7110_SPI2_CLK_APB, "u2_ssp_spi_clk_apb",
315 GATE_FLAG_NORMAL, JH7110_APB0),
316 JH7110_GATE(JH7110_SPI3_CLK_APB, "u3_ssp_spi_clk_apb",
317 GATE_FLAG_NORMAL, JH7110_APB12),
318 JH7110_GATE(JH7110_SPI4_CLK_APB, "u4_ssp_spi_clk_apb",
319 GATE_FLAG_NORMAL, JH7110_APB12),
320 JH7110_GATE(JH7110_SPI5_CLK_APB, "u5_ssp_spi_clk_apb",
321 GATE_FLAG_NORMAL, JH7110_APB12),
322 JH7110_GATE(JH7110_SPI6_CLK_APB, "u6_ssp_spi_clk_apb",
323 GATE_FLAG_NORMAL, JH7110_APB12),
325 JH7110_GATE(JH7110_I2C0_CLK_APB, "u0_dw_i2c_clk_apb",
326 GATE_FLAG_NORMAL, JH7110_APB0),
327 JH7110_GATE(JH7110_I2C1_CLK_APB, "u1_dw_i2c_clk_apb",
328 GATE_FLAG_NORMAL, JH7110_APB0),
329 JH7110_GATE(JH7110_I2C2_CLK_APB, "u2_dw_i2c_clk_apb",
330 GATE_FLAG_NORMAL, JH7110_APB0),
331 JH7110_GATE(JH7110_I2C3_CLK_APB, "u3_dw_i2c_clk_apb",
332 GATE_FLAG_NORMAL, JH7110_APB12),
333 JH7110_GATE(JH7110_I2C4_CLK_APB, "u4_dw_i2c_clk_apb",
334 GATE_FLAG_NORMAL, JH7110_APB12),
335 JH7110_GATE(JH7110_I2C5_CLK_APB, "u5_dw_i2c_clk_apb",
336 GATE_FLAG_NORMAL, JH7110_APB12),
337 JH7110_GATE(JH7110_I2C6_CLK_APB, "u6_dw_i2c_clk_apb",
338 GATE_FLAG_NORMAL, JH7110_APB12),
340 JH7110_GATE(JH7110_UART0_CLK_APB, "u0_dw_uart_clk_apb",
341 CLK_IGNORE_UNUSED, JH7110_APB0),
342 JH7110_GATE(JH7110_UART0_CLK_CORE, "u0_dw_uart_clk_core",
343 CLK_IGNORE_UNUSED, JH7110_OSC),
344 JH7110_GATE(JH7110_UART1_CLK_APB, "u1_dw_uart_clk_apb",
345 GATE_FLAG_NORMAL, JH7110_APB0),
346 JH7110_GATE(JH7110_UART1_CLK_CORE, "u1_dw_uart_clk_core",
347 GATE_FLAG_NORMAL, JH7110_OSC),
348 JH7110_GATE(JH7110_UART2_CLK_APB, "u2_dw_uart_clk_apb",
349 GATE_FLAG_NORMAL, JH7110_APB0),
350 JH7110_GATE(JH7110_UART2_CLK_CORE, "u2_dw_uart_clk_core",
351 GATE_FLAG_NORMAL, JH7110_OSC),
352 JH7110_GATE(JH7110_UART3_CLK_APB, "u3_dw_uart_clk_apb",
353 GATE_FLAG_NORMAL, JH7110_APB0),
354 JH7110_GDIV(JH7110_UART3_CLK_CORE, "u3_dw_uart_clk_core",
355 GATE_FLAG_NORMAL, 10, JH7110_PERH_ROOT),
356 JH7110_GATE(JH7110_UART4_CLK_APB, "u4_dw_uart_clk_apb",
357 GATE_FLAG_NORMAL, JH7110_APB0),
358 JH7110_GDIV(JH7110_UART4_CLK_CORE, "u4_dw_uart_clk_core",
359 GATE_FLAG_NORMAL, 10, JH7110_PERH_ROOT),
360 JH7110_GATE(JH7110_UART5_CLK_APB, "u5_dw_uart_clk_apb",
361 GATE_FLAG_NORMAL, JH7110_APB0),
362 JH7110_GDIV(JH7110_UART5_CLK_CORE, "u5_dw_uart_clk_core",
363 GATE_FLAG_NORMAL, 10, JH7110_PERH_ROOT),
365 JH7110_GATE(JH7110_PWMDAC_CLK_APB, "u0_pwmdac_clk_apb",
366 GATE_FLAG_NORMAL, JH7110_APB0),
367 JH7110_GDIV(JH7110_PWMDAC_CLK_CORE, "u0_pwmdac_clk_core",
368 GATE_FLAG_NORMAL, 256, JH7110_AUDIO_ROOT),
370 JH7110_GATE(JH7110_SPDIF_CLK_APB, "u0_cdns_spdif_clk_apb",
371 GATE_FLAG_NORMAL, JH7110_APB0),
372 JH7110_GATE(JH7110_SPDIF_CLK_CORE, "u0_cdns_spdif_clk_core",
373 GATE_FLAG_NORMAL, JH7110_MCLK),
375 JH7110_GATE(JH7110_I2STX0_4CHCLK_APB, "u0_i2stx_4ch_clk_apb",
376 GATE_FLAG_NORMAL, JH7110_APB0),
377 JH7110_GDIV(JH7110_I2STX_4CH0_BCLK_MST, "i2stx_4ch0_bclk_mst",
378 GATE_FLAG_NORMAL, 32, JH7110_MCLK),
379 JH7110__INV(JH7110_I2STX_4CH0_BCLK_MST_INV, "i2stx_4ch0_bclk_mst_inv",
380 JH7110_I2STX_4CH0_BCLK_MST),
381 JH7110_MDIV(JH7110_I2STX_4CH0_LRCK_MST, "i2stx_4ch0_lrck_mst",
383 JH7110_I2STX_4CH0_BCLK_MST_INV,
384 JH7110_I2STX_4CH0_BCLK_MST),
385 JH7110__MUX(JH7110_I2STX0_4CHBCLK, "u0_i2stx_4ch_bclk",
387 JH7110_I2STX_4CH0_BCLK_MST,
388 JH7110_I2STX_BCLK_EXT),
389 JH7110__INV(JH7110_I2STX0_4CHBCLK_N, "u0_i2stx_4ch_bclk_n",
390 JH7110_I2STX0_4CHBCLK),
391 JH7110__MUX(JH7110_I2STX0_4CHLRCK, "u0_i2stx_4ch_lrck",
393 JH7110_I2STX_4CH0_LRCK_MST,
394 JH7110_I2STX_LRCK_EXT),
396 JH7110_GATE(JH7110_I2STX1_4CHCLK_APB, "u1_i2stx_4ch_clk_apb",
397 GATE_FLAG_NORMAL, JH7110_APB0),
398 JH7110_GDIV(JH7110_I2STX_4CH1_BCLK_MST, "i2stx_4ch1_bclk_mst",
399 GATE_FLAG_NORMAL, 32, JH7110_MCLK),
400 JH7110__INV(JH7110_I2STX_4CH1_BCLK_MST_INV, "i2stx_4ch1_bclk_mst_inv",
401 JH7110_I2STX_4CH1_BCLK_MST),
402 JH7110_MDIV(JH7110_I2STX_4CH1_LRCK_MST, "i2stx_4ch1_lrck_mst",
404 JH7110_I2STX_4CH1_BCLK_MST_INV,
405 JH7110_I2STX_4CH1_BCLK_MST),
406 JH7110__MUX(JH7110_I2STX1_4CHBCLK, "u1_i2stx_4ch_bclk",
408 JH7110_I2STX_4CH1_BCLK_MST,
409 JH7110_I2STX_BCLK_EXT),
410 JH7110__INV(JH7110_I2STX1_4CHBCLK_N, "u1_i2stx_4ch_bclk_n",
411 JH7110_I2STX1_4CHBCLK),
412 JH7110__MUX(JH7110_I2STX1_4CHLRCK, "u1_i2stx_4ch_lrck",
414 JH7110_I2STX_4CH1_LRCK_MST,
415 JH7110_I2STX_LRCK_EXT),
417 JH7110_GATE(JH7110_I2SRX0_3CH_CLK_APB, "u0_i2srx_3ch_clk_apb",
418 GATE_FLAG_NORMAL, JH7110_APB0),
419 JH7110_GDIV(JH7110_I2SRX_3CH_BCLK_MST, "i2srx_3ch_bclk_mst",
420 GATE_FLAG_NORMAL, 32, JH7110_MCLK),
421 JH7110__INV(JH7110_I2SRX_3CH_BCLK_MST_INV, "i2srx_3ch_bclk_mst_inv",
422 JH7110_I2SRX_3CH_BCLK_MST),
423 JH7110_MDIV(JH7110_I2SRX_3CH_LRCK_MST, "i2srx_3ch_lrck_mst",
425 JH7110_I2SRX_3CH_BCLK_MST_INV,
426 JH7110_I2SRX_3CH_BCLK_MST),
427 JH7110__MUX(JH7110_I2SRX0_3CH_BCLK, "u0_i2srx_3ch_bclk",
429 JH7110_I2SRX_3CH_BCLK_MST,
430 JH7110_I2SRX_BCLK_EXT),
431 JH7110__INV(JH7110_I2SRX0_3CH_BCLK_N, "u0_i2srx_3ch_bclk_n",
432 JH7110_I2SRX0_3CH_BCLK),
433 JH7110__MUX(JH7110_I2SRX0_3CH_LRCK, "u0_i2srx_3ch_lrck",
435 JH7110_I2SRX_3CH_LRCK_MST,
436 JH7110_I2SRX_LRCK_EXT),
438 JH7110_GDIV(JH7110_PDM_CLK_DMIC, "u0_pdm_4mic_clk_dmic",
439 GATE_FLAG_NORMAL, 64, JH7110_MCLK),
440 JH7110_GATE(JH7110_PDM_CLK_APB, "u0_pdm_4mic_clk_apb",
441 GATE_FLAG_NORMAL, JH7110_APB0),
443 JH7110_GATE(JH7110_TDM_CLK_AHB, "u0_tdm16slot_clk_ahb",
444 GATE_FLAG_NORMAL, JH7110_AHB0),
445 JH7110_GATE(JH7110_TDM_CLK_APB, "u0_tdm16slot_clk_apb",
446 GATE_FLAG_NORMAL, JH7110_APB0),
447 JH7110_GDIV(JH7110_TDM_INTERNAL, "tdm_internal",
448 GATE_FLAG_NORMAL, 64, JH7110_MCLK),
449 JH7110__MUX(JH7110_TDM_CLK_TDM, "u0_tdm16slot_clk_tdm",
453 JH7110__INV(JH7110_TDM_CLK_TDM_N, "u0_tdm16slot_clk_tdm_n",
455 JH7110__DIV(JH7110_JTAG_CERTIFICATION_TRNG_CLK,
456 "u0_jtag_certification_trng_clk", 4, JH7110_OSC),
459 int __init clk_starfive_jh7110_sys_init(struct platform_device *pdev,
460 struct jh7110_clk_priv *priv)
465 priv->sys_base = devm_platform_ioremap_resource_byname(pdev, "sys");
466 if (IS_ERR(priv->sys_base))
467 return PTR_ERR(priv->sys_base);
469 priv->pll[PLL_OF(JH7110_PLL0_OUT)] =
470 clk_hw_register_fixed_rate(priv->dev,
471 "pll0_out", "osc", 0, 1250000000);
472 if (IS_ERR(priv->pll[PLL_OF(JH7110_PLL0_OUT)]))
473 return PTR_ERR(priv->pll[PLL_OF(JH7110_PLL0_OUT)]);
475 priv->pll[PLL_OF(JH7110_PLL1_OUT)] =
476 clk_hw_register_fixed_rate(priv->dev,
477 "pll1_out", "osc", 0, 1066000000);
478 if (IS_ERR(priv->pll[PLL_OF(JH7110_PLL1_OUT)]))
479 return PTR_ERR(priv->pll[PLL_OF(JH7110_PLL1_OUT)]);
481 priv->pll[PLL_OF(JH7110_PLL2_OUT)] =
482 clk_hw_register_fixed_rate(priv->dev,
483 "pll2_out", "osc", 0, 1228800000);
484 if (IS_ERR(priv->pll[PLL_OF(JH7110_PLL2_OUT)]))
485 return PTR_ERR(priv->pll[PLL_OF(JH7110_PLL2_OUT)]);
487 priv->pll[PLL_OF(JH7110_AON_APB)] =
488 devm_clk_hw_register_fixed_factor(priv->dev,
489 "aon_apb", "apb_bus_func", 0, 1, 1);
490 priv->pll[PLL_OF(JH7110_RESET1_CTRL_CLK_SRC)] =
491 devm_clk_hw_register_fixed_factor(priv->dev,
492 "u1_reset_ctrl_clk_src", "osc", 0, 1, 1);
493 priv->pll[PLL_OF(JH7110_DDR_ROOT)] =
494 devm_clk_hw_register_fixed_factor(priv->dev,
495 "ddr_root", "pll1_out", 0, 1, 1);
496 priv->pll[PLL_OF(JH7110_VDEC_ROOT)] =
497 devm_clk_hw_register_fixed_factor(priv->dev,
498 "vdec_root", "pll0_out", 0, 1, 1);
499 priv->pll[PLL_OF(JH7110_VENC_ROOT)] =
500 devm_clk_hw_register_fixed_factor(priv->dev,
501 "venc_root", "pll2_out", 0, 1, 1);
502 priv->pll[PLL_OF(JH7110_VOUT_ROOT)] =
503 devm_clk_hw_register_fixed_factor(priv->dev,
504 "vout_root", "pll2_out", 0, 1, 1);
505 priv->pll[PLL_OF(JH7110_GMACUSB_ROOT)] =
506 devm_clk_hw_register_fixed_factor(priv->dev,
507 "gmacusb_root", "pll0_out", 0, 1, 1);
508 priv->pll[PLL_OF(JH7110_PCLK2_MUX_FUNC_PCLK)] =
509 devm_clk_hw_register_fixed_factor(priv->dev,
510 "u2_pclk_mux_func_pclk", "apb_bus_func", 0, 1, 1);
511 priv->pll[PLL_OF(JH7110_PCLK2_MUX_BIST_PCLK)] =
512 devm_clk_hw_register_fixed_factor(priv->dev,
513 "u2_pclk_mux_bist_pclk", "bist_apb", 0, 1, 1);
514 priv->pll[PLL_OF(JH7110_APB_BUS)] =
515 devm_clk_hw_register_fixed_factor(priv->dev,
516 "apb_bus", "u2_pclk_mux_pclk", 0, 1, 1);
517 priv->pll[PLL_OF(JH7110_APB12)] =
518 devm_clk_hw_register_fixed_factor(priv->dev,
519 "apb12", "apb_bus", 0, 1, 1);
520 priv->pll[PLL_OF(JH7110_AXI_CFG1)] =
521 devm_clk_hw_register_fixed_factor(priv->dev,
522 "axi_cfg1", "isp_axi", 0, 1, 1);
523 priv->pll[PLL_OF(JH7110_PLL_WRAP_CRG_GCLK0)] =
524 devm_clk_hw_register_fixed_factor(priv->dev,
525 "u0_pll_wrap_crg_gclk0", "gclk0", 0, 1, 1);
526 priv->pll[PLL_OF(JH7110_PLL_WRAP_CRG_GCLK1)] =
527 devm_clk_hw_register_fixed_factor(priv->dev,
528 "u0_pll_wrap_crg_gclk1", "gclk1", 0, 1, 1);
529 priv->pll[PLL_OF(JH7110_PLL_WRAP_CRG_GCLK2)] =
530 devm_clk_hw_register_fixed_factor(priv->dev,
531 "u0_pll_wrap_crg_gclk2", "gclk2", 0, 1, 1);
532 priv->pll[PLL_OF(JH7110_JTAG2APB_PCLK)] =
533 devm_clk_hw_register_fixed_factor(priv->dev,
534 "u0_jtag2apb_pclk", "bist_apb", 0, 1, 1);
535 priv->pll[PLL_OF(JH7110_U7_BUS_CLK)] =
536 devm_clk_hw_register_fixed_factor(priv->dev,
537 "u0_u7mc_sft7110_bus_clk", "cpu_bus", 0, 1, 1);
538 priv->pll[PLL_OF(JH7110_U7_IRQ_SYNC_BUS_CLK)] =
539 devm_clk_hw_register_fixed_factor(priv->dev,
540 "u0_u7mc_sft7110_irq_sync_bus_clk", "cpu_bus", 0, 1, 1);
541 priv->pll[PLL_OF(JH7110_NOC_BUS_CLK2_CPU_AXI)] =
542 devm_clk_hw_register_fixed_factor(priv->dev,
543 "u0_sft7110_noc_bus_clk2_cpu_axi",
544 "u0_sft7110_noc_bus_clk_cpu_axi", 0, 1, 1);
545 priv->pll[PLL_OF(JH7110_NOC_BUS_CLK_APB_BUS)] =
546 devm_clk_hw_register_fixed_factor(priv->dev,
547 "u0_sft7110_noc_bus_clk_apb_bus", "apb_bus", 0, 1, 1);
548 priv->pll[PLL_OF(JH7110_NOC_BUS_CLK2_APB_BUS)] =
549 devm_clk_hw_register_fixed_factor(priv->dev,
550 "u0_sft7110_noc_bus_clk2_apb_bus",
551 "u0_sft7110_noc_bus_clk_apb_bus", 0, 1, 1);
552 priv->pll[PLL_OF(JH7110_NOC_BUS_CLK2_AXICFG0_AXI)] =
553 devm_clk_hw_register_fixed_factor(priv->dev,
554 "u0_sft7110_noc_bus_clk2_axicfg0_axi",
555 "u0_sft7110_noc_bus_clk_axicfg0_axi", 0, 1, 1);
556 priv->pll[PLL_OF(JH7110_DDR_CLK_DDRPHY_PLL_BYPASS)] =
557 devm_clk_hw_register_fixed_factor(priv->dev,
558 "u0_ddr_sft7110_clk_ddrphy_pll_bypass",
559 "pll1_out", 0, 1, 1);
560 priv->pll[PLL_OF(JH7110_DDR_CLK_OSC)] =
561 devm_clk_hw_register_fixed_factor(priv->dev,
562 "u0_ddr_sft7110_clk_osc", "osc", 0, 1, 1);
563 priv->pll[PLL_OF(JH7110_DDR_CLK_APB)] =
564 devm_clk_hw_register_fixed_factor(priv->dev,
565 "u0_ddr_sft7110_clk_apb", "apb12", 0, 1, 1);
566 priv->pll[PLL_OF(JH7110_NOC_BUS_CLK_DDRC)] =
567 devm_clk_hw_register_fixed_factor(priv->dev,
568 "u0_sft7110_noc_bus_clk_ddrc", "ddr_bus", 0, 1, 1);
569 priv->pll[PLL_OF(JH7110_NOC_BUS_CLK2_DDRC)] =
570 devm_clk_hw_register_fixed_factor(priv->dev,
571 "u0_sft7110_noc_bus_clk2_ddrc",
572 "u0_sft7110_noc_bus_clk_ddrc", 0, 1, 1);
573 priv->pll[PLL_OF(JH7110_SYS_AHB_DEC_CLK_AHB)] =
574 devm_clk_hw_register_fixed_factor(priv->dev,
575 "u0_saif_amba_sys_ahb_dec_clk_ahb", "ahb0", 0, 1, 1);
576 priv->pll[PLL_OF(JH7110_STG_AHB_DEC_CLK_AHB)] =
577 devm_clk_hw_register_fixed_factor(priv->dev,
578 "u0_saif_amba_stg_ahb_dec_clk_ahb", "ahb0", 0, 1, 1);
579 priv->pll[PLL_OF(JH7110_NOC_BUS_CLK2_GPU_AXI)] =
580 devm_clk_hw_register_fixed_factor(priv->dev,
581 "u0_sft7110_noc_bus_clk2_gpu_axi",
582 "u0_sft7110_noc_bus_clk_gpu_axi", 0, 1, 1);
583 priv->pll[PLL_OF(JH7110_ISP_TOP_CLK_DVP)] =
584 devm_clk_hw_register_fixed_factor(priv->dev,
585 "u0_dom_isp_top_clk_dom_isp_top_clk_dvp",
587 priv->pll[PLL_OF(JH7110_NOC_BUS_CLK2_ISP_AXI)] =
588 devm_clk_hw_register_fixed_factor(priv->dev,
589 "u0_sft7110_noc_bus_clk2_isp_axi",
590 "u0_sft7110_noc_bus_clk_isp_axi", 0, 1, 1);
591 priv->pll[PLL_OF(JH7110_ISP_TOP_CLK_BIST_APB)] =
592 devm_clk_hw_register_fixed_factor(priv->dev,
593 "u0_dom_isp_top_clk_dom_isp_top_clk_bist_apb",
594 "bist_apb", 0, 1, 1);
595 priv->pll[PLL_OF(JH7110_NOC_BUS_CLK2_DISP_AXI)] =
596 devm_clk_hw_register_fixed_factor(priv->dev,
597 "u0_sft7110_noc_bus_clk2_disp_axi",
598 "u0_sft7110_noc_bus_clk_disp_axi", 0, 1, 1);
599 priv->pll[PLL_OF(JH7110_VOUT_TOP_CLK_HDMITX0_BCLK)] =
600 devm_clk_hw_register_fixed_factor(priv->dev,
601 "u0_dom_vout_top_clk_dom_vout_top_clk_hdmitx0_bclk",
602 "u0_i2stx_4ch_bclk", 0, 1, 1);
603 priv->pll[PLL_OF(JH7110_VOUT_TOP_U0_HDMI_TX_PIN_WS)] =
604 devm_clk_hw_register_fixed_factor(priv->dev,
605 "u0_dom_vout_top_u0_hdmi_tx_pin_ws",
606 "u0_i2stx_4ch_lrck", 0, 1, 1);
607 priv->pll[PLL_OF(JH7110_VOUT_TOP_CLK_HDMIPHY_REF)] =
608 devm_clk_hw_register_fixed_factor(priv->dev,
609 "u0_dom_vout_top_clk_dom_vout_top_clk_hdmiphy_ref",
611 priv->pll[PLL_OF(JH7110_VOUT_TOP_BIST_PCLK)] =
612 devm_clk_hw_register_fixed_factor(priv->dev,
613 "u0_dom_vout_top_clk_dom_vout_top_bist_pclk",
614 "bist_apb", 0, 1, 1);
615 priv->pll[PLL_OF(JH7110_AXIMEM0_128B_CLK_AXI)] =
616 devm_clk_hw_register_fixed_factor(priv->dev,
617 "u0_aximem_128b_clk_axi",
618 "u0_WAVE511_clk_axi", 0, 1, 1);
619 priv->pll[PLL_OF(JH7110_VDEC_INTSRAM_CLK_VDEC_AXI)] =
620 devm_clk_hw_register_fixed_factor(priv->dev,
621 "u0_vdec_intsram_clk_vdec_axi",
622 "u0_aximem_128b_clk_axi", 0, 1, 1);
623 priv->pll[PLL_OF(JH7110_NOC_BUS_CLK2_VDEC_AXI)] =
624 devm_clk_hw_register_fixed_factor(priv->dev,
625 "u0_sft7110_noc_bus_clk2_vdec_axi",
626 "u0_sft7110_noc_bus_clk_vdec_axi", 0, 1, 1);
627 priv->pll[PLL_OF(JH7110_AXIMEM1_128B_CLK_AXI)] =
628 devm_clk_hw_register_fixed_factor(priv->dev,
629 "u1_aximem_128b_clk_axi",
630 "u0_wave420l_clk_axi", 0, 1, 1);
631 priv->pll[PLL_OF(JH7110_VENC_INTSRAM_CLK_VENC_AXI)] =
632 devm_clk_hw_register_fixed_factor(priv->dev,
633 "u0_venc_intsram_clk_venc_axi",
634 "u0_wave420l_clk_axi", 0, 1, 1);
635 priv->pll[PLL_OF(JH7110_NOC_BUS_CLK2_VENC_AXI)] =
636 devm_clk_hw_register_fixed_factor(priv->dev,
637 "u0_sft7110_noc_bus_clk2_venc_axi",
638 "u0_sft7110_noc_bus_clk_venc_axi", 0, 1, 1);
639 priv->pll[PLL_OF(JH7110_SRAM_CLK_ROM)] =
640 devm_clk_hw_register_fixed_factor(priv->dev,
641 "u0_intmem_rom_sram_clk_rom",
642 "u2_aximem_128b_clk_axi", 0, 1, 1);
643 priv->pll[PLL_OF(JH7110_NOC_BUS_CLK2_STG_AXI)] =
644 devm_clk_hw_register_fixed_factor(priv->dev,
645 "u0_sft7110_noc_bus_clk2_stg_axi",
646 "u0_sft7110_noc_bus_clk_stg_axi", 0, 1, 1);
647 priv->pll[PLL_OF(JH7110_GMAC5_CLK_RMII)] =
648 devm_clk_hw_register_fixed_factor(priv->dev,
649 "u1_dw_gmac5_axi64_clk_rmii",
650 "gmac1_rmii_refin", 0, 1, 1);
651 priv->pll[PLL_OF(JH7110_AON_AHB)] =
652 devm_clk_hw_register_fixed_factor(priv->dev,
653 "aon_ahb", "stg_axiahb", 0, 1, 1);
654 priv->pll[PLL_OF(JH7110_SYS_CRG_PCLK)] =
655 devm_clk_hw_register_fixed_factor(priv->dev,
656 "u0_sys_crg_pclk", "apb12", 0, 1, 1);
657 priv->pll[PLL_OF(JH7110_SYS_SYSCON_PCLK)] =
658 devm_clk_hw_register_fixed_factor(priv->dev,
659 "u0_sys_syscon_pclk", "apb12", 0, 1, 1);
660 priv->pll[PLL_OF(JH7110_SPI0_CLK_CORE)] =
661 devm_clk_hw_register_fixed_factor(priv->dev,
662 "u0_ssp_spi_clk_core", "u0_ssp_spi_clk_apb", 0, 1, 1);
663 priv->pll[PLL_OF(JH7110_SPI1_CLK_CORE)] =
664 devm_clk_hw_register_fixed_factor(priv->dev,
665 "u1_ssp_spi_clk_core", "u1_ssp_spi_clk_apb", 0, 1, 1);
666 priv->pll[PLL_OF(JH7110_SPI2_CLK_CORE)] =
667 devm_clk_hw_register_fixed_factor(priv->dev,
668 "u2_ssp_spi_clk_core", "u2_ssp_spi_clk_apb", 0, 1, 1);
669 priv->pll[PLL_OF(JH7110_SPI3_CLK_CORE)] =
670 devm_clk_hw_register_fixed_factor(priv->dev,
671 "u3_ssp_spi_clk_core", "u3_ssp_spi_clk_apb", 0, 1, 1);
672 priv->pll[PLL_OF(JH7110_SPI4_CLK_CORE)] =
673 devm_clk_hw_register_fixed_factor(priv->dev,
674 "u4_ssp_spi_clk_core", "u4_ssp_spi_clk_apb", 0, 1, 1);
675 priv->pll[PLL_OF(JH7110_SPI5_CLK_CORE)] =
676 devm_clk_hw_register_fixed_factor(priv->dev,
677 "u5_ssp_spi_clk_core", "u5_ssp_spi_clk_apb", 0, 1, 1);
678 priv->pll[PLL_OF(JH7110_SPI6_CLK_CORE)] =
679 devm_clk_hw_register_fixed_factor(priv->dev,
680 "u6_ssp_spi_clk_core", "u6_ssp_spi_clk_apb", 0, 1, 1);
681 priv->pll[PLL_OF(JH7110_I2C0_CLK_CORE)] =
682 devm_clk_hw_register_fixed_factor(priv->dev,
683 "u0_dw_i2c_clk_core", "u0_dw_i2c_clk_apb", 0, 1, 1);
684 priv->pll[PLL_OF(JH7110_I2C1_CLK_CORE)] =
685 devm_clk_hw_register_fixed_factor(priv->dev,
686 "u1_dw_i2c_clk_core", "u1_dw_i2c_clk_apb", 0, 1, 1);
687 priv->pll[PLL_OF(JH7110_I2C2_CLK_CORE)] =
688 devm_clk_hw_register_fixed_factor(priv->dev,
689 "u2_dw_i2c_clk_core", "u2_dw_i2c_clk_apb", 0, 1, 1);
690 priv->pll[PLL_OF(JH7110_I2C3_CLK_CORE)] =
691 devm_clk_hw_register_fixed_factor(priv->dev,
692 "u3_dw_i2c_clk_core", "u3_dw_i2c_clk_apb", 0, 1, 1);
693 priv->pll[PLL_OF(JH7110_I2C4_CLK_CORE)] =
694 devm_clk_hw_register_fixed_factor(priv->dev,
695 "u4_dw_i2c_clk_core", "u4_dw_i2c_clk_apb", 0, 1, 1);
696 priv->pll[PLL_OF(JH7110_I2C5_CLK_CORE)] =
697 devm_clk_hw_register_fixed_factor(priv->dev,
698 "u5_dw_i2c_clk_core", "u5_dw_i2c_clk_apb", 0, 1, 1);
699 priv->pll[PLL_OF(JH7110_I2C6_CLK_CORE)] =
700 devm_clk_hw_register_fixed_factor(priv->dev,
701 "u6_dw_i2c_clk_core", "u6_dw_i2c_clk_apb", 0, 1, 1);
702 priv->pll[PLL_OF(JH7110_I2STX_BCLK_MST)] =
703 devm_clk_hw_register_fixed_factor(priv->dev,
704 "i2stx_bclk_mst", "i2stx_4ch1_bclk_mst", 0, 1, 1);
705 priv->pll[PLL_OF(JH7110_I2STX_LRCK_MST)] =
706 devm_clk_hw_register_fixed_factor(priv->dev,
707 "i2stx_lrck_mst", "i2stx_4ch1_lrck_mst", 0, 1, 1);
708 priv->pll[PLL_OF(JH7110_I2SRX_BCLK_MST)] =
709 devm_clk_hw_register_fixed_factor(priv->dev,
710 "i2srx_bclk_mst", "i2srx_3ch_bclk_mst", 0, 1, 1);
711 priv->pll[PLL_OF(JH7110_I2SRX_LRCK_MST)] =
712 devm_clk_hw_register_fixed_factor(priv->dev,
713 "i2srx_lrck_mst", "i2srx_3ch_lrck_mst", 0, 1, 1);
714 priv->pll[PLL_OF(JH7110_PDM_CLK_DMIC0_BCLK_SLV)] =
715 devm_clk_hw_register_fixed_factor(priv->dev,
716 "u0_pdm_4mic_clk_dmic0_bclk_slv",
717 "u0_i2srx_3ch_bclk", 0, 1, 1);
718 priv->pll[PLL_OF(JH7110_PDM_CLK_DMIC0_LRCK_SLV)] =
719 devm_clk_hw_register_fixed_factor(priv->dev,
720 "u0_pdm_4mic_clk_dmic0_lrck_slv",
721 "u0_i2srx_3ch_lrck", 0, 1, 1);
722 priv->pll[PLL_OF(JH7110_PDM_CLK_DMIC1_BCLK_SLV)] =
723 devm_clk_hw_register_fixed_factor(priv->dev,
724 "u0_pdm_4mic_clk_dmic1_bclk_slv",
725 "u0_i2srx_3ch_bclk", 0, 1, 1);
726 priv->pll[PLL_OF(JH7110_PDM_CLK_DMIC1_LRCK_SLV)] =
727 devm_clk_hw_register_fixed_factor(priv->dev,
728 "u0_pdm_4mic_clk_dmic1_lrck_slv",
729 "u0_i2srx_3ch_lrck", 0, 1, 1);
730 priv->pll[PLL_OF(JH7110_TDM_CLK_MST)] =
731 devm_clk_hw_register_fixed_factor(priv->dev,
732 "tdm_clk_mst", "ahb0", 0, 1, 1);
733 priv->pll[PLL_OF(JH7110_AHB2APB_CLK_AHB)] =
734 devm_clk_hw_register_fixed_factor(priv->dev,
735 "u1_ahb2apb_clk_ahb", "tdm_internal", 0, 1, 1);
736 priv->pll[PLL_OF(JH7110_P2P_ASYNC_CLK_APBS)] =
737 devm_clk_hw_register_fixed_factor(priv->dev,
738 "u1_p2p_async_clk_apbs", "apb0", 0, 1, 1);
739 priv->pll[PLL_OF(JH7110_P2P_ASYNC_CLK_APBM)] =
740 devm_clk_hw_register_fixed_factor(priv->dev,
741 "u1_p2p_async_clk_apbm", "aon_apb", 0, 1, 1);
742 priv->pll[PLL_OF(JH7110_JTAG_DAISY_CHAIN_JTAG_TCK)] =
743 devm_clk_hw_register_fixed_factor(priv->dev,
744 "u0_jtag_daisy_chain_JTAG_TCK",
745 "jtag_tck_inner", 0, 1, 1);
746 priv->pll[PLL_OF(JH7110_U7_DEBUG_SYSTEMJTAG_JTAG_TCK)] =
747 devm_clk_hw_register_fixed_factor(priv->dev,
748 "u0_u7mc_sft7110_debug_systemjtag_jtag_TCK",
749 "u0_jtag_daisy_chain_jtag_tck_0", 0, 1, 1);
750 priv->pll[PLL_OF(JH7110_E2_DEBUG_SYSTEMJTAG_TCK)] =
751 devm_clk_hw_register_fixed_factor(priv->dev,
752 "u0_e2_sft7110_debug_systemjtag_jtag_TCK",
753 "u0_jtag_daisy_chain_jtag_tck_1", 0, 1, 1);
754 priv->pll[PLL_OF(JH7110_JTAG_CERTIFICATION_TCK)] =
755 devm_clk_hw_register_fixed_factor(priv->dev,
756 "u0_jtag_certification_tck",
757 "jtag_tck_inner", 0, 1, 1);
758 priv->pll[PLL_OF(JH7110_SEC_SKP_CLK)] =
759 devm_clk_hw_register_fixed_factor(priv->dev,
760 "u0_sec_top_skp_clk",
761 "u0_jtag_certification_trng_clk", 0, 1, 1);
762 priv->pll[PLL_OF(JH7110_U2_PCLK_MUX_PCLK)] =
763 devm_clk_hw_register_fixed_factor(priv->dev,
765 "u2_pclk_mux_func_pclk", 0, 1, 1);
768 for (idx = 0; idx < JH7110_CLK_SYS_REG_END; idx++) {
769 u32 max = jh7110_clk_sys_data[idx].max;
770 struct clk_parent_data parents[4] = {};
771 struct clk_init_data init = {
772 .name = jh7110_clk_sys_data[idx].name,
773 .ops = starfive_jh7110_clk_ops(max),
774 .parent_data = parents,
775 .num_parents = ((max & JH7110_CLK_MUX_MASK) \
776 >> JH7110_CLK_MUX_SHIFT) + 1,
777 .flags = jh7110_clk_sys_data[idx].flags,
779 struct jh7110_clk *clk = &priv->reg[idx];
782 for (i = 0; i < init.num_parents; i++) {
783 unsigned int pidx = jh7110_clk_sys_data[idx].parents[i];
785 if (pidx < JH7110_CLK_SYS_REG_END)
786 parents[i].hw = &priv->reg[pidx].hw;
787 else if ((pidx < JH7110_CLK_SYS_END) && \
788 (pidx > JH7110_CLK_SYS_REG_END))
789 parents[i].hw = priv->pll[PLL_OF(pidx)];
790 else if (pidx == JH7110_OSC)
791 parents[i].fw_name = "osc";
792 else if (pidx == JH7110_GMAC1_RMII_REFIN)
793 parents[i].fw_name = "gmac1_rmii_refin";
794 else if (pidx == JH7110_GMAC1_RGMII_RXIN)
795 parents[i].fw_name = "gmac1_rgmii_rxin";
796 else if (pidx == JH7110_I2STX_BCLK_EXT)
797 parents[i].fw_name = "i2stx_bclk_ext";
798 else if (pidx == JH7110_I2STX_LRCK_EXT)
799 parents[i].fw_name = "i2stx_lrck_ext";
800 else if (pidx == JH7110_I2SRX_BCLK_EXT)
801 parents[i].fw_name = "i2srx_bclk_ext";
802 else if (pidx == JH7110_I2SRX_LRCK_EXT)
803 parents[i].fw_name = "i2srx_lrck_ext";
804 else if (pidx == JH7110_TDM_EXT)
805 parents[i].fw_name = "tdm_ext";
806 else if (pidx == JH7110_MCLK_EXT)
807 parents[i].fw_name = "mclk_ext";
808 else if (pidx == JH7110_JTAG_TCK_INNER)
809 parents[i].fw_name = "jtag_tclk_inner";
810 else if (pidx == JH7110_BIST_APB)
811 parents[i].fw_name = "bist_apb";
814 clk->hw.init = &init;
816 clk->max_div = max & JH7110_CLK_DIV_MASK;
817 clk->reg_flags = JH7110_CLK_SYS_FLAG;
819 ret = devm_clk_hw_register(priv->dev, &clk->hw);
824 dev_dbg(&pdev->dev,"starfive JH7110 clk_sys init successfully.");
projects / platform / kernel / linux-starfive.git / blob