1 /* SPDX-License-Identifier: GPL-2.0 OR MIT */
3 * StarFive JH7110 PLL Clock Generator Driver
5 * Copyright (C) 2022 Xingyu Wu <xingyu.wu@starfivetech.com>
8 #ifndef _CLK_STARFIVE_JH7110_PLL_H_
9 #define _CLK_STARFIVE_JH7110_PLL_H_
12 * If set PLL2_DEFAULT_FREQ NULL of 0 , then PLL2 frequency is original.
13 * If set PLL2_DEFAULT_FREQ one of 'starfive_pll2_freq_value', then PLL2
14 * frequency will be set the new rate during clock tree registering.
16 #define PLL0_DEFAULT_FREQ PLL0_FREQ_1500_VALUE
17 #define PLL2_DEFAULT_FREQ PLL2_FREQ_1188_VALUE
23 #define PLL_INDEX_MAX 3
25 #define PLL0_DACPD_SHIFT 24
26 #define PLL0_DACPD_MASK 0x1000000
27 #define PLL0_DSMPD_SHIFT 25
28 #define PLL0_DSMPD_MASK 0x2000000
29 #define PLL0_FBDIV_SHIFT 0
30 #define PLL0_FBDIV_MASK 0xFFF
31 #define PLL0_FRAC_SHIFT 0
32 #define PLL0_FRAC_MASK 0xFFFFFF
33 #define PLL0_POSTDIV1_SHIFT 28
34 #define PLL0_POSTDIV1_MASK 0x30000000
35 #define PLL0_PREDIV_SHIFT 0
36 #define PLL0_PREDIV_MASK 0x3F
38 #define PLL1_DACPD_SHIFT 15
39 #define PLL1_DACPD_MASK 0x8000
40 #define PLL1_DSMPD_SHIFT 16
41 #define PLL1_DSMPD_MASK 0x10000
42 #define PLL1_FBDIV_SHIFT 17
43 #define PLL1_FBDIV_MASK 0x1FFE0000
44 #define PLL1_FRAC_SHIFT 0
45 #define PLL1_FRAC_MASK 0xFFFFFF
46 #define PLL1_POSTDIV1_SHIFT 28
47 #define PLL1_POSTDIV1_MASK 0x30000000
48 #define PLL1_PREDIV_SHIFT 0
49 #define PLL1_PREDIV_MASK 0x3F
51 #define PLL2_DACPD_SHIFT 15
52 #define PLL2_DACPD_MASK 0x8000
53 #define PLL2_DSMPD_SHIFT 16
54 #define PLL2_DSMPD_MASK 0x10000
55 #define PLL2_FBDIV_SHIFT 17
56 #define PLL2_FBDIV_MASK 0x1FFE0000
57 #define PLL2_FRAC_SHIFT 0
58 #define PLL2_FRAC_MASK 0xFFFFFF
59 #define PLL2_POSTDIV1_SHIFT 28
60 #define PLL2_POSTDIV1_MASK 0x30000000
61 #define PLL2_PREDIV_SHIFT 0
62 #define PLL2_PREDIV_MASK 0x3F
64 #define FRAC_PATR_SIZE 1000
66 struct pll_syscon_offset {
75 struct pll_syscon_mask {
84 struct pll_syscon_shift {
93 struct jh7110_clk_pll_data {
96 unsigned long refclk_freq;
98 unsigned int freq_select_idx;
100 struct regmap *sys_syscon_regmap;
101 struct pll_syscon_offset offset;
102 struct pll_syscon_mask mask;
103 struct pll_syscon_shift shift;
106 struct starfive_pll_syscon_value {
111 /* Both daxpd and dsmpd set 1 while integer multiple mode */
112 /* Both daxpd and dsmpd set 0 while fraction multiple mode */
115 /* frac value should be decimals multiplied by 2^24 */
119 enum starfive_pll0_freq_value {
120 PLL0_FREQ_375_VALUE = 375000000,
121 PLL0_FREQ_500_VALUE = 500000000,
122 PLL0_FREQ_625_VALUE = 625000000,
123 PLL0_FREQ_750_VALUE = 750000000,
124 PLL0_FREQ_875_VALUE = 875000000,
125 PLL0_FREQ_1000_VALUE = 1000000000,
126 PLL0_FREQ_1250_VALUE = 1250000000,
127 PLL0_FREQ_1375_VALUE = 1375000000,
128 PLL0_FREQ_1500_VALUE = 1500000000
131 enum starfive_pll0_freq {
141 PLL0_FREQ_MAX = PLL0_FREQ_1500
144 enum starfive_pll1_freq_value {
145 PLL1_FREQ_1066_VALUE = 1066000000,
148 enum starfive_pll1_freq {
152 enum starfive_pll2_freq_value {
153 PLL2_FREQ_1188_VALUE = 1188000000,
154 PLL2_FREQ_12288_VALUE = 1228800000,
157 enum starfive_pll2_freq {
162 static const struct starfive_pll_syscon_value
163 jh7110_pll0_syscon_freq[] = {
165 .freq = PLL0_FREQ_375_VALUE,
173 .freq = PLL0_FREQ_500_VALUE,
181 .freq = PLL0_FREQ_625_VALUE,
189 .freq = PLL0_FREQ_750_VALUE,
197 .freq = PLL0_FREQ_875_VALUE,
205 .freq = PLL0_FREQ_1000_VALUE,
213 .freq = PLL0_FREQ_1250_VALUE,
221 .freq = PLL0_FREQ_1375_VALUE,
229 .freq = PLL0_FREQ_1500_VALUE,
238 static const struct starfive_pll_syscon_value
239 jh7110_pll1_syscon_freq[] = {
241 .freq = PLL1_FREQ_1066_VALUE,
250 static const struct starfive_pll_syscon_value
251 jh7110_pll2_syscon_freq[] = {
253 .freq = PLL2_FREQ_1188_VALUE,
260 [PLL2_FREQ_12288] = {
261 .freq = PLL2_FREQ_12288_VALUE,
270 int __init clk_starfive_jh7110_pll_init(struct platform_device *pdev,
271 struct jh7110_clk_pll_data *pll_priv);