drivers/clk/starfive/clk-starfive-jh7110-gen.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * StarFive JH7110 Clock Generator Driver
   4  *
   5  * Copyright (C) 2022 Xingyu Wu <xingyu.wu@starfivetech.com>
   6  */
   7
   8 #include <linux/bits.h>
   9 #include <linux/clk.h>
  10 #include <linux/clk-provider.h>
  11 #include <linux/device.h>
  12 #include <linux/init.h>
  13 #include <linux/io.h>
  14 #include <linux/kernel.h>
  15 #include <linux/mod_devicetable.h>
  16 #include <linux/module.h>
  17 #include <linux/platform_device.h>
  18 #include <linux/of_device.h>
  19 #include <linux/pm_runtime.h>
  20
  21 #include <dt-bindings/clock/starfive-jh7110-clkgen.h>
  22 #include "clk-starfive-jh7110.h"
  23 #include "clk-starfive-jh7110-pll.h"
  24
  25 static struct jh7110_clk * __init jh7110_clk_from(struct clk_hw *hw)
  26 {
  27         return container_of(hw, struct jh7110_clk, hw);
  28 }
  29
  30 static struct jh7110_clk_priv *jh7110_priv_from(struct jh7110_clk *clk)
  31 {
  32         return container_of(clk, struct jh7110_clk_priv, reg[clk->idx]);
  33 }
  34
  35 void __iomem *jh7110_clk_reg_addr_get(struct jh7110_clk *clk)
  36 {
  37         void __iomem *reg;
  38         struct jh7110_clk_priv *priv = jh7110_priv_from(clk);
  39
  40         if (clk->reg_flags == JH7110_CLK_SYS_FLAG)
  41                 reg = priv->sys_base + 4 * clk->idx;
  42         else if (clk->reg_flags == JH7110_CLK_STG_FLAG)
  43                 reg = priv->stg_base + 4 * (clk->idx - JH7110_CLK_SYS_REG_END);
  44         else if (clk->reg_flags == JH7110_CLK_AON_FLAG)
  45                 reg = priv->aon_base + 4 * (clk->idx - JH7110_CLK_STG_REG_END);
  46         else if (clk->reg_flags == JH7110_CLK_VOUT_FLAG)
  47                 reg = priv->vout_base + 4 * clk->idx;
  48         else if (clk->reg_flags == JH7110_CLK_ISP_FLAG)
  49                 reg = priv->isp_base + 4 * clk->idx;
  50
  51         return reg;
  52 }
  53
  54 static u32 jh7110_clk_reg_get(struct jh7110_clk *clk)
  55 {
  56         void __iomem *reg = jh7110_clk_reg_addr_get(clk);
  57         if (clk->reg_flags == JH7110_CLK_ISP_FLAG) {
  58                 int ret;
  59                 struct jh7110_clk_priv *priv = jh7110_priv_from(clk);
  60
  61                 if (pm_runtime_suspended(priv->dev)) {
  62                         ret = pm_runtime_get_sync(priv->dev);
  63                         if (ret < 0) {
  64                                 dev_err(priv->dev, "cannot resume device :%d.\n", ret);
  65                                 return 0;
  66                         }
  67                         pm_runtime_put(priv->dev);
  68                 }
  69         }
  70
  71         return readl_relaxed(reg);
  72 }
  73
  74 static void jh7110_clk_reg_rmw(struct jh7110_clk *clk, u32 mask, u32 value)
  75 {
  76         struct jh7110_clk_priv *priv = jh7110_priv_from(clk);
  77         void __iomem *reg = jh7110_clk_reg_addr_get(clk);
  78         unsigned long flags;
  79
  80         spin_lock_irqsave(&priv->rmw_lock, flags);
  81         if ((clk->idx == JH7110_UART3_CLK_CORE
  82                 || clk->idx == JH7110_UART4_CLK_CORE
  83                 || clk->idx == JH7110_UART5_CLK_CORE)
  84                 && (value != JH7110_CLK_ENABLE))
  85                 value  <<= 8;
  86         value |= jh7110_clk_reg_get(clk) & ~mask;
  87         writel_relaxed(value, reg);
  88         spin_unlock_irqrestore(&priv->rmw_lock, flags);
  89 }
  90
  91 static int jh7110_clk_enable(struct clk_hw *hw)
  92 {
  93         struct jh7110_clk *clk = jh7110_clk_from(hw);
  94
  95         jh7110_clk_reg_rmw(clk, JH7110_CLK_ENABLE, JH7110_CLK_ENABLE);
  96         return 0;
  97 }
  98
  99 static void jh7110_clk_disable(struct clk_hw *hw)
 100 {
 101         struct jh7110_clk *clk = jh7110_clk_from(hw);
 102
 103         jh7110_clk_reg_rmw(clk, JH7110_CLK_ENABLE, 0);
 104 }
 105
 106 static int jh7110_clk_is_enabled(struct clk_hw *hw)
 107 {
 108         struct jh7110_clk *clk = jh7110_clk_from(hw);
 109
 110         return !!(jh7110_clk_reg_get(clk) & JH7110_CLK_ENABLE);
 111 }
 112
 113 static unsigned long jh7110_clk_recalc_rate(struct clk_hw *hw,
 114                                                 unsigned long parent_rate)
 115 {
 116         struct jh7110_clk *clk = jh7110_clk_from(hw);
 117         u32 div = jh7110_clk_reg_get(clk) & JH7110_CLK_DIV_MASK;
 118
 119         if (clk->idx == JH7110_UART3_CLK_CORE
 120                 || clk->idx == JH7110_UART4_CLK_CORE
 121                 || clk->idx == JH7110_UART5_CLK_CORE)
 122                 div = div >> 8;
 123
 124         return div ? parent_rate / div : 0;
 125 }
 126
 127 static int jh7110_clk_determine_rate(struct clk_hw *hw,
 128                                         struct clk_rate_request *req)
 129 {
 130         struct jh7110_clk *clk = jh7110_clk_from(hw);
 131         unsigned long parent = req->best_parent_rate;
 132         unsigned long rate = clamp(req->rate, req->min_rate, req->max_rate);
 133         unsigned long div = min_t(unsigned long,
 134                                 DIV_ROUND_UP(parent, rate), clk->max_div);
 135         unsigned long result = parent / div;
 136
 137         /*
 138          * we want the result clamped by min_rate and max_rate if possible:
 139          * case 1: div hits the max divider value, which means it's less than
 140          * parent / rate, so the result is greater than rate and min_rate in
 141          * particular. we can't do anything about result > max_rate because the
 142          * divider doesn't go any further.
 143          * case 2: div = DIV_ROUND_UP(parent, rate) which means the result is
 144          * always lower or equal to rate and max_rate. however the result may
 145          * turn out lower than min_rate, but then the next higher rate is fine:
 146          *      div - 1 = ceil(parent / rate) - 1 < parent / rate
 147          * and thus
 148          *      min_rate <= rate < parent / (div - 1)
 149          */
 150         if (result < req->min_rate && div > 1)
 151                 result = parent / (div - 1);
 152
 153         req->rate = result;
 154         return 0;
 155 }
 156
 157 static int jh7110_clk_set_rate(struct clk_hw *hw,
 158                                 unsigned long rate,
 159                                 unsigned long parent_rate)
 160 {
 161         struct jh7110_clk *clk = jh7110_clk_from(hw);
 162         unsigned long div = clamp(DIV_ROUND_CLOSEST(parent_rate, rate),
 163                                         1UL, (unsigned long)clk->max_div);
 164
 165         jh7110_clk_reg_rmw(clk, JH7110_CLK_DIV_MASK, div);
 166         return 0;
 167 }
 168
 169 static u8 jh7110_clk_get_parent(struct clk_hw *hw)
 170 {
 171         struct jh7110_clk *clk = jh7110_clk_from(hw);
 172         u32 value = jh7110_clk_reg_get(clk);
 173
 174         return (value & JH7110_CLK_MUX_MASK) >> JH7110_CLK_MUX_SHIFT;
 175 }
 176
 177 static int jh7110_clk_set_parent(struct clk_hw *hw, u8 index)
 178 {
 179         struct jh7110_clk *clk = jh7110_clk_from(hw);
 180         u32 value = (u32)index << JH7110_CLK_MUX_SHIFT;
 181
 182         jh7110_clk_reg_rmw(clk, JH7110_CLK_MUX_MASK, value);
 183         return 0;
 184 }
 185
 186 static int jh7110_clk_mux_determine_rate(struct clk_hw *hw,
 187                                          struct clk_rate_request *req)
 188 {
 189         return clk_mux_determine_rate_flags(hw, req, 0);
 190 }
 191
 192 static int jh7110_clk_get_phase(struct clk_hw *hw)
 193 {
 194         struct jh7110_clk *clk = jh7110_clk_from(hw);
 195         u32 value = jh7110_clk_reg_get(clk);
 196
 197         return (value & JH7110_CLK_INVERT) ? 180 : 0;
 198 }
 199
 200 static int jh7110_clk_set_phase(struct clk_hw *hw, int degrees)
 201 {
 202         struct jh7110_clk *clk = jh7110_clk_from(hw);
 203         u32 value;
 204
 205         if (degrees == 0)
 206                 value = 0;
 207         else if (degrees == 180)
 208                 value = JH7110_CLK_INVERT;
 209         else
 210                 return -EINVAL;
 211
 212         jh7110_clk_reg_rmw(clk, JH7110_CLK_INVERT, value);
 213         return 0;
 214 }
 215
 216 #ifdef CONFIG_DEBUG_FS
 217 static void jh7110_clk_debug_init(struct clk_hw *hw, struct dentry *dentry)
 218 {
 219         static const struct debugfs_reg32 jh7110_clk_reg = {
 220                 .name = "CTRL",
 221                 .offset = 0,
 222         };
 223         struct jh7110_clk *clk = jh7110_clk_from(hw);
 224         struct jh7110_clk_priv *priv = jh7110_priv_from(clk);
 225         struct debugfs_regset32 *regset;
 226
 227         regset = devm_kzalloc(priv->dev, sizeof(*regset), GFP_KERNEL);
 228         if (!regset)
 229                 return;
 230
 231         regset->regs = &jh7110_clk_reg;
 232         regset->nregs = 1;
 233         regset->base = jh7110_clk_reg_addr_get(clk);
 234
 235         debugfs_create_regset32("registers", 0400, dentry, regset);
 236 }
 237 #else
 238 #define jh7110_clk_debug_init NULL
 239 #endif
 240
 241 static const struct clk_ops jh7110_clk_gate_ops = {
 242         .enable = jh7110_clk_enable,
 243         .disable = jh7110_clk_disable,
 244         .is_enabled = jh7110_clk_is_enabled,
 245         .debug_init = jh7110_clk_debug_init,
 246 };
 247
 248 static const struct clk_ops jh7110_clk_div_ops = {
 249         .recalc_rate = jh7110_clk_recalc_rate,
 250         .determine_rate = jh7110_clk_determine_rate,
 251         .set_rate = jh7110_clk_set_rate,
 252         .debug_init = jh7110_clk_debug_init,
 253 };
 254
 255 static const struct clk_ops jh7110_clk_gdiv_ops = {
 256         .enable = jh7110_clk_enable,
 257         .disable = jh7110_clk_disable,
 258         .is_enabled = jh7110_clk_is_enabled,
 259         .recalc_rate = jh7110_clk_recalc_rate,
 260         .determine_rate = jh7110_clk_determine_rate,
 261         .set_rate = jh7110_clk_set_rate,
 262         .debug_init = jh7110_clk_debug_init,
 263 };
 264
 265 static const struct clk_ops jh7110_clk_mux_ops = {
 266         .determine_rate = jh7110_clk_mux_determine_rate,
 267         .set_parent = jh7110_clk_set_parent,
 268         .get_parent = jh7110_clk_get_parent,
 269         .debug_init = jh7110_clk_debug_init,
 270 };
 271
 272 static const struct clk_ops jh7110_clk_gmux_ops = {
 273         .enable = jh7110_clk_enable,
 274         .disable = jh7110_clk_disable,
 275         .is_enabled = jh7110_clk_is_enabled,
 276         .determine_rate = jh7110_clk_mux_determine_rate,
 277         .set_parent = jh7110_clk_set_parent,
 278         .get_parent = jh7110_clk_get_parent,
 279         .debug_init = jh7110_clk_debug_init,
 280 };
 281
 282 static const struct clk_ops jh7110_clk_mdiv_ops = {
 283         .recalc_rate = jh7110_clk_recalc_rate,
 284         .determine_rate = jh7110_clk_determine_rate,
 285         .get_parent = jh7110_clk_get_parent,
 286         .set_parent = jh7110_clk_set_parent,
 287         .set_rate = jh7110_clk_set_rate,
 288         .debug_init = jh7110_clk_debug_init,
 289 };
 290
 291 static const struct clk_ops jh7110_clk_gmd_ops = {
 292         .enable = jh7110_clk_enable,
 293         .disable = jh7110_clk_disable,
 294         .is_enabled = jh7110_clk_is_enabled,
 295         .recalc_rate = jh7110_clk_recalc_rate,
 296         .determine_rate = jh7110_clk_determine_rate,
 297         .get_parent = jh7110_clk_get_parent,
 298         .set_parent = jh7110_clk_set_parent,
 299         .set_rate = jh7110_clk_set_rate,
 300         .debug_init = jh7110_clk_debug_init,
 301 };
 302
 303 static const struct clk_ops jh7110_clk_inv_ops = {
 304         .get_phase = jh7110_clk_get_phase,
 305         .set_phase = jh7110_clk_set_phase,
 306         .debug_init = jh7110_clk_debug_init,
 307 };
 308
 309 const struct clk_ops *starfive_jh7110_clk_ops(u32 max)
 310 {
 311         const struct clk_ops *ops;
 312
 313         if (max & JH7110_CLK_DIV_MASK) {
 314                 if (max & JH7110_CLK_MUX_MASK) {
 315                         if (max & JH7110_CLK_ENABLE)
 316                                 ops = &jh7110_clk_gmd_ops;
 317                         else
 318                                 ops = &jh7110_clk_mdiv_ops;
 319                 } else if (max & JH7110_CLK_ENABLE)
 320                         ops = &jh7110_clk_gdiv_ops;
 321                 else
 322                         ops = &jh7110_clk_div_ops;
 323         } else if (max & JH7110_CLK_MUX_MASK) {
 324                 if (max & JH7110_CLK_ENABLE)
 325                         ops = &jh7110_clk_gmux_ops;
 326                 else
 327                         ops = &jh7110_clk_mux_ops;
 328         } else if (max & JH7110_CLK_ENABLE)
 329                 ops = &jh7110_clk_gate_ops;
 330         else
 331                 ops = &jh7110_clk_inv_ops;
 332
 333         return ops;
 334 }
 335 EXPORT_SYMBOL_GPL(starfive_jh7110_clk_ops);
 336
 337 static struct clk_hw *jh7110_clk_get(struct of_phandle_args *clkspec,
 338                                                 void *data)
 339 {
 340         struct jh7110_clk_priv *priv = data;
 341         unsigned int idx = clkspec->args[0];
 342
 343         if (idx < JH7110_PLL0_OUT)
 344                 return &priv->reg[idx].hw;
 345
 346         if (idx < JH7110_CLK_END) {
 347 #ifdef CONFIG_CLK_STARFIVE_JH7110_PLL
 348                 if ((idx == JH7110_PLL0_OUT) || (idx == JH7110_PLL2_OUT))
 349                         return &priv->pll_priv[PLL_OF(idx)].hw;
 350 #endif
 351                 return priv->pll[PLL_OF(idx)];
 352         }
 353
 354         return ERR_PTR(-EINVAL);
 355 }
 356
 357
 358 static int __init clk_starfive_jh7110_probe(struct platform_device *pdev)
 359 {
 360         struct jh7110_clk_priv *priv;
 361         int ret = 0;
 362
 363         priv = devm_kzalloc(&pdev->dev, struct_size(priv, reg, JH7110_PLL0_OUT),
 364                                         GFP_KERNEL);
 365         if (!priv)
 366                 return -ENOMEM;
 367
 368         spin_lock_init(&priv->rmw_lock);
 369         priv->dev = &pdev->dev;
 370
 371 #ifdef CONFIG_CLK_STARFIVE_JH7110_PLL
 372         ret = clk_starfive_jh7110_pll_init(pdev, priv->pll_priv);
 373         if (ret)
 374                 return ret;
 375 #endif
 376
 377         ret = clk_starfive_jh7110_sys_init(pdev, priv);
 378         if (ret)
 379                 return ret;
 380
 381         ret = clk_starfive_jh7110_stg_init(pdev, priv);
 382         if (ret)
 383                 return ret;
 384
 385         ret = clk_starfive_jh7110_aon_init(pdev, priv);
 386         if (ret)
 387                 return ret;
 388
 389         ret = devm_of_clk_add_hw_provider(priv->dev, jh7110_clk_get, priv);
 390         if (ret)
 391                 return ret;
 392
 393         dev_info(&pdev->dev, "starfive JH7110 clkgen init successfully.");
 394         return 0;
 395 }
 396
 397 static const struct of_device_id clk_starfive_jh7110_match[] = {
 398         {.compatible = "starfive,jh7110-clkgen"},
 399         { /* sentinel */ }
 400 };
 401
 402 static struct platform_driver clk_starfive_jh7110_driver = {
 403         .driver = {
 404                 .name = "clk-starfive-jh7110",
 405                 .of_match_table = clk_starfive_jh7110_match,
 406         },
 407 };
 408 builtin_platform_driver_probe(clk_starfive_jh7110_driver,
 409                         clk_starfive_jh7110_probe);
 410
 411 MODULE_AUTHOR("Xingyu Wu <xingyu.wu@starfivetech.com>");
 412 MODULE_DESCRIPTION("StarFive JH7110 sysgen clock driver");
 413 MODULE_LICENSE("GPL");