1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Clock tree for CSR SiRFprimaII
5 * Copyright (c) 2011 - 2014 Cambridge Silicon Radio Limited, a CSR plc group
9 #include <linux/module.h>
10 #include <linux/bitops.h>
12 #include <linux/clkdev.h>
13 #include <linux/clk-provider.h>
14 #include <linux/of_address.h>
15 #include <linux/syscore_ops.h>
18 #include "clk-common.c"
20 static struct clk_dmn clk_mmc01 = {
21 .regofs = SIRFSOC_CLKC_MMC_CFG,
24 .init = &clk_mmc01_init,
28 static struct clk_dmn clk_mmc23 = {
29 .regofs = SIRFSOC_CLKC_MMC_CFG,
32 .init = &clk_mmc23_init,
36 static struct clk_dmn clk_mmc45 = {
37 .regofs = SIRFSOC_CLKC_MMC_CFG,
40 .init = &clk_mmc45_init,
44 static const struct clk_init_data clk_nand_init = {
47 .parent_names = std_clk_io_parents,
48 .num_parents = ARRAY_SIZE(std_clk_io_parents),
51 static struct clk_std clk_nand = {
54 .init = &clk_nand_init,
58 enum prima2_clk_index {
59 /* 0 1 2 3 4 5 6 7 8 9 */
60 rtc, osc, pll1, pll2, pll3, mem, sys, security, dsp, gps,
61 mf, io, cpu, uart0, uart1, uart2, tsc, i2c0, i2c1, spi0,
62 spi1, pwmc, efuse, pulse, dmac0, dmac1, nand, audio, usp0, usp1,
63 usp2, vip, gfx, mm, lcd, vpp, mmc01, mmc23, mmc45, usbpll,
64 usb0, usb1, cphif, maxclk,
67 static __initdata struct clk_hw *prima2_clk_hw_array[maxclk] = {
113 static struct clk *prima2_clks[maxclk];
115 static void __init prima2_clk_init(struct device_node *np)
117 struct device_node *rscnp;
120 rscnp = of_find_compatible_node(NULL, NULL, "sirf,prima2-rsc");
121 sirfsoc_rsc_vbase = of_iomap(rscnp, 0);
122 if (!sirfsoc_rsc_vbase)
123 panic("unable to map rsc registers\n");
126 sirfsoc_clk_vbase = of_iomap(np, 0);
127 if (!sirfsoc_clk_vbase)
128 panic("unable to map clkc registers\n");
130 /* These are always available (RTC and 26MHz OSC)*/
131 prima2_clks[rtc] = clk_register_fixed_rate(NULL, "rtc", NULL, 0, 32768);
132 prima2_clks[osc] = clk_register_fixed_rate(NULL, "osc", NULL, 0,
135 for (i = pll1; i < maxclk; i++) {
136 prima2_clks[i] = clk_register(NULL, prima2_clk_hw_array[i]);
137 BUG_ON(!prima2_clks[i]);
139 clk_register_clkdev(prima2_clks[cpu], NULL, "cpu");
140 clk_register_clkdev(prima2_clks[io], NULL, "io");
141 clk_register_clkdev(prima2_clks[mem], NULL, "mem");
142 clk_register_clkdev(prima2_clks[mem], NULL, "osc");
144 clk_data.clks = prima2_clks;
145 clk_data.clk_num = maxclk;
147 of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
149 CLK_OF_DECLARE(prima2_clk, "sirf,prima2-clkc", prima2_clk_init);