1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * common clks module for all SiRF SoCs
5 * Copyright (c) 2011 - 2014 Cambridge Silicon Radio Limited, a CSR plc group
12 #define MHZ (KHZ * KHZ)
14 static void __iomem *sirfsoc_clk_vbase;
15 static void __iomem *sirfsoc_rsc_vbase;
16 static struct clk_onecell_data clk_data;
19 * SiRFprimaII clock controller
20 * - 2 oscillators: osc-26MHz, rtc-32.768KHz
21 * - 3 standard configurable plls: pll1, pll2 & pll3
22 * - 2 exclusive plls: usb phy pll and sata phy pll
23 * - 8 clock domains: cpu/cpudiv, mem/memdiv, sys/io, dsp, graphic, multimedia,
25 * Each clock domain can select its own clock source from five clock sources,
26 * X_XIN, X_XINW, PLL1, PLL2 and PLL3. The domain clock is used as the source
27 * clock of the group clock.
28 * - dsp domain: gps, mf
29 * - io domain: dmac, nand, audio, uart, i2c, spi, usp, pwm, pulse
30 * - sys domain: security
35 unsigned short regofs; /* register offset */
38 #define to_pllclk(_hw) container_of(_hw, struct clk_pll, hw)
42 signed char enable_bit; /* enable bit: 0 ~ 63 */
43 unsigned short regofs; /* register offset */
46 #define to_dmnclk(_hw) container_of(_hw, struct clk_dmn, hw)
50 signed char enable_bit; /* enable bit: 0 ~ 63 */
53 #define to_stdclk(_hw) container_of(_hw, struct clk_std, hw)
55 static int std_clk_is_enabled(struct clk_hw *hw);
56 static int std_clk_enable(struct clk_hw *hw);
57 static void std_clk_disable(struct clk_hw *hw);
59 static inline unsigned long clkc_readl(unsigned reg)
61 return readl(sirfsoc_clk_vbase + reg);
64 static inline void clkc_writel(u32 val, unsigned reg)
66 writel(val, sirfsoc_clk_vbase + reg);
73 static unsigned long pll_clk_recalc_rate(struct clk_hw *hw,
74 unsigned long parent_rate)
76 unsigned long fin = parent_rate;
77 struct clk_pll *clk = to_pllclk(hw);
78 u32 regcfg2 = clk->regofs + SIRFSOC_CLKC_PLL1_CFG2 -
79 SIRFSOC_CLKC_PLL1_CFG0;
81 if (clkc_readl(regcfg2) & BIT(2)) {
85 /* fout = fin * nf / nr / od */
86 u32 cfg0 = clkc_readl(clk->regofs);
87 u32 nf = (cfg0 & (BIT(13) - 1)) + 1;
88 u32 nr = ((cfg0 >> 13) & (BIT(6) - 1)) + 1;
89 u32 od = ((cfg0 >> 19) & (BIT(4) - 1)) + 1;
91 return fin / MHZ * nf / nr / od * MHZ;
95 static long pll_clk_round_rate(struct clk_hw *hw, unsigned long rate,
96 unsigned long *parent_rate)
98 unsigned long fin, nf, nr, od;
102 * fout = fin * nf / (nr * od);
103 * set od = 1, nr = fin/MHz, so fout = nf * MHz
105 rate = rate - rate % MHZ;
120 dividend = (u64)fin * nf;
121 do_div(dividend, nr * od);
123 return (long)dividend;
126 static int pll_clk_set_rate(struct clk_hw *hw, unsigned long rate,
127 unsigned long parent_rate)
129 struct clk_pll *clk = to_pllclk(hw);
130 unsigned long fin, nf, nr, od, reg;
133 * fout = fin * nf / (nr * od);
134 * set od = 1, nr = fin/MHz, so fout = nf * MHz
138 if (unlikely((rate % MHZ) || nf > BIT(13) || nf < 1))
145 BUG_ON((fin % MHZ) || nr > BIT(6));
149 reg = (nf - 1) | ((nr - 1) << 13) | ((od - 1) << 19);
150 clkc_writel(reg, clk->regofs);
152 reg = clk->regofs + SIRFSOC_CLKC_PLL1_CFG1 - SIRFSOC_CLKC_PLL1_CFG0;
153 clkc_writel((nf >> 1) - 1, reg);
155 reg = clk->regofs + SIRFSOC_CLKC_PLL1_CFG2 - SIRFSOC_CLKC_PLL1_CFG0;
156 while (!(clkc_readl(reg) & BIT(6)))
162 static long cpu_clk_round_rate(struct clk_hw *hw, unsigned long rate,
163 unsigned long *parent_rate)
166 * SiRF SoC has not cpu clock control,
167 * So bypass to it's parent pll.
169 struct clk_hw *parent_clk = clk_hw_get_parent(hw);
170 struct clk_hw *pll_parent_clk = clk_hw_get_parent(parent_clk);
171 unsigned long pll_parent_rate = clk_hw_get_rate(pll_parent_clk);
172 return pll_clk_round_rate(parent_clk, rate, &pll_parent_rate);
175 static unsigned long cpu_clk_recalc_rate(struct clk_hw *hw,
176 unsigned long parent_rate)
179 * SiRF SoC has not cpu clock control,
180 * So return the parent pll rate.
182 struct clk_hw *parent_clk = clk_hw_get_parent(hw);
183 return clk_hw_get_rate(parent_clk);
186 static const struct clk_ops std_pll_ops = {
187 .recalc_rate = pll_clk_recalc_rate,
188 .round_rate = pll_clk_round_rate,
189 .set_rate = pll_clk_set_rate,
192 static const char * const pll_clk_parents[] = {
196 static const struct clk_init_data clk_pll1_init = {
199 .parent_names = pll_clk_parents,
200 .num_parents = ARRAY_SIZE(pll_clk_parents),
203 static const struct clk_init_data clk_pll2_init = {
206 .parent_names = pll_clk_parents,
207 .num_parents = ARRAY_SIZE(pll_clk_parents),
210 static const struct clk_init_data clk_pll3_init = {
213 .parent_names = pll_clk_parents,
214 .num_parents = ARRAY_SIZE(pll_clk_parents),
217 static struct clk_pll clk_pll1 = {
218 .regofs = SIRFSOC_CLKC_PLL1_CFG0,
220 .init = &clk_pll1_init,
224 static struct clk_pll clk_pll2 = {
225 .regofs = SIRFSOC_CLKC_PLL2_CFG0,
227 .init = &clk_pll2_init,
231 static struct clk_pll clk_pll3 = {
232 .regofs = SIRFSOC_CLKC_PLL3_CFG0,
234 .init = &clk_pll3_init,
239 * usb uses specified pll
242 static int usb_pll_clk_enable(struct clk_hw *hw)
244 u32 reg = readl(sirfsoc_rsc_vbase + SIRFSOC_USBPHY_PLL_CTRL);
245 reg &= ~(SIRFSOC_USBPHY_PLL_POWERDOWN | SIRFSOC_USBPHY_PLL_BYPASS);
246 writel(reg, sirfsoc_rsc_vbase + SIRFSOC_USBPHY_PLL_CTRL);
247 while (!(readl(sirfsoc_rsc_vbase + SIRFSOC_USBPHY_PLL_CTRL) &
248 SIRFSOC_USBPHY_PLL_LOCK))
254 static void usb_pll_clk_disable(struct clk_hw *clk)
256 u32 reg = readl(sirfsoc_rsc_vbase + SIRFSOC_USBPHY_PLL_CTRL);
257 reg |= (SIRFSOC_USBPHY_PLL_POWERDOWN | SIRFSOC_USBPHY_PLL_BYPASS);
258 writel(reg, sirfsoc_rsc_vbase + SIRFSOC_USBPHY_PLL_CTRL);
261 static unsigned long usb_pll_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
263 u32 reg = readl(sirfsoc_rsc_vbase + SIRFSOC_USBPHY_PLL_CTRL);
264 return (reg & SIRFSOC_USBPHY_PLL_BYPASS) ? parent_rate : 48*MHZ;
267 static const struct clk_ops usb_pll_ops = {
268 .enable = usb_pll_clk_enable,
269 .disable = usb_pll_clk_disable,
270 .recalc_rate = usb_pll_clk_recalc_rate,
273 static const struct clk_init_data clk_usb_pll_init = {
276 .parent_names = pll_clk_parents,
277 .num_parents = ARRAY_SIZE(pll_clk_parents),
280 static struct clk_hw usb_pll_clk_hw = {
281 .init = &clk_usb_pll_init,
285 * clock domains - cpu, mem, sys/io, dsp, gfx
288 static const char * const dmn_clk_parents[] = {
296 static u8 dmn_clk_get_parent(struct clk_hw *hw)
298 struct clk_dmn *clk = to_dmnclk(hw);
299 u32 cfg = clkc_readl(clk->regofs);
300 const char *name = clk_hw_get_name(hw);
302 /* parent of io domain can only be pll3 */
303 if (strcmp(name, "io") == 0)
306 WARN_ON((cfg & (BIT(3) - 1)) > 4);
308 return cfg & (BIT(3) - 1);
311 static int dmn_clk_set_parent(struct clk_hw *hw, u8 parent)
313 struct clk_dmn *clk = to_dmnclk(hw);
314 u32 cfg = clkc_readl(clk->regofs);
315 const char *name = clk_hw_get_name(hw);
317 /* parent of io domain can only be pll3 */
318 if (strcmp(name, "io") == 0)
321 cfg &= ~(BIT(3) - 1);
322 clkc_writel(cfg | parent, clk->regofs);
323 /* BIT(3) - switching status: 1 - busy, 0 - done */
324 while (clkc_readl(clk->regofs) & BIT(3))
330 static unsigned long dmn_clk_recalc_rate(struct clk_hw *hw,
331 unsigned long parent_rate)
334 unsigned long fin = parent_rate;
335 struct clk_dmn *clk = to_dmnclk(hw);
337 u32 cfg = clkc_readl(clk->regofs);
340 /* fcd bypass mode */
344 * wait count: bit[19:16], hold count: bit[23:20]
346 u32 wait = (cfg >> 16) & (BIT(4) - 1);
347 u32 hold = (cfg >> 20) & (BIT(4) - 1);
349 return fin / (wait + hold + 2);
353 static long dmn_clk_round_rate(struct clk_hw *hw, unsigned long rate,
354 unsigned long *parent_rate)
357 unsigned ratio, wait, hold;
358 const char *name = clk_hw_get_name(hw);
359 unsigned bits = (strcmp(name, "mem") == 0) ? 3 : 4;
366 if (ratio > BIT(bits + 1))
367 ratio = BIT(bits + 1);
369 wait = (ratio >> 1) - 1;
370 hold = ratio - wait - 2;
372 return fin / (wait + hold + 2);
375 static int dmn_clk_set_rate(struct clk_hw *hw, unsigned long rate,
376 unsigned long parent_rate)
378 struct clk_dmn *clk = to_dmnclk(hw);
380 unsigned ratio, wait, hold, reg;
381 const char *name = clk_hw_get_name(hw);
382 unsigned bits = (strcmp(name, "mem") == 0) ? 3 : 4;
387 if (unlikely(ratio < 2 || ratio > BIT(bits + 1)))
392 wait = (ratio >> 1) - 1;
393 hold = ratio - wait - 2;
395 reg = clkc_readl(clk->regofs);
396 reg &= ~(((BIT(bits) - 1) << 16) | ((BIT(bits) - 1) << 20));
397 reg |= (wait << 16) | (hold << 20) | BIT(25);
398 clkc_writel(reg, clk->regofs);
400 /* waiting FCD been effective */
401 while (clkc_readl(clk->regofs) & BIT(25))
407 static int cpu_clk_set_rate(struct clk_hw *hw, unsigned long rate,
408 unsigned long parent_rate)
411 struct clk *cur_parent;
413 if (rate == clk_get_rate(clk_pll1.hw.clk)) {
414 ret1 = clk_set_parent(hw->clk, clk_pll1.hw.clk);
418 if (rate == clk_get_rate(clk_pll2.hw.clk)) {
419 ret1 = clk_set_parent(hw->clk, clk_pll2.hw.clk);
423 if (rate == clk_get_rate(clk_pll3.hw.clk)) {
424 ret1 = clk_set_parent(hw->clk, clk_pll3.hw.clk);
428 cur_parent = clk_get_parent(hw->clk);
430 /* switch to tmp pll before setting parent clock's rate */
431 if (cur_parent == clk_pll1.hw.clk) {
432 ret1 = clk_set_parent(hw->clk, clk_pll2.hw.clk);
436 ret2 = clk_set_rate(clk_pll1.hw.clk, rate);
438 ret1 = clk_set_parent(hw->clk, clk_pll1.hw.clk);
440 return ret2 ? ret2 : ret1;
443 static const struct clk_ops msi_ops = {
444 .set_rate = dmn_clk_set_rate,
445 .round_rate = dmn_clk_round_rate,
446 .recalc_rate = dmn_clk_recalc_rate,
447 .set_parent = dmn_clk_set_parent,
448 .get_parent = dmn_clk_get_parent,
451 static const struct clk_init_data clk_mem_init = {
454 .parent_names = dmn_clk_parents,
455 .num_parents = ARRAY_SIZE(dmn_clk_parents),
458 static struct clk_dmn clk_mem = {
459 .regofs = SIRFSOC_CLKC_MEM_CFG,
461 .init = &clk_mem_init,
465 static const struct clk_init_data clk_sys_init = {
468 .parent_names = dmn_clk_parents,
469 .num_parents = ARRAY_SIZE(dmn_clk_parents),
470 .flags = CLK_SET_RATE_GATE,
473 static struct clk_dmn clk_sys = {
474 .regofs = SIRFSOC_CLKC_SYS_CFG,
476 .init = &clk_sys_init,
480 static const struct clk_init_data clk_io_init = {
483 .parent_names = dmn_clk_parents,
484 .num_parents = ARRAY_SIZE(dmn_clk_parents),
487 static struct clk_dmn clk_io = {
488 .regofs = SIRFSOC_CLKC_IO_CFG,
490 .init = &clk_io_init,
494 static const struct clk_ops cpu_ops = {
495 .set_parent = dmn_clk_set_parent,
496 .get_parent = dmn_clk_get_parent,
497 .set_rate = cpu_clk_set_rate,
498 .round_rate = cpu_clk_round_rate,
499 .recalc_rate = cpu_clk_recalc_rate,
502 static const struct clk_init_data clk_cpu_init = {
505 .parent_names = dmn_clk_parents,
506 .num_parents = ARRAY_SIZE(dmn_clk_parents),
507 .flags = CLK_SET_RATE_PARENT,
510 static struct clk_dmn clk_cpu = {
511 .regofs = SIRFSOC_CLKC_CPU_CFG,
513 .init = &clk_cpu_init,
517 static const struct clk_ops dmn_ops = {
518 .is_enabled = std_clk_is_enabled,
519 .enable = std_clk_enable,
520 .disable = std_clk_disable,
521 .set_rate = dmn_clk_set_rate,
522 .round_rate = dmn_clk_round_rate,
523 .recalc_rate = dmn_clk_recalc_rate,
524 .set_parent = dmn_clk_set_parent,
525 .get_parent = dmn_clk_get_parent,
528 /* dsp, gfx, mm, lcd and vpp domain */
530 static const struct clk_init_data clk_dsp_init = {
533 .parent_names = dmn_clk_parents,
534 .num_parents = ARRAY_SIZE(dmn_clk_parents),
537 static struct clk_dmn clk_dsp = {
538 .regofs = SIRFSOC_CLKC_DSP_CFG,
541 .init = &clk_dsp_init,
545 static const struct clk_init_data clk_gfx_init = {
548 .parent_names = dmn_clk_parents,
549 .num_parents = ARRAY_SIZE(dmn_clk_parents),
552 static struct clk_dmn clk_gfx = {
553 .regofs = SIRFSOC_CLKC_GFX_CFG,
556 .init = &clk_gfx_init,
560 static const struct clk_init_data clk_mm_init = {
563 .parent_names = dmn_clk_parents,
564 .num_parents = ARRAY_SIZE(dmn_clk_parents),
567 static struct clk_dmn clk_mm = {
568 .regofs = SIRFSOC_CLKC_MM_CFG,
571 .init = &clk_mm_init,
576 * for atlas6, gfx2d holds the bit of prima2's clk_mm
578 #define clk_gfx2d clk_mm
580 static const struct clk_init_data clk_lcd_init = {
583 .parent_names = dmn_clk_parents,
584 .num_parents = ARRAY_SIZE(dmn_clk_parents),
587 static struct clk_dmn clk_lcd = {
588 .regofs = SIRFSOC_CLKC_LCD_CFG,
591 .init = &clk_lcd_init,
595 static const struct clk_init_data clk_vpp_init = {
598 .parent_names = dmn_clk_parents,
599 .num_parents = ARRAY_SIZE(dmn_clk_parents),
602 static struct clk_dmn clk_vpp = {
603 .regofs = SIRFSOC_CLKC_LCD_CFG,
606 .init = &clk_vpp_init,
610 static const struct clk_init_data clk_mmc01_init = {
613 .parent_names = dmn_clk_parents,
614 .num_parents = ARRAY_SIZE(dmn_clk_parents),
617 static const struct clk_init_data clk_mmc23_init = {
620 .parent_names = dmn_clk_parents,
621 .num_parents = ARRAY_SIZE(dmn_clk_parents),
624 static const struct clk_init_data clk_mmc45_init = {
627 .parent_names = dmn_clk_parents,
628 .num_parents = ARRAY_SIZE(dmn_clk_parents),
632 * peripheral controllers in io domain
635 static int std_clk_is_enabled(struct clk_hw *hw)
639 struct clk_std *clk = to_stdclk(hw);
641 bit = clk->enable_bit % 32;
642 reg = clk->enable_bit / 32;
643 reg = SIRFSOC_CLKC_CLK_EN0 + reg * sizeof(reg);
645 return !!(clkc_readl(reg) & BIT(bit));
648 static int std_clk_enable(struct clk_hw *hw)
652 struct clk_std *clk = to_stdclk(hw);
654 BUG_ON(clk->enable_bit < 0 || clk->enable_bit > 63);
656 bit = clk->enable_bit % 32;
657 reg = clk->enable_bit / 32;
658 reg = SIRFSOC_CLKC_CLK_EN0 + reg * sizeof(reg);
660 val = clkc_readl(reg) | BIT(bit);
661 clkc_writel(val, reg);
665 static void std_clk_disable(struct clk_hw *hw)
669 struct clk_std *clk = to_stdclk(hw);
671 BUG_ON(clk->enable_bit < 0 || clk->enable_bit > 63);
673 bit = clk->enable_bit % 32;
674 reg = clk->enable_bit / 32;
675 reg = SIRFSOC_CLKC_CLK_EN0 + reg * sizeof(reg);
677 val = clkc_readl(reg) & ~BIT(bit);
678 clkc_writel(val, reg);
681 static const char * const std_clk_io_parents[] = {
685 static const struct clk_ops ios_ops = {
686 .is_enabled = std_clk_is_enabled,
687 .enable = std_clk_enable,
688 .disable = std_clk_disable,
691 static const struct clk_init_data clk_cphif_init = {
694 .parent_names = std_clk_io_parents,
695 .num_parents = ARRAY_SIZE(std_clk_io_parents),
698 static struct clk_std clk_cphif = {
701 .init = &clk_cphif_init,
705 static const struct clk_init_data clk_dmac0_init = {
708 .parent_names = std_clk_io_parents,
709 .num_parents = ARRAY_SIZE(std_clk_io_parents),
712 static struct clk_std clk_dmac0 = {
715 .init = &clk_dmac0_init,
719 static const struct clk_init_data clk_dmac1_init = {
722 .parent_names = std_clk_io_parents,
723 .num_parents = ARRAY_SIZE(std_clk_io_parents),
726 static struct clk_std clk_dmac1 = {
729 .init = &clk_dmac1_init,
733 static const struct clk_init_data clk_audio_init = {
736 .parent_names = std_clk_io_parents,
737 .num_parents = ARRAY_SIZE(std_clk_io_parents),
740 static struct clk_std clk_audio = {
743 .init = &clk_audio_init,
747 static const struct clk_init_data clk_uart0_init = {
750 .parent_names = std_clk_io_parents,
751 .num_parents = ARRAY_SIZE(std_clk_io_parents),
754 static struct clk_std clk_uart0 = {
757 .init = &clk_uart0_init,
761 static const struct clk_init_data clk_uart1_init = {
764 .parent_names = std_clk_io_parents,
765 .num_parents = ARRAY_SIZE(std_clk_io_parents),
768 static struct clk_std clk_uart1 = {
771 .init = &clk_uart1_init,
775 static const struct clk_init_data clk_uart2_init = {
778 .parent_names = std_clk_io_parents,
779 .num_parents = ARRAY_SIZE(std_clk_io_parents),
782 static struct clk_std clk_uart2 = {
785 .init = &clk_uart2_init,
789 static const struct clk_init_data clk_usp0_init = {
792 .parent_names = std_clk_io_parents,
793 .num_parents = ARRAY_SIZE(std_clk_io_parents),
796 static struct clk_std clk_usp0 = {
799 .init = &clk_usp0_init,
803 static const struct clk_init_data clk_usp1_init = {
806 .parent_names = std_clk_io_parents,
807 .num_parents = ARRAY_SIZE(std_clk_io_parents),
810 static struct clk_std clk_usp1 = {
813 .init = &clk_usp1_init,
817 static const struct clk_init_data clk_usp2_init = {
820 .parent_names = std_clk_io_parents,
821 .num_parents = ARRAY_SIZE(std_clk_io_parents),
824 static struct clk_std clk_usp2 = {
827 .init = &clk_usp2_init,
831 static const struct clk_init_data clk_vip_init = {
834 .parent_names = std_clk_io_parents,
835 .num_parents = ARRAY_SIZE(std_clk_io_parents),
838 static struct clk_std clk_vip = {
841 .init = &clk_vip_init,
845 static const struct clk_init_data clk_spi0_init = {
848 .parent_names = std_clk_io_parents,
849 .num_parents = ARRAY_SIZE(std_clk_io_parents),
852 static struct clk_std clk_spi0 = {
855 .init = &clk_spi0_init,
859 static const struct clk_init_data clk_spi1_init = {
862 .parent_names = std_clk_io_parents,
863 .num_parents = ARRAY_SIZE(std_clk_io_parents),
866 static struct clk_std clk_spi1 = {
869 .init = &clk_spi1_init,
873 static const struct clk_init_data clk_tsc_init = {
876 .parent_names = std_clk_io_parents,
877 .num_parents = ARRAY_SIZE(std_clk_io_parents),
880 static struct clk_std clk_tsc = {
883 .init = &clk_tsc_init,
887 static const struct clk_init_data clk_i2c0_init = {
890 .parent_names = std_clk_io_parents,
891 .num_parents = ARRAY_SIZE(std_clk_io_parents),
894 static struct clk_std clk_i2c0 = {
897 .init = &clk_i2c0_init,
901 static const struct clk_init_data clk_i2c1_init = {
904 .parent_names = std_clk_io_parents,
905 .num_parents = ARRAY_SIZE(std_clk_io_parents),
908 static struct clk_std clk_i2c1 = {
911 .init = &clk_i2c1_init,
915 static const struct clk_init_data clk_pwmc_init = {
918 .parent_names = std_clk_io_parents,
919 .num_parents = ARRAY_SIZE(std_clk_io_parents),
922 static struct clk_std clk_pwmc = {
925 .init = &clk_pwmc_init,
929 static const struct clk_init_data clk_efuse_init = {
932 .parent_names = std_clk_io_parents,
933 .num_parents = ARRAY_SIZE(std_clk_io_parents),
936 static struct clk_std clk_efuse = {
939 .init = &clk_efuse_init,
943 static const struct clk_init_data clk_pulse_init = {
946 .parent_names = std_clk_io_parents,
947 .num_parents = ARRAY_SIZE(std_clk_io_parents),
950 static struct clk_std clk_pulse = {
953 .init = &clk_pulse_init,
957 static const char * const std_clk_dsp_parents[] = {
961 static const struct clk_init_data clk_gps_init = {
964 .parent_names = std_clk_dsp_parents,
965 .num_parents = ARRAY_SIZE(std_clk_dsp_parents),
968 static struct clk_std clk_gps = {
971 .init = &clk_gps_init,
975 static const struct clk_init_data clk_mf_init = {
978 .parent_names = std_clk_io_parents,
979 .num_parents = ARRAY_SIZE(std_clk_io_parents),
982 static struct clk_std clk_mf = {
985 .init = &clk_mf_init,
989 static const char * const std_clk_sys_parents[] = {
993 static const struct clk_init_data clk_security_init = {
996 .parent_names = std_clk_sys_parents,
997 .num_parents = ARRAY_SIZE(std_clk_sys_parents),
1000 static struct clk_std clk_security = {
1003 .init = &clk_security_init,
1007 static const char * const std_clk_usb_parents[] = {
1011 static const struct clk_init_data clk_usb0_init = {
1014 .parent_names = std_clk_usb_parents,
1015 .num_parents = ARRAY_SIZE(std_clk_usb_parents),
1018 static struct clk_std clk_usb0 = {
1021 .init = &clk_usb0_init,
1025 static const struct clk_init_data clk_usb1_init = {
1028 .parent_names = std_clk_usb_parents,
1029 .num_parents = ARRAY_SIZE(std_clk_usb_parents),
1032 static struct clk_std clk_usb1 = {
1035 .init = &clk_usb1_init,