1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2018-2021 SiFive, Inc.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * The PRCI implements clock and reset control for the SiFive chip.
19 * This driver assumes that it has sole control over all PRCI resources.
21 * This driver is based on the PRCI driver written by Wesley Terpstra:
22 * https://github.com/riscv/riscv-linux/commit/999529edf517ed75b56659d456d221b2ee56bb60
26 #include <clk-uclass.h>
29 #include <dm/device_compat.h>
32 #include <asm/arch/reset.h>
33 #include <linux/delay.h>
34 #include <linux/math64.h>
35 #include <dt-bindings/clock/sifive-fu740-prci.h>
37 #include "fu540-prci.h"
38 #include "fu740-prci.h"
45 * __prci_readl() - read from a PRCI register
47 * @offs: register offset to read from (in bytes, from PRCI base address)
49 * Read the register located at offset @offs from the base virtual
50 * address of the PRCI register target described by @pd, and return
51 * the value to the caller.
53 * Context: Any context.
55 * Return: the contents of the register described by @pd and @offs.
57 static u32 __prci_readl(struct __prci_data *pd, u32 offs)
59 return readl(pd->va + offs);
62 static void __prci_writel(u32 v, u32 offs, struct __prci_data *pd)
64 writel(v, pd->va + offs);
67 /* WRPLL-related private functions */
70 * __prci_wrpll_unpack() - unpack WRPLL configuration registers into parameters
71 * @c: ptr to a struct wrpll_cfg record to write config into
72 * @r: value read from the PRCI PLL configuration register
74 * Given a value @r read from an FU540 PRCI PLL configuration register,
75 * split it into fields and populate it into the WRPLL configuration record
78 * The COREPLLCFG0 macros are used below, but the other *PLLCFG0 macros
79 * have the same register layout.
81 * Context: Any context.
83 static void __prci_wrpll_unpack(struct wrpll_cfg *c, u32 r)
87 v = r & PRCI_COREPLLCFG0_DIVR_MASK;
88 v >>= PRCI_COREPLLCFG0_DIVR_SHIFT;
91 v = r & PRCI_COREPLLCFG0_DIVF_MASK;
92 v >>= PRCI_COREPLLCFG0_DIVF_SHIFT;
95 v = r & PRCI_COREPLLCFG0_DIVQ_MASK;
96 v >>= PRCI_COREPLLCFG0_DIVQ_SHIFT;
99 v = r & PRCI_COREPLLCFG0_RANGE_MASK;
100 v >>= PRCI_COREPLLCFG0_RANGE_SHIFT;
103 c->flags &= (WRPLL_FLAGS_INT_FEEDBACK_MASK |
104 WRPLL_FLAGS_EXT_FEEDBACK_MASK);
106 /* external feedback mode not supported */
107 c->flags |= WRPLL_FLAGS_INT_FEEDBACK_MASK;
111 * __prci_wrpll_pack() - pack PLL configuration parameters into a register value
112 * @c: pointer to a struct wrpll_cfg record containing the PLL's cfg
114 * Using a set of WRPLL configuration values pointed to by @c,
115 * assemble a PRCI PLL configuration register value, and return it to
118 * Context: Any context. Caller must ensure that the contents of the
119 * record pointed to by @c do not change during the execution
122 * Returns: a value suitable for writing into a PRCI PLL configuration
125 static u32 __prci_wrpll_pack(const struct wrpll_cfg *c)
129 r |= c->divr << PRCI_COREPLLCFG0_DIVR_SHIFT;
130 r |= c->divf << PRCI_COREPLLCFG0_DIVF_SHIFT;
131 r |= c->divq << PRCI_COREPLLCFG0_DIVQ_SHIFT;
132 r |= c->range << PRCI_COREPLLCFG0_RANGE_SHIFT;
134 /* external feedback mode not supported */
135 r |= PRCI_COREPLLCFG0_FSE_MASK;
141 * __prci_wrpll_read_cfg0() - read the WRPLL configuration from the PRCI
143 * @pwd: PRCI WRPLL metadata
145 * Read the current configuration of the PLL identified by @pwd from
146 * the PRCI identified by @pd, and store it into the local configuration
149 * Context: Any context. Caller must prevent the records pointed to by
150 * @pd and @pwd from changing during execution.
152 static void __prci_wrpll_read_cfg0(struct __prci_data *pd,
153 struct __prci_wrpll_data *pwd)
155 __prci_wrpll_unpack(&pwd->c, __prci_readl(pd, pwd->cfg0_offs));
159 * __prci_wrpll_write_cfg0() - write WRPLL configuration into the PRCI
161 * @pwd: PRCI WRPLL metadata
162 * @c: WRPLL configuration record to write
164 * Write the WRPLL configuration described by @c into the WRPLL
165 * configuration register identified by @pwd in the PRCI instance
166 * described by @c. Make a cached copy of the WRPLL's current
167 * configuration so it can be used by other code.
169 * Context: Any context. Caller must prevent the records pointed to by
170 * @pd and @pwd from changing during execution.
172 static void __prci_wrpll_write_cfg0(struct __prci_data *pd,
173 struct __prci_wrpll_data *pwd,
176 __prci_writel(__prci_wrpll_pack(c), pwd->cfg0_offs, pd);
178 memcpy(&pwd->c, c, sizeof(*c));
182 * __prci_wrpll_write_cfg1() - write Clock enable/disable configuration
185 * @pwd: PRCI WRPLL metadata
186 * @enable: Clock enable or disable value
188 static void __prci_wrpll_write_cfg1(struct __prci_data *pd,
189 struct __prci_wrpll_data *pwd,
192 __prci_writel(enable, pwd->cfg1_offs, pd);
195 unsigned long sifive_prci_wrpll_recalc_rate(struct __prci_clock *pc,
196 unsigned long parent_rate)
198 struct __prci_wrpll_data *pwd = pc->pwd;
200 return wrpll_calc_output_rate(&pwd->c, parent_rate);
203 unsigned long sifive_prci_wrpll_round_rate(struct __prci_clock *pc,
205 unsigned long *parent_rate)
207 struct __prci_wrpll_data *pwd = pc->pwd;
210 memcpy(&c, &pwd->c, sizeof(c));
212 wrpll_configure_for_rate(&c, rate, *parent_rate);
214 return wrpll_calc_output_rate(&c, *parent_rate);
217 int sifive_prci_wrpll_set_rate(struct __prci_clock *pc,
219 unsigned long parent_rate)
221 struct __prci_wrpll_data *pwd = pc->pwd;
222 struct __prci_data *pd = pc->pd;
225 r = wrpll_configure_for_rate(&pwd->c, rate, parent_rate);
229 if (pwd->enable_bypass)
230 pwd->enable_bypass(pd);
232 __prci_wrpll_write_cfg0(pd, pwd, &pwd->c);
234 udelay(wrpll_calc_max_lock_us(&pwd->c));
239 int sifive_prci_clock_enable(struct __prci_clock *pc, bool enable)
241 struct __prci_wrpll_data *pwd = pc->pwd;
242 struct __prci_data *pd = pc->pd;
245 __prci_wrpll_write_cfg1(pd, pwd, PRCI_COREPLLCFG1_CKE_MASK);
247 if (pwd->disable_bypass)
248 pwd->disable_bypass(pd);
250 if (pwd->release_reset)
251 pwd->release_reset(pd);
255 if (pwd->enable_bypass)
256 pwd->enable_bypass(pd);
258 r = __prci_readl(pd, pwd->cfg1_offs);
259 r &= ~PRCI_COREPLLCFG1_CKE_MASK;
261 __prci_wrpll_write_cfg1(pd, pwd, r);
267 /* TLCLKSEL clock integration */
269 unsigned long sifive_prci_tlclksel_recalc_rate(struct __prci_clock *pc,
270 unsigned long parent_rate)
272 struct __prci_data *pd = pc->pd;
276 v = __prci_readl(pd, PRCI_CLKMUXSTATUSREG_OFFSET);
277 v &= PRCI_CLKMUXSTATUSREG_TLCLKSEL_STATUS_MASK;
280 return div_u64(parent_rate, div);
283 /* HFPCLK clock integration */
285 unsigned long sifive_prci_hfpclkplldiv_recalc_rate(struct __prci_clock *pc,
286 unsigned long parent_rate)
288 struct __prci_data *pd = pc->pd;
289 u32 div = __prci_readl(pd, PRCI_HFPCLKPLLDIV_OFFSET);
291 return div_u64(parent_rate, div + 2);
295 * sifive_prci_coreclksel_use_final_corepll() - switch the CORECLK mux to output
297 * @pd: struct __prci_data * for the PRCI containing the CORECLK mux reg
299 * Switch the CORECLK mux to the final COREPLL output clock; return once
302 * Context: Any context. Caller must prevent concurrent changes to the
303 * PRCI_CORECLKSEL_OFFSET register.
305 void sifive_prci_coreclksel_use_final_corepll(struct __prci_data *pd)
309 r = __prci_readl(pd, PRCI_CORECLKSEL_OFFSET);
310 r &= ~PRCI_CORECLKSEL_CORECLKSEL_MASK;
311 __prci_writel(r, PRCI_CORECLKSEL_OFFSET, pd);
313 r = __prci_readl(pd, PRCI_CORECLKSEL_OFFSET); /* barrier */
317 * sifive_prci_corepllsel_use_dvfscorepll() - switch the COREPLL mux to
318 * output DVFS_COREPLL
319 * @pd: struct __prci_data * for the PRCI containing the COREPLL mux reg
321 * Switch the COREPLL mux to the DVFSCOREPLL output clock; return once complete.
323 * Context: Any context. Caller must prevent concurrent changes to the
324 * PRCI_COREPLLSEL_OFFSET register.
326 void sifive_prci_corepllsel_use_dvfscorepll(struct __prci_data *pd)
330 r = __prci_readl(pd, PRCI_COREPLLSEL_OFFSET);
331 r |= PRCI_COREPLLSEL_COREPLLSEL_MASK;
332 __prci_writel(r, PRCI_COREPLLSEL_OFFSET, pd);
334 r = __prci_readl(pd, PRCI_COREPLLSEL_OFFSET); /* barrier */
338 * sifive_prci_corepllsel_use_corepll() - switch the COREPLL mux to
340 * @pd: struct __prci_data * for the PRCI containing the COREPLL mux reg
342 * Switch the COREPLL mux to the COREPLL output clock; return once complete.
344 * Context: Any context. Caller must prevent concurrent changes to the
345 * PRCI_COREPLLSEL_OFFSET register.
347 void sifive_prci_corepllsel_use_corepll(struct __prci_data *pd)
351 r = __prci_readl(pd, PRCI_COREPLLSEL_OFFSET);
352 r &= ~PRCI_COREPLLSEL_COREPLLSEL_MASK;
353 __prci_writel(r, PRCI_COREPLLSEL_OFFSET, pd);
355 r = __prci_readl(pd, PRCI_COREPLLSEL_OFFSET); /* barrier */
359 * sifive_prci_hfpclkpllsel_use_hfclk() - switch the HFPCLKPLL mux to
361 * @pd: struct __prci_data * for the PRCI containing the HFPCLKPLL mux reg
363 * Switch the HFPCLKPLL mux to the HFCLK input source; return once complete.
365 * Context: Any context. Caller must prevent concurrent changes to the
366 * PRCI_HFPCLKPLLSEL_OFFSET register.
368 void sifive_prci_hfpclkpllsel_use_hfclk(struct __prci_data *pd)
372 r = __prci_readl(pd, PRCI_HFPCLKPLLSEL_OFFSET);
373 r |= PRCI_HFPCLKPLLSEL_HFPCLKPLLSEL_MASK;
374 __prci_writel(r, PRCI_HFPCLKPLLSEL_OFFSET, pd);
376 r = __prci_readl(pd, PRCI_HFPCLKPLLSEL_OFFSET); /* barrier */
380 * sifive_prci_hfpclkpllsel_use_hfpclkpll() - switch the HFPCLKPLL mux to
382 * @pd: struct __prci_data * for the PRCI containing the HFPCLKPLL mux reg
384 * Switch the HFPCLKPLL mux to the HFPCLKPLL output clock; return once complete.
386 * Context: Any context. Caller must prevent concurrent changes to the
387 * PRCI_HFPCLKPLLSEL_OFFSET register.
389 void sifive_prci_hfpclkpllsel_use_hfpclkpll(struct __prci_data *pd)
393 r = __prci_readl(pd, PRCI_HFPCLKPLLSEL_OFFSET);
394 r &= ~PRCI_HFPCLKPLLSEL_HFPCLKPLLSEL_MASK;
395 __prci_writel(r, PRCI_HFPCLKPLLSEL_OFFSET, pd);
397 r = __prci_readl(pd, PRCI_HFPCLKPLLSEL_OFFSET); /* barrier */
400 static int __prci_consumer_reset(const char *rst_name, bool trigger)
403 struct reset_ctl rst_sig;
406 ret = uclass_get_device_by_driver(UCLASS_RESET,
407 DM_DRIVER_GET(sifive_reset),
410 dev_err(dev, "Reset driver not found: %d\n", ret);
414 ret = reset_get_by_name(dev, rst_name, &rst_sig);
416 dev_err(dev, "failed to get %s reset\n", rst_name);
420 if (reset_valid(&rst_sig)) {
422 ret = reset_deassert(&rst_sig);
424 ret = reset_assert(&rst_sig);
426 dev_err(dev, "failed to trigger reset id = %ld\n",
436 * sifive_prci_ddr_release_reset() - Release DDR reset
437 * @pd: struct __prci_data * for the PRCI containing the DDRCLK mux reg
440 void sifive_prci_ddr_release_reset(struct __prci_data *pd)
442 /* Release DDR ctrl reset */
443 __prci_consumer_reset("ddr_ctrl", true);
445 /* HACK to get the '1 full controller clock cycle'. */
446 asm volatile ("fence");
448 /* Release DDR AXI reset */
449 __prci_consumer_reset("ddr_axi", true);
451 /* Release DDR AHB reset */
452 __prci_consumer_reset("ddr_ahb", true);
454 /* Release DDR PHY reset */
455 __prci_consumer_reset("ddr_phy", true);
457 /* HACK to get the '1 full controller clock cycle'. */
458 asm volatile ("fence");
461 * These take like 16 cycles to actually propagate. We can't go sending
462 * stuff before they come out of reset. So wait.
464 for (int i = 0; i < 256; i++)
465 asm volatile ("nop");
469 * sifive_prci_ethernet_release_reset() - Release ethernet reset
470 * @pd: struct __prci_data * for the PRCI containing the Ethernet CLK mux reg
473 void sifive_prci_ethernet_release_reset(struct __prci_data *pd)
475 /* Release GEMGXL reset */
476 __prci_consumer_reset("gemgxl_reset", true);
478 /* Procmon => core clock */
479 __prci_writel(PRCI_PROCMONCFG_CORE_CLOCK_MASK, PRCI_PROCMONCFG_OFFSET,
482 /* Release Chiplink reset */
483 __prci_consumer_reset("cltx_reset", true);
487 * sifive_prci_cltx_release_reset() - Release cltx reset
488 * @pd: struct __prci_data * for the PRCI containing the Ethernet CLK mux reg
491 void sifive_prci_cltx_release_reset(struct __prci_data *pd)
493 /* Release CLTX reset */
494 __prci_consumer_reset("cltx_reset", true);
497 /* Core clock mux control */
500 * sifive_prci_coreclksel_use_hfclk() - switch the CORECLK mux to output HFCLK
501 * @pd: struct __prci_data * for the PRCI containing the CORECLK mux reg
503 * Switch the CORECLK mux to the HFCLK input source; return once complete.
505 * Context: Any context. Caller must prevent concurrent changes to the
506 * PRCI_CORECLKSEL_OFFSET register.
508 void sifive_prci_coreclksel_use_hfclk(struct __prci_data *pd)
512 r = __prci_readl(pd, PRCI_CORECLKSEL_OFFSET);
513 r |= PRCI_CORECLKSEL_CORECLKSEL_MASK;
514 __prci_writel(r, PRCI_CORECLKSEL_OFFSET, pd);
516 r = __prci_readl(pd, PRCI_CORECLKSEL_OFFSET); /* barrier */
520 * sifive_prci_coreclksel_use_corepll() - switch the CORECLK mux to output COREPLL
521 * @pd: struct __prci_data * for the PRCI containing the CORECLK mux reg
523 * Switch the CORECLK mux to the PLL output clock; return once complete.
525 * Context: Any context. Caller must prevent concurrent changes to the
526 * PRCI_CORECLKSEL_OFFSET register.
528 void sifive_prci_coreclksel_use_corepll(struct __prci_data *pd)
532 r = __prci_readl(pd, PRCI_CORECLKSEL_OFFSET);
533 r &= ~PRCI_CORECLKSEL_CORECLKSEL_MASK;
534 __prci_writel(r, PRCI_CORECLKSEL_OFFSET, pd);
536 r = __prci_readl(pd, PRCI_CORECLKSEL_OFFSET); /* barrier */
539 static ulong sifive_prci_parent_rate(struct __prci_clock *pc, struct prci_clk_desc *data)
543 struct __prci_clock *p;
545 if (strcmp(pc->parent_name, "corepll") == 0 ||
546 strcmp(pc->parent_name, "hfpclkpll") == 0) {
547 for (i = 0; i < data->num_clks; i++) {
548 if (strcmp(pc->parent_name, data->clks[i].name) == 0)
552 if (i >= data->num_clks)
556 if (!p->pd || !p->ops->recalc_rate)
559 return p->ops->recalc_rate(p, sifive_prci_parent_rate(p, data));
562 if (strcmp(pc->parent_name, "rtcclk") == 0)
563 parent_rate = clk_get_rate(&pc->pd->parent_rtcclk);
565 parent_rate = clk_get_rate(&pc->pd->parent_hfclk);
570 static ulong sifive_prci_get_rate(struct clk *clk)
572 struct __prci_clock *pc;
573 struct prci_clk_desc *data =
574 (struct prci_clk_desc *)dev_get_driver_data(clk->dev);
576 if (data->num_clks <= clk->id)
579 pc = &data->clks[clk->id];
580 if (!pc->pd || !pc->ops->recalc_rate)
583 return pc->ops->recalc_rate(pc, sifive_prci_parent_rate(pc, data));
586 static ulong sifive_prci_set_rate(struct clk *clk, ulong rate)
589 struct __prci_clock *pc;
590 struct prci_clk_desc *data =
591 (struct prci_clk_desc *)dev_get_driver_data(clk->dev);
593 if (data->num_clks <= clk->id)
596 pc = &data->clks[clk->id];
597 if (!pc->pd || !pc->ops->set_rate)
600 err = pc->ops->set_rate(pc, rate, sifive_prci_parent_rate(pc, data));
607 static int sifive_prci_enable(struct clk *clk)
609 struct __prci_clock *pc;
611 struct prci_clk_desc *data =
612 (struct prci_clk_desc *)dev_get_driver_data(clk->dev);
614 if (data->num_clks <= clk->id)
617 pc = &data->clks[clk->id];
621 if (pc->ops->enable_clk)
622 ret = pc->ops->enable_clk(pc, 1);
627 static int sifive_prci_disable(struct clk *clk)
629 struct __prci_clock *pc;
631 struct prci_clk_desc *data =
632 (struct prci_clk_desc *)dev_get_driver_data(clk->dev);
634 if (data->num_clks <= clk->id)
637 pc = &data->clks[clk->id];
641 if (pc->ops->enable_clk)
642 ret = pc->ops->enable_clk(pc, 0);
647 static int sifive_prci_probe(struct udevice *dev)
650 struct __prci_clock *pc;
651 struct __prci_data *pd = dev_get_priv(dev);
653 struct prci_clk_desc *data =
654 (struct prci_clk_desc *)dev_get_driver_data(dev);
656 pd->va = dev_read_addr_ptr(dev);
660 err = clk_get_by_index(dev, 0, &pd->parent_hfclk);
664 err = clk_get_by_index(dev, 1, &pd->parent_rtcclk);
668 for (i = 0; i < data->num_clks; ++i) {
672 __prci_wrpll_read_cfg0(pd, pc->pwd);
675 if (IS_ENABLED(CONFIG_SPL_BUILD)) {
676 if (device_is_compatible(dev, "sifive,fu740-c000-prci")) {
678 unsigned long parent_rate;
680 prci_pll_reg = readl(pd->va + PRCI_PRCIPLL_OFFSET);
682 if (prci_pll_reg & PRCI_PRCIPLL_HFPCLKPLL) {
684 * Only initialize the HFPCLK PLL. In this
685 * case the design uses hfpclk to drive
688 pc = &data->clks[FU740_PRCI_CLK_HFPCLKPLL];
689 parent_rate = sifive_prci_parent_rate(pc, data);
690 sifive_prci_wrpll_set_rate(pc, 260000000,
692 pc->ops->enable_clk(pc, 1);
693 } else if (prci_pll_reg & PRCI_PRCIPLL_CLTXPLL) {
695 pc = &data->clks[FU740_PRCI_CLK_CLTXPLL];
696 parent_rate = sifive_prci_parent_rate(pc, data);
697 sifive_prci_wrpll_set_rate(pc, 260000000,
699 pc->ops->enable_clk(pc, 1);
707 static struct clk_ops sifive_prci_ops = {
708 .set_rate = sifive_prci_set_rate,
709 .get_rate = sifive_prci_get_rate,
710 .enable = sifive_prci_enable,
711 .disable = sifive_prci_disable,
714 static int sifive_clk_bind(struct udevice *dev)
716 return sifive_reset_bind(dev, PRCI_DEVICERESETCNT);
719 static const struct udevice_id sifive_prci_ids[] = {
720 { .compatible = "sifive,fu540-c000-prci", .data = (ulong)&prci_clk_fu540 },
721 { .compatible = "sifive,fu740-c000-prci", .data = (ulong)&prci_clk_fu740 },
725 U_BOOT_DRIVER(sifive_prci) = {
726 .name = "sifive-prci",
728 .of_match = sifive_prci_ids,
729 .probe = sifive_prci_probe,
730 .ops = &sifive_prci_ops,
731 .priv_auto = sizeof(struct __prci_data),
732 .bind = sifive_clk_bind,