drivers/clk/samsung/clk-pll.h

   1 /*
   2  * Copyright (c) 2013 Samsung Electronics Co., Ltd.
   3  * Copyright (c) 2013 Linaro Ltd.
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License version 2 as
   7  * published by the Free Software Foundation.
   8  *
   9  * Common Clock Framework support for all PLL's in Samsung platforms
  10 */
  11
  12 #ifndef __SAMSUNG_CLK_PLL_H
  13 #define __SAMSUNG_CLK_PLL_H
  14
  15 enum samsung_pll_type {
  16         pll_2126,
  17         pll_3000,
  18         pll_35xx,
  19         pll_36xx,
  20         pll_2550,
  21         pll_2650,
  22         pll_4500,
  23         pll_4502,
  24         pll_4508,
  25         pll_4600,
  26         pll_4650,
  27         pll_4650c,
  28         pll_6552,
  29         pll_6552_s3c2416,
  30         pll_6553,
  31         pll_s3c2410_mpll,
  32         pll_s3c2410_upll,
  33         pll_s3c2440_mpll,
  34         pll_2550xx,
  35         pll_2650xx,
  36         pll_1450x,
  37         pll_1451x,
  38         pll_1452x,
  39         pll_1460x,
  40 };
  41
  42 #define PLL_35XX_RATE(_rate, _m, _p, _s)                        \
  43         {                                                       \
  44                 .rate   =       (_rate),                                \
  45                 .mdiv   =       (_m),                           \
  46                 .pdiv   =       (_p),                           \
  47                 .sdiv   =       (_s),                           \
  48         }
  49
  50 #define PLL_36XX_RATE(_rate, _m, _p, _s, _k)                    \
  51         {                                                       \
  52                 .rate   =       (_rate),                                \
  53                 .mdiv   =       (_m),                           \
  54                 .pdiv   =       (_p),                           \
  55                 .sdiv   =       (_s),                           \
  56                 .kdiv   =       (_k),                           \
  57         }
  58
  59 #define PLL_45XX_RATE(_rate, _m, _p, _s, _afc)                  \
  60         {                                                       \
  61                 .rate   =       (_rate),                        \
  62                 .mdiv   =       (_m),                           \
  63                 .pdiv   =       (_p),                           \
  64                 .sdiv   =       (_s),                           \
  65                 .afc    =       (_afc),                         \
  66         }
  67
  68 #define PLL_4600_RATE(_rate, _m, _p, _s, _k, _vsel)             \
  69         {                                                       \
  70                 .rate   =       (_rate),                        \
  71                 .mdiv   =       (_m),                           \
  72                 .pdiv   =       (_p),                           \
  73                 .sdiv   =       (_s),                           \
  74                 .kdiv   =       (_k),                           \
  75                 .vsel   =       (_vsel),                        \
  76         }
  77
  78 #define PLL_4650_RATE(_rate, _m, _p, _s, _k, _mfr, _mrr, _vsel) \
  79         {                                                       \
  80                 .rate   =       (_rate),                        \
  81                 .mdiv   =       (_m),                           \
  82                 .pdiv   =       (_p),                           \
  83                 .sdiv   =       (_s),                           \
  84                 .kdiv   =       (_k),                           \
  85                 .mfr    =       (_mfr),                         \
  86                 .mrr    =       (_mrr),                         \
  87                 .vsel   =       (_vsel),                        \
  88         }
  89
  90 /* NOTE: Rate table should be kept sorted in descending order. */
  91
  92 struct samsung_pll_rate_table {
  93         unsigned int rate;
  94         unsigned int pdiv;
  95         unsigned int mdiv;
  96         unsigned int sdiv;
  97         unsigned int kdiv;
  98         unsigned int afc;
  99         unsigned int mfr;
 100         unsigned int mrr;
 101         unsigned int vsel;
 102 };
 103
 104 extern struct clk * __init samsung_clk_register_pll2550x(const char *name,
 105                         const char *pname, const void __iomem *reg_base,
 106                         const unsigned long offset);
 107
 108 #endif /* __SAMSUNG_CLK_PLL_H */