1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2013 Samsung Electronics Co., Ltd.
4 * Copyright (c) 2013 Linaro Ltd.
6 * This file contains the utility functions to register the pll clocks.
9 #include <linux/errno.h>
10 #include <linux/hrtimer.h>
11 #include <linux/iopoll.h>
12 #include <linux/delay.h>
13 #include <linux/slab.h>
14 #include <linux/timekeeping.h>
15 #include <linux/clk-provider.h>
20 #define PLL_TIMEOUT_US 20000U
21 #define PLL_TIMEOUT_LOOPS 1000000U
23 struct samsung_clk_pll {
25 void __iomem *lock_reg;
26 void __iomem *con_reg;
27 /* PLL enable control bit offset in @con_reg register */
28 unsigned short enable_offs;
29 /* PLL lock status bit offset in @con_reg register */
30 unsigned short lock_offs;
31 enum samsung_pll_type type;
32 unsigned int rate_count;
33 const struct samsung_pll_rate_table *rate_table;
36 #define to_clk_pll(_hw) container_of(_hw, struct samsung_clk_pll, hw)
38 static const struct samsung_pll_rate_table *samsung_get_pll_settings(
39 struct samsung_clk_pll *pll, unsigned long rate)
41 const struct samsung_pll_rate_table *rate_table = pll->rate_table;
44 for (i = 0; i < pll->rate_count; i++) {
45 if (rate == rate_table[i].rate)
46 return &rate_table[i];
52 static long samsung_pll_round_rate(struct clk_hw *hw,
53 unsigned long drate, unsigned long *prate)
55 struct samsung_clk_pll *pll = to_clk_pll(hw);
56 const struct samsung_pll_rate_table *rate_table = pll->rate_table;
59 /* Assumming rate_table is in descending order */
60 for (i = 0; i < pll->rate_count; i++) {
61 if (drate >= rate_table[i].rate)
62 return rate_table[i].rate;
65 /* return minimum supported value */
66 return rate_table[i - 1].rate;
69 static bool pll_early_timeout = true;
71 static int __init samsung_pll_disable_early_timeout(void)
73 pll_early_timeout = false;
76 arch_initcall(samsung_pll_disable_early_timeout);
78 /* Wait until the PLL is locked */
79 static int samsung_pll_lock_wait(struct samsung_clk_pll *pll,
80 unsigned int reg_mask)
86 * This function might be called when the timekeeping API can't be used
87 * to detect timeouts. One situation is when the clocksource is not yet
88 * initialized, another when the timekeeping is suspended. udelay() also
89 * cannot be used when the clocksource is not running on arm64, since
90 * the current timer is used as cycle counter. So a simple busy loop
91 * is used here in that special cases. The limit of iterations has been
92 * derived from experimental measurements of various PLLs on multiple
93 * Exynos SoC variants. Single register read time was usually in range
94 * 0.4...1.5 us, never less than 0.4 us.
96 if (pll_early_timeout || timekeeping_suspended) {
97 i = PLL_TIMEOUT_LOOPS;
99 if (readl_relaxed(pll->con_reg) & reg_mask)
106 ret = readl_relaxed_poll_timeout_atomic(pll->con_reg, val,
107 val & reg_mask, 0, PLL_TIMEOUT_US);
111 pr_err("Could not lock PLL %s\n", clk_hw_get_name(&pll->hw));
116 static int samsung_pll3xxx_enable(struct clk_hw *hw)
118 struct samsung_clk_pll *pll = to_clk_pll(hw);
121 tmp = readl_relaxed(pll->con_reg);
122 tmp |= BIT(pll->enable_offs);
123 writel_relaxed(tmp, pll->con_reg);
125 return samsung_pll_lock_wait(pll, BIT(pll->lock_offs));
128 static void samsung_pll3xxx_disable(struct clk_hw *hw)
130 struct samsung_clk_pll *pll = to_clk_pll(hw);
133 tmp = readl_relaxed(pll->con_reg);
134 tmp &= ~BIT(pll->enable_offs);
135 writel_relaxed(tmp, pll->con_reg);
142 #define PLL2126_MDIV_MASK (0xff)
143 #define PLL2126_PDIV_MASK (0x3f)
144 #define PLL2126_SDIV_MASK (0x3)
145 #define PLL2126_MDIV_SHIFT (16)
146 #define PLL2126_PDIV_SHIFT (8)
147 #define PLL2126_SDIV_SHIFT (0)
149 static unsigned long samsung_pll2126_recalc_rate(struct clk_hw *hw,
150 unsigned long parent_rate)
152 struct samsung_clk_pll *pll = to_clk_pll(hw);
153 u32 pll_con, mdiv, pdiv, sdiv;
154 u64 fvco = parent_rate;
156 pll_con = readl_relaxed(pll->con_reg);
157 mdiv = (pll_con >> PLL2126_MDIV_SHIFT) & PLL2126_MDIV_MASK;
158 pdiv = (pll_con >> PLL2126_PDIV_SHIFT) & PLL2126_PDIV_MASK;
159 sdiv = (pll_con >> PLL2126_SDIV_SHIFT) & PLL2126_SDIV_MASK;
162 do_div(fvco, (pdiv + 2) << sdiv);
164 return (unsigned long)fvco;
167 static const struct clk_ops samsung_pll2126_clk_ops = {
168 .recalc_rate = samsung_pll2126_recalc_rate,
175 #define PLL3000_MDIV_MASK (0xff)
176 #define PLL3000_PDIV_MASK (0x3)
177 #define PLL3000_SDIV_MASK (0x3)
178 #define PLL3000_MDIV_SHIFT (16)
179 #define PLL3000_PDIV_SHIFT (8)
180 #define PLL3000_SDIV_SHIFT (0)
182 static unsigned long samsung_pll3000_recalc_rate(struct clk_hw *hw,
183 unsigned long parent_rate)
185 struct samsung_clk_pll *pll = to_clk_pll(hw);
186 u32 pll_con, mdiv, pdiv, sdiv;
187 u64 fvco = parent_rate;
189 pll_con = readl_relaxed(pll->con_reg);
190 mdiv = (pll_con >> PLL3000_MDIV_SHIFT) & PLL3000_MDIV_MASK;
191 pdiv = (pll_con >> PLL3000_PDIV_SHIFT) & PLL3000_PDIV_MASK;
192 sdiv = (pll_con >> PLL3000_SDIV_SHIFT) & PLL3000_SDIV_MASK;
194 fvco *= (2 * (mdiv + 8));
195 do_div(fvco, pdiv << sdiv);
197 return (unsigned long)fvco;
200 static const struct clk_ops samsung_pll3000_clk_ops = {
201 .recalc_rate = samsung_pll3000_recalc_rate,
207 /* Maximum lock time can be 270 * PDIV cycles */
208 #define PLL35XX_LOCK_FACTOR (270)
210 #define PLL35XX_MDIV_MASK (0x3FF)
211 #define PLL35XX_PDIV_MASK (0x3F)
212 #define PLL35XX_SDIV_MASK (0x7)
213 #define PLL35XX_MDIV_SHIFT (16)
214 #define PLL35XX_PDIV_SHIFT (8)
215 #define PLL35XX_SDIV_SHIFT (0)
216 #define PLL35XX_LOCK_STAT_SHIFT (29)
217 #define PLL35XX_ENABLE_SHIFT (31)
219 static unsigned long samsung_pll35xx_recalc_rate(struct clk_hw *hw,
220 unsigned long parent_rate)
222 struct samsung_clk_pll *pll = to_clk_pll(hw);
223 u32 mdiv, pdiv, sdiv, pll_con;
224 u64 fvco = parent_rate;
226 pll_con = readl_relaxed(pll->con_reg);
227 mdiv = (pll_con >> PLL35XX_MDIV_SHIFT) & PLL35XX_MDIV_MASK;
228 pdiv = (pll_con >> PLL35XX_PDIV_SHIFT) & PLL35XX_PDIV_MASK;
229 sdiv = (pll_con >> PLL35XX_SDIV_SHIFT) & PLL35XX_SDIV_MASK;
232 do_div(fvco, (pdiv << sdiv));
234 return (unsigned long)fvco;
237 static inline bool samsung_pll35xx_mp_change(
238 const struct samsung_pll_rate_table *rate, u32 pll_con)
240 u32 old_mdiv, old_pdiv;
242 old_mdiv = (pll_con >> PLL35XX_MDIV_SHIFT) & PLL35XX_MDIV_MASK;
243 old_pdiv = (pll_con >> PLL35XX_PDIV_SHIFT) & PLL35XX_PDIV_MASK;
245 return (rate->mdiv != old_mdiv || rate->pdiv != old_pdiv);
248 static int samsung_pll35xx_set_rate(struct clk_hw *hw, unsigned long drate,
251 struct samsung_clk_pll *pll = to_clk_pll(hw);
252 const struct samsung_pll_rate_table *rate;
255 /* Get required rate settings from table */
256 rate = samsung_get_pll_settings(pll, drate);
258 pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__,
259 drate, clk_hw_get_name(hw));
263 tmp = readl_relaxed(pll->con_reg);
265 if (!(samsung_pll35xx_mp_change(rate, tmp))) {
266 /* If only s change, change just s value only*/
267 tmp &= ~(PLL35XX_SDIV_MASK << PLL35XX_SDIV_SHIFT);
268 tmp |= rate->sdiv << PLL35XX_SDIV_SHIFT;
269 writel_relaxed(tmp, pll->con_reg);
274 /* Set PLL lock time. */
275 writel_relaxed(rate->pdiv * PLL35XX_LOCK_FACTOR,
278 /* Change PLL PMS values */
279 tmp &= ~((PLL35XX_MDIV_MASK << PLL35XX_MDIV_SHIFT) |
280 (PLL35XX_PDIV_MASK << PLL35XX_PDIV_SHIFT) |
281 (PLL35XX_SDIV_MASK << PLL35XX_SDIV_SHIFT));
282 tmp |= (rate->mdiv << PLL35XX_MDIV_SHIFT) |
283 (rate->pdiv << PLL35XX_PDIV_SHIFT) |
284 (rate->sdiv << PLL35XX_SDIV_SHIFT);
285 writel_relaxed(tmp, pll->con_reg);
287 /* Wait for PLL lock if the PLL is enabled */
288 if (tmp & BIT(pll->enable_offs))
289 return samsung_pll_lock_wait(pll, BIT(pll->lock_offs));
294 static const struct clk_ops samsung_pll35xx_clk_ops = {
295 .recalc_rate = samsung_pll35xx_recalc_rate,
296 .round_rate = samsung_pll_round_rate,
297 .set_rate = samsung_pll35xx_set_rate,
298 .enable = samsung_pll3xxx_enable,
299 .disable = samsung_pll3xxx_disable,
302 static const struct clk_ops samsung_pll35xx_clk_min_ops = {
303 .recalc_rate = samsung_pll35xx_recalc_rate,
309 /* Maximum lock time can be 3000 * PDIV cycles */
310 #define PLL36XX_LOCK_FACTOR (3000)
312 #define PLL36XX_KDIV_MASK (0xFFFF)
313 #define PLL36XX_MDIV_MASK (0x1FF)
314 #define PLL36XX_PDIV_MASK (0x3F)
315 #define PLL36XX_SDIV_MASK (0x7)
316 #define PLL36XX_MDIV_SHIFT (16)
317 #define PLL36XX_PDIV_SHIFT (8)
318 #define PLL36XX_SDIV_SHIFT (0)
319 #define PLL36XX_KDIV_SHIFT (0)
320 #define PLL36XX_LOCK_STAT_SHIFT (29)
321 #define PLL36XX_ENABLE_SHIFT (31)
323 static unsigned long samsung_pll36xx_recalc_rate(struct clk_hw *hw,
324 unsigned long parent_rate)
326 struct samsung_clk_pll *pll = to_clk_pll(hw);
327 u32 mdiv, pdiv, sdiv, pll_con0, pll_con1;
329 u64 fvco = parent_rate;
331 pll_con0 = readl_relaxed(pll->con_reg);
332 pll_con1 = readl_relaxed(pll->con_reg + 4);
333 mdiv = (pll_con0 >> PLL36XX_MDIV_SHIFT) & PLL36XX_MDIV_MASK;
334 pdiv = (pll_con0 >> PLL36XX_PDIV_SHIFT) & PLL36XX_PDIV_MASK;
335 sdiv = (pll_con0 >> PLL36XX_SDIV_SHIFT) & PLL36XX_SDIV_MASK;
336 kdiv = (s16)(pll_con1 & PLL36XX_KDIV_MASK);
338 fvco *= (mdiv << 16) + kdiv;
339 do_div(fvco, (pdiv << sdiv));
342 return (unsigned long)fvco;
345 static inline bool samsung_pll36xx_mpk_change(
346 const struct samsung_pll_rate_table *rate, u32 pll_con0, u32 pll_con1)
348 u32 old_mdiv, old_pdiv, old_kdiv;
350 old_mdiv = (pll_con0 >> PLL36XX_MDIV_SHIFT) & PLL36XX_MDIV_MASK;
351 old_pdiv = (pll_con0 >> PLL36XX_PDIV_SHIFT) & PLL36XX_PDIV_MASK;
352 old_kdiv = (pll_con1 >> PLL36XX_KDIV_SHIFT) & PLL36XX_KDIV_MASK;
354 return (rate->mdiv != old_mdiv || rate->pdiv != old_pdiv ||
355 rate->kdiv != old_kdiv);
358 static int samsung_pll36xx_set_rate(struct clk_hw *hw, unsigned long drate,
359 unsigned long parent_rate)
361 struct samsung_clk_pll *pll = to_clk_pll(hw);
362 u32 pll_con0, pll_con1;
363 const struct samsung_pll_rate_table *rate;
365 rate = samsung_get_pll_settings(pll, drate);
367 pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__,
368 drate, clk_hw_get_name(hw));
372 pll_con0 = readl_relaxed(pll->con_reg);
373 pll_con1 = readl_relaxed(pll->con_reg + 4);
375 if (!(samsung_pll36xx_mpk_change(rate, pll_con0, pll_con1))) {
376 /* If only s change, change just s value only*/
377 pll_con0 &= ~(PLL36XX_SDIV_MASK << PLL36XX_SDIV_SHIFT);
378 pll_con0 |= (rate->sdiv << PLL36XX_SDIV_SHIFT);
379 writel_relaxed(pll_con0, pll->con_reg);
384 /* Set PLL lock time. */
385 writel_relaxed(rate->pdiv * PLL36XX_LOCK_FACTOR, pll->lock_reg);
387 /* Change PLL PMS values */
388 pll_con0 &= ~((PLL36XX_MDIV_MASK << PLL36XX_MDIV_SHIFT) |
389 (PLL36XX_PDIV_MASK << PLL36XX_PDIV_SHIFT) |
390 (PLL36XX_SDIV_MASK << PLL36XX_SDIV_SHIFT));
391 pll_con0 |= (rate->mdiv << PLL36XX_MDIV_SHIFT) |
392 (rate->pdiv << PLL36XX_PDIV_SHIFT) |
393 (rate->sdiv << PLL36XX_SDIV_SHIFT);
394 writel_relaxed(pll_con0, pll->con_reg);
396 pll_con1 &= ~(PLL36XX_KDIV_MASK << PLL36XX_KDIV_SHIFT);
397 pll_con1 |= rate->kdiv << PLL36XX_KDIV_SHIFT;
398 writel_relaxed(pll_con1, pll->con_reg + 4);
400 if (pll_con0 & BIT(pll->enable_offs))
401 return samsung_pll_lock_wait(pll, BIT(pll->lock_offs));
406 static const struct clk_ops samsung_pll36xx_clk_ops = {
407 .recalc_rate = samsung_pll36xx_recalc_rate,
408 .set_rate = samsung_pll36xx_set_rate,
409 .round_rate = samsung_pll_round_rate,
410 .enable = samsung_pll3xxx_enable,
411 .disable = samsung_pll3xxx_disable,
414 static const struct clk_ops samsung_pll36xx_clk_min_ops = {
415 .recalc_rate = samsung_pll36xx_recalc_rate,
419 * PLL0822x Clock Type
421 /* Maximum lock time can be 150 * PDIV cycles */
422 #define PLL0822X_LOCK_FACTOR (150)
424 #define PLL0822X_MDIV_MASK (0x3FF)
425 #define PLL0822X_PDIV_MASK (0x3F)
426 #define PLL0822X_SDIV_MASK (0x7)
427 #define PLL0822X_MDIV_SHIFT (16)
428 #define PLL0822X_PDIV_SHIFT (8)
429 #define PLL0822X_SDIV_SHIFT (0)
430 #define PLL0822X_LOCK_STAT_SHIFT (29)
431 #define PLL0822X_ENABLE_SHIFT (31)
433 static unsigned long samsung_pll0822x_recalc_rate(struct clk_hw *hw,
434 unsigned long parent_rate)
436 struct samsung_clk_pll *pll = to_clk_pll(hw);
437 u32 mdiv, pdiv, sdiv, pll_con3;
438 u64 fvco = parent_rate;
440 pll_con3 = readl_relaxed(pll->con_reg);
441 mdiv = (pll_con3 >> PLL0822X_MDIV_SHIFT) & PLL0822X_MDIV_MASK;
442 pdiv = (pll_con3 >> PLL0822X_PDIV_SHIFT) & PLL0822X_PDIV_MASK;
443 sdiv = (pll_con3 >> PLL0822X_SDIV_SHIFT) & PLL0822X_SDIV_MASK;
446 do_div(fvco, (pdiv << sdiv));
448 return (unsigned long)fvco;
451 static int samsung_pll0822x_set_rate(struct clk_hw *hw, unsigned long drate,
454 const struct samsung_pll_rate_table *rate;
455 struct samsung_clk_pll *pll = to_clk_pll(hw);
458 /* Get required rate settings from table */
459 rate = samsung_get_pll_settings(pll, drate);
461 pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__,
462 drate, clk_hw_get_name(hw));
466 /* Change PLL PMS values */
467 pll_con3 = readl_relaxed(pll->con_reg);
468 pll_con3 &= ~((PLL0822X_MDIV_MASK << PLL0822X_MDIV_SHIFT) |
469 (PLL0822X_PDIV_MASK << PLL0822X_PDIV_SHIFT) |
470 (PLL0822X_SDIV_MASK << PLL0822X_SDIV_SHIFT));
471 pll_con3 |= (rate->mdiv << PLL0822X_MDIV_SHIFT) |
472 (rate->pdiv << PLL0822X_PDIV_SHIFT) |
473 (rate->sdiv << PLL0822X_SDIV_SHIFT);
475 /* Set PLL lock time */
476 writel_relaxed(rate->pdiv * PLL0822X_LOCK_FACTOR,
479 /* Write PMS values */
480 writel_relaxed(pll_con3, pll->con_reg);
482 /* Wait for PLL lock if the PLL is enabled */
483 if (pll_con3 & BIT(pll->enable_offs))
484 return samsung_pll_lock_wait(pll, BIT(pll->lock_offs));
489 static const struct clk_ops samsung_pll0822x_clk_ops = {
490 .recalc_rate = samsung_pll0822x_recalc_rate,
491 .round_rate = samsung_pll_round_rate,
492 .set_rate = samsung_pll0822x_set_rate,
493 .enable = samsung_pll3xxx_enable,
494 .disable = samsung_pll3xxx_disable,
497 static const struct clk_ops samsung_pll0822x_clk_min_ops = {
498 .recalc_rate = samsung_pll0822x_recalc_rate,
502 * PLL0831x Clock Type
504 /* Maximum lock time can be 500 * PDIV cycles */
505 #define PLL0831X_LOCK_FACTOR (500)
507 #define PLL0831X_KDIV_MASK (0xFFFF)
508 #define PLL0831X_MDIV_MASK (0x1FF)
509 #define PLL0831X_PDIV_MASK (0x3F)
510 #define PLL0831X_SDIV_MASK (0x7)
511 #define PLL0831X_MDIV_SHIFT (16)
512 #define PLL0831X_PDIV_SHIFT (8)
513 #define PLL0831X_SDIV_SHIFT (0)
514 #define PLL0831X_KDIV_SHIFT (0)
515 #define PLL0831X_LOCK_STAT_SHIFT (29)
516 #define PLL0831X_ENABLE_SHIFT (31)
518 static unsigned long samsung_pll0831x_recalc_rate(struct clk_hw *hw,
519 unsigned long parent_rate)
521 struct samsung_clk_pll *pll = to_clk_pll(hw);
522 u32 mdiv, pdiv, sdiv, pll_con3, pll_con5;
524 u64 fvco = parent_rate;
526 pll_con3 = readl_relaxed(pll->con_reg);
527 pll_con5 = readl_relaxed(pll->con_reg + 8);
528 mdiv = (pll_con3 >> PLL0831X_MDIV_SHIFT) & PLL0831X_MDIV_MASK;
529 pdiv = (pll_con3 >> PLL0831X_PDIV_SHIFT) & PLL0831X_PDIV_MASK;
530 sdiv = (pll_con3 >> PLL0831X_SDIV_SHIFT) & PLL0831X_SDIV_MASK;
531 kdiv = (s16)((pll_con5 >> PLL0831X_KDIV_SHIFT) & PLL0831X_KDIV_MASK);
533 fvco *= (mdiv << 16) + kdiv;
534 do_div(fvco, (pdiv << sdiv));
537 return (unsigned long)fvco;
540 static int samsung_pll0831x_set_rate(struct clk_hw *hw, unsigned long drate,
541 unsigned long parent_rate)
543 const struct samsung_pll_rate_table *rate;
544 struct samsung_clk_pll *pll = to_clk_pll(hw);
545 u32 pll_con3, pll_con5;
547 /* Get required rate settings from table */
548 rate = samsung_get_pll_settings(pll, drate);
550 pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__,
551 drate, clk_hw_get_name(hw));
555 pll_con3 = readl_relaxed(pll->con_reg);
556 pll_con5 = readl_relaxed(pll->con_reg + 8);
558 /* Change PLL PMSK values */
559 pll_con3 &= ~((PLL0831X_MDIV_MASK << PLL0831X_MDIV_SHIFT) |
560 (PLL0831X_PDIV_MASK << PLL0831X_PDIV_SHIFT) |
561 (PLL0831X_SDIV_MASK << PLL0831X_SDIV_SHIFT));
562 pll_con3 |= (rate->mdiv << PLL0831X_MDIV_SHIFT) |
563 (rate->pdiv << PLL0831X_PDIV_SHIFT) |
564 (rate->sdiv << PLL0831X_SDIV_SHIFT);
565 pll_con5 &= ~(PLL0831X_KDIV_MASK << PLL0831X_KDIV_SHIFT);
567 * kdiv is 16-bit 2's complement (s16), but stored as unsigned int.
568 * Cast it to u16 to avoid leading 0xffff's in case of negative value.
570 pll_con5 |= ((u16)rate->kdiv << PLL0831X_KDIV_SHIFT);
572 /* Set PLL lock time */
573 writel_relaxed(rate->pdiv * PLL0831X_LOCK_FACTOR, pll->lock_reg);
575 /* Write PMSK values */
576 writel_relaxed(pll_con3, pll->con_reg);
577 writel_relaxed(pll_con5, pll->con_reg + 8);
579 /* Wait for PLL lock if the PLL is enabled */
580 if (pll_con3 & BIT(pll->enable_offs))
581 return samsung_pll_lock_wait(pll, BIT(pll->lock_offs));
586 static const struct clk_ops samsung_pll0831x_clk_ops = {
587 .recalc_rate = samsung_pll0831x_recalc_rate,
588 .set_rate = samsung_pll0831x_set_rate,
589 .round_rate = samsung_pll_round_rate,
590 .enable = samsung_pll3xxx_enable,
591 .disable = samsung_pll3xxx_disable,
594 static const struct clk_ops samsung_pll0831x_clk_min_ops = {
595 .recalc_rate = samsung_pll0831x_recalc_rate,
601 #define PLL4502_LOCK_FACTOR 400
602 #define PLL4508_LOCK_FACTOR 240
604 #define PLL45XX_MDIV_MASK (0x3FF)
605 #define PLL45XX_PDIV_MASK (0x3F)
606 #define PLL45XX_SDIV_MASK (0x7)
607 #define PLL45XX_AFC_MASK (0x1F)
608 #define PLL45XX_MDIV_SHIFT (16)
609 #define PLL45XX_PDIV_SHIFT (8)
610 #define PLL45XX_SDIV_SHIFT (0)
611 #define PLL45XX_AFC_SHIFT (0)
613 #define PLL45XX_ENABLE BIT(31)
614 #define PLL45XX_LOCKED BIT(29)
616 static unsigned long samsung_pll45xx_recalc_rate(struct clk_hw *hw,
617 unsigned long parent_rate)
619 struct samsung_clk_pll *pll = to_clk_pll(hw);
620 u32 mdiv, pdiv, sdiv, pll_con;
621 u64 fvco = parent_rate;
623 pll_con = readl_relaxed(pll->con_reg);
624 mdiv = (pll_con >> PLL45XX_MDIV_SHIFT) & PLL45XX_MDIV_MASK;
625 pdiv = (pll_con >> PLL45XX_PDIV_SHIFT) & PLL45XX_PDIV_MASK;
626 sdiv = (pll_con >> PLL45XX_SDIV_SHIFT) & PLL45XX_SDIV_MASK;
628 if (pll->type == pll_4508)
632 do_div(fvco, (pdiv << sdiv));
634 return (unsigned long)fvco;
637 static bool samsung_pll45xx_mp_change(u32 pll_con0, u32 pll_con1,
638 const struct samsung_pll_rate_table *rate)
640 u32 old_mdiv, old_pdiv, old_afc;
642 old_mdiv = (pll_con0 >> PLL45XX_MDIV_SHIFT) & PLL45XX_MDIV_MASK;
643 old_pdiv = (pll_con0 >> PLL45XX_PDIV_SHIFT) & PLL45XX_PDIV_MASK;
644 old_afc = (pll_con1 >> PLL45XX_AFC_SHIFT) & PLL45XX_AFC_MASK;
646 return (old_mdiv != rate->mdiv || old_pdiv != rate->pdiv
647 || old_afc != rate->afc);
650 static int samsung_pll45xx_set_rate(struct clk_hw *hw, unsigned long drate,
653 struct samsung_clk_pll *pll = to_clk_pll(hw);
654 const struct samsung_pll_rate_table *rate;
657 /* Get required rate settings from table */
658 rate = samsung_get_pll_settings(pll, drate);
660 pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__,
661 drate, clk_hw_get_name(hw));
665 con0 = readl_relaxed(pll->con_reg);
666 con1 = readl_relaxed(pll->con_reg + 0x4);
668 if (!(samsung_pll45xx_mp_change(con0, con1, rate))) {
669 /* If only s change, change just s value only*/
670 con0 &= ~(PLL45XX_SDIV_MASK << PLL45XX_SDIV_SHIFT);
671 con0 |= rate->sdiv << PLL45XX_SDIV_SHIFT;
672 writel_relaxed(con0, pll->con_reg);
677 /* Set PLL PMS values. */
678 con0 &= ~((PLL45XX_MDIV_MASK << PLL45XX_MDIV_SHIFT) |
679 (PLL45XX_PDIV_MASK << PLL45XX_PDIV_SHIFT) |
680 (PLL45XX_SDIV_MASK << PLL45XX_SDIV_SHIFT));
681 con0 |= (rate->mdiv << PLL45XX_MDIV_SHIFT) |
682 (rate->pdiv << PLL45XX_PDIV_SHIFT) |
683 (rate->sdiv << PLL45XX_SDIV_SHIFT);
685 /* Set PLL AFC value. */
686 con1 = readl_relaxed(pll->con_reg + 0x4);
687 con1 &= ~(PLL45XX_AFC_MASK << PLL45XX_AFC_SHIFT);
688 con1 |= (rate->afc << PLL45XX_AFC_SHIFT);
690 /* Set PLL lock time. */
693 writel_relaxed(rate->pdiv * PLL4502_LOCK_FACTOR, pll->lock_reg);
696 writel_relaxed(rate->pdiv * PLL4508_LOCK_FACTOR, pll->lock_reg);
702 /* Set new configuration. */
703 writel_relaxed(con1, pll->con_reg + 0x4);
704 writel_relaxed(con0, pll->con_reg);
706 /* Wait for PLL lock */
707 return samsung_pll_lock_wait(pll, PLL45XX_LOCKED);
710 static const struct clk_ops samsung_pll45xx_clk_ops = {
711 .recalc_rate = samsung_pll45xx_recalc_rate,
712 .round_rate = samsung_pll_round_rate,
713 .set_rate = samsung_pll45xx_set_rate,
716 static const struct clk_ops samsung_pll45xx_clk_min_ops = {
717 .recalc_rate = samsung_pll45xx_recalc_rate,
723 #define PLL46XX_LOCK_FACTOR 3000
725 #define PLL46XX_VSEL_MASK (1)
726 #define PLL46XX_MDIV_MASK (0x1FF)
727 #define PLL1460X_MDIV_MASK (0x3FF)
729 #define PLL46XX_PDIV_MASK (0x3F)
730 #define PLL46XX_SDIV_MASK (0x7)
731 #define PLL46XX_VSEL_SHIFT (27)
732 #define PLL46XX_MDIV_SHIFT (16)
733 #define PLL46XX_PDIV_SHIFT (8)
734 #define PLL46XX_SDIV_SHIFT (0)
736 #define PLL46XX_KDIV_MASK (0xFFFF)
737 #define PLL4650C_KDIV_MASK (0xFFF)
738 #define PLL46XX_KDIV_SHIFT (0)
739 #define PLL46XX_MFR_MASK (0x3F)
740 #define PLL46XX_MRR_MASK (0x1F)
741 #define PLL46XX_KDIV_SHIFT (0)
742 #define PLL46XX_MFR_SHIFT (16)
743 #define PLL46XX_MRR_SHIFT (24)
745 #define PLL46XX_ENABLE BIT(31)
746 #define PLL46XX_LOCKED BIT(29)
747 #define PLL46XX_VSEL BIT(27)
749 static unsigned long samsung_pll46xx_recalc_rate(struct clk_hw *hw,
750 unsigned long parent_rate)
752 struct samsung_clk_pll *pll = to_clk_pll(hw);
753 u32 mdiv, pdiv, sdiv, kdiv, pll_con0, pll_con1, shift;
754 u64 fvco = parent_rate;
756 pll_con0 = readl_relaxed(pll->con_reg);
757 pll_con1 = readl_relaxed(pll->con_reg + 4);
758 mdiv = (pll_con0 >> PLL46XX_MDIV_SHIFT) & ((pll->type == pll_1460x) ?
759 PLL1460X_MDIV_MASK : PLL46XX_MDIV_MASK);
760 pdiv = (pll_con0 >> PLL46XX_PDIV_SHIFT) & PLL46XX_PDIV_MASK;
761 sdiv = (pll_con0 >> PLL46XX_SDIV_SHIFT) & PLL46XX_SDIV_MASK;
762 kdiv = pll->type == pll_4650c ? pll_con1 & PLL4650C_KDIV_MASK :
763 pll_con1 & PLL46XX_KDIV_MASK;
765 shift = ((pll->type == pll_4600) || (pll->type == pll_1460x)) ? 16 : 10;
767 fvco *= (mdiv << shift) + kdiv;
768 do_div(fvco, (pdiv << sdiv));
771 return (unsigned long)fvco;
774 static bool samsung_pll46xx_mpk_change(u32 pll_con0, u32 pll_con1,
775 const struct samsung_pll_rate_table *rate)
777 u32 old_mdiv, old_pdiv, old_kdiv;
779 old_mdiv = (pll_con0 >> PLL46XX_MDIV_SHIFT) & PLL46XX_MDIV_MASK;
780 old_pdiv = (pll_con0 >> PLL46XX_PDIV_SHIFT) & PLL46XX_PDIV_MASK;
781 old_kdiv = (pll_con1 >> PLL46XX_KDIV_SHIFT) & PLL46XX_KDIV_MASK;
783 return (old_mdiv != rate->mdiv || old_pdiv != rate->pdiv
784 || old_kdiv != rate->kdiv);
787 static int samsung_pll46xx_set_rate(struct clk_hw *hw, unsigned long drate,
790 struct samsung_clk_pll *pll = to_clk_pll(hw);
791 const struct samsung_pll_rate_table *rate;
792 u32 con0, con1, lock;
794 /* Get required rate settings from table */
795 rate = samsung_get_pll_settings(pll, drate);
797 pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__,
798 drate, clk_hw_get_name(hw));
802 con0 = readl_relaxed(pll->con_reg);
803 con1 = readl_relaxed(pll->con_reg + 0x4);
805 if (!(samsung_pll46xx_mpk_change(con0, con1, rate))) {
806 /* If only s change, change just s value only*/
807 con0 &= ~(PLL46XX_SDIV_MASK << PLL46XX_SDIV_SHIFT);
808 con0 |= rate->sdiv << PLL46XX_SDIV_SHIFT;
809 writel_relaxed(con0, pll->con_reg);
814 /* Set PLL lock time. */
815 lock = rate->pdiv * PLL46XX_LOCK_FACTOR;
817 /* Maximum lock time bitfield is 16-bit. */
820 /* Set PLL PMS and VSEL values. */
821 if (pll->type == pll_1460x) {
822 con0 &= ~((PLL1460X_MDIV_MASK << PLL46XX_MDIV_SHIFT) |
823 (PLL46XX_PDIV_MASK << PLL46XX_PDIV_SHIFT) |
824 (PLL46XX_SDIV_MASK << PLL46XX_SDIV_SHIFT));
826 con0 &= ~((PLL46XX_MDIV_MASK << PLL46XX_MDIV_SHIFT) |
827 (PLL46XX_PDIV_MASK << PLL46XX_PDIV_SHIFT) |
828 (PLL46XX_SDIV_MASK << PLL46XX_SDIV_SHIFT) |
829 (PLL46XX_VSEL_MASK << PLL46XX_VSEL_SHIFT));
830 con0 |= rate->vsel << PLL46XX_VSEL_SHIFT;
833 con0 |= (rate->mdiv << PLL46XX_MDIV_SHIFT) |
834 (rate->pdiv << PLL46XX_PDIV_SHIFT) |
835 (rate->sdiv << PLL46XX_SDIV_SHIFT);
837 /* Set PLL K, MFR and MRR values. */
838 con1 = readl_relaxed(pll->con_reg + 0x4);
839 con1 &= ~((PLL46XX_KDIV_MASK << PLL46XX_KDIV_SHIFT) |
840 (PLL46XX_MFR_MASK << PLL46XX_MFR_SHIFT) |
841 (PLL46XX_MRR_MASK << PLL46XX_MRR_SHIFT));
842 con1 |= (rate->kdiv << PLL46XX_KDIV_SHIFT) |
843 (rate->mfr << PLL46XX_MFR_SHIFT) |
844 (rate->mrr << PLL46XX_MRR_SHIFT);
846 /* Write configuration to PLL */
847 writel_relaxed(lock, pll->lock_reg);
848 writel_relaxed(con0, pll->con_reg);
849 writel_relaxed(con1, pll->con_reg + 0x4);
851 /* Wait for PLL lock */
852 return samsung_pll_lock_wait(pll, PLL46XX_LOCKED);
855 static const struct clk_ops samsung_pll46xx_clk_ops = {
856 .recalc_rate = samsung_pll46xx_recalc_rate,
857 .round_rate = samsung_pll_round_rate,
858 .set_rate = samsung_pll46xx_set_rate,
861 static const struct clk_ops samsung_pll46xx_clk_min_ops = {
862 .recalc_rate = samsung_pll46xx_recalc_rate,
869 #define PLL6552_MDIV_MASK 0x3ff
870 #define PLL6552_PDIV_MASK 0x3f
871 #define PLL6552_SDIV_MASK 0x7
872 #define PLL6552_MDIV_SHIFT 16
873 #define PLL6552_MDIV_SHIFT_2416 14
874 #define PLL6552_PDIV_SHIFT 8
875 #define PLL6552_PDIV_SHIFT_2416 5
876 #define PLL6552_SDIV_SHIFT 0
878 static unsigned long samsung_pll6552_recalc_rate(struct clk_hw *hw,
879 unsigned long parent_rate)
881 struct samsung_clk_pll *pll = to_clk_pll(hw);
882 u32 mdiv, pdiv, sdiv, pll_con;
883 u64 fvco = parent_rate;
885 pll_con = readl_relaxed(pll->con_reg);
886 if (pll->type == pll_6552_s3c2416) {
887 mdiv = (pll_con >> PLL6552_MDIV_SHIFT_2416) & PLL6552_MDIV_MASK;
888 pdiv = (pll_con >> PLL6552_PDIV_SHIFT_2416) & PLL6552_PDIV_MASK;
890 mdiv = (pll_con >> PLL6552_MDIV_SHIFT) & PLL6552_MDIV_MASK;
891 pdiv = (pll_con >> PLL6552_PDIV_SHIFT) & PLL6552_PDIV_MASK;
893 sdiv = (pll_con >> PLL6552_SDIV_SHIFT) & PLL6552_SDIV_MASK;
896 do_div(fvco, (pdiv << sdiv));
898 return (unsigned long)fvco;
901 static const struct clk_ops samsung_pll6552_clk_ops = {
902 .recalc_rate = samsung_pll6552_recalc_rate,
909 #define PLL6553_MDIV_MASK 0xff
910 #define PLL6553_PDIV_MASK 0x3f
911 #define PLL6553_SDIV_MASK 0x7
912 #define PLL6553_KDIV_MASK 0xffff
913 #define PLL6553_MDIV_SHIFT 16
914 #define PLL6553_PDIV_SHIFT 8
915 #define PLL6553_SDIV_SHIFT 0
916 #define PLL6553_KDIV_SHIFT 0
918 static unsigned long samsung_pll6553_recalc_rate(struct clk_hw *hw,
919 unsigned long parent_rate)
921 struct samsung_clk_pll *pll = to_clk_pll(hw);
922 u32 mdiv, pdiv, sdiv, kdiv, pll_con0, pll_con1;
923 u64 fvco = parent_rate;
925 pll_con0 = readl_relaxed(pll->con_reg);
926 pll_con1 = readl_relaxed(pll->con_reg + 0x4);
927 mdiv = (pll_con0 >> PLL6553_MDIV_SHIFT) & PLL6553_MDIV_MASK;
928 pdiv = (pll_con0 >> PLL6553_PDIV_SHIFT) & PLL6553_PDIV_MASK;
929 sdiv = (pll_con0 >> PLL6553_SDIV_SHIFT) & PLL6553_SDIV_MASK;
930 kdiv = (pll_con1 >> PLL6553_KDIV_SHIFT) & PLL6553_KDIV_MASK;
932 fvco *= (mdiv << 16) + kdiv;
933 do_div(fvco, (pdiv << sdiv));
936 return (unsigned long)fvco;
939 static const struct clk_ops samsung_pll6553_clk_ops = {
940 .recalc_rate = samsung_pll6553_recalc_rate,
944 * PLL2550x Clock Type
947 #define PLL2550X_R_MASK (0x1)
948 #define PLL2550X_P_MASK (0x3F)
949 #define PLL2550X_M_MASK (0x3FF)
950 #define PLL2550X_S_MASK (0x7)
951 #define PLL2550X_R_SHIFT (20)
952 #define PLL2550X_P_SHIFT (14)
953 #define PLL2550X_M_SHIFT (4)
954 #define PLL2550X_S_SHIFT (0)
956 static unsigned long samsung_pll2550x_recalc_rate(struct clk_hw *hw,
957 unsigned long parent_rate)
959 struct samsung_clk_pll *pll = to_clk_pll(hw);
960 u32 r, p, m, s, pll_stat;
961 u64 fvco = parent_rate;
963 pll_stat = readl_relaxed(pll->con_reg);
964 r = (pll_stat >> PLL2550X_R_SHIFT) & PLL2550X_R_MASK;
967 p = (pll_stat >> PLL2550X_P_SHIFT) & PLL2550X_P_MASK;
968 m = (pll_stat >> PLL2550X_M_SHIFT) & PLL2550X_M_MASK;
969 s = (pll_stat >> PLL2550X_S_SHIFT) & PLL2550X_S_MASK;
972 do_div(fvco, (p << s));
974 return (unsigned long)fvco;
977 static const struct clk_ops samsung_pll2550x_clk_ops = {
978 .recalc_rate = samsung_pll2550x_recalc_rate,
982 * PLL2550xx Clock Type
985 /* Maximum lock time can be 270 * PDIV cycles */
986 #define PLL2550XX_LOCK_FACTOR 270
988 #define PLL2550XX_M_MASK 0x3FF
989 #define PLL2550XX_P_MASK 0x3F
990 #define PLL2550XX_S_MASK 0x7
991 #define PLL2550XX_LOCK_STAT_MASK 0x1
992 #define PLL2550XX_M_SHIFT 9
993 #define PLL2550XX_P_SHIFT 3
994 #define PLL2550XX_S_SHIFT 0
995 #define PLL2550XX_LOCK_STAT_SHIFT 21
997 static unsigned long samsung_pll2550xx_recalc_rate(struct clk_hw *hw,
998 unsigned long parent_rate)
1000 struct samsung_clk_pll *pll = to_clk_pll(hw);
1001 u32 mdiv, pdiv, sdiv, pll_con;
1002 u64 fvco = parent_rate;
1004 pll_con = readl_relaxed(pll->con_reg);
1005 mdiv = (pll_con >> PLL2550XX_M_SHIFT) & PLL2550XX_M_MASK;
1006 pdiv = (pll_con >> PLL2550XX_P_SHIFT) & PLL2550XX_P_MASK;
1007 sdiv = (pll_con >> PLL2550XX_S_SHIFT) & PLL2550XX_S_MASK;
1010 do_div(fvco, (pdiv << sdiv));
1012 return (unsigned long)fvco;
1015 static inline bool samsung_pll2550xx_mp_change(u32 mdiv, u32 pdiv, u32 pll_con)
1017 u32 old_mdiv, old_pdiv;
1019 old_mdiv = (pll_con >> PLL2550XX_M_SHIFT) & PLL2550XX_M_MASK;
1020 old_pdiv = (pll_con >> PLL2550XX_P_SHIFT) & PLL2550XX_P_MASK;
1022 return mdiv != old_mdiv || pdiv != old_pdiv;
1025 static int samsung_pll2550xx_set_rate(struct clk_hw *hw, unsigned long drate,
1026 unsigned long prate)
1028 struct samsung_clk_pll *pll = to_clk_pll(hw);
1029 const struct samsung_pll_rate_table *rate;
1032 /* Get required rate settings from table */
1033 rate = samsung_get_pll_settings(pll, drate);
1035 pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__,
1036 drate, clk_hw_get_name(hw));
1040 tmp = readl_relaxed(pll->con_reg);
1042 if (!(samsung_pll2550xx_mp_change(rate->mdiv, rate->pdiv, tmp))) {
1043 /* If only s change, change just s value only*/
1044 tmp &= ~(PLL2550XX_S_MASK << PLL2550XX_S_SHIFT);
1045 tmp |= rate->sdiv << PLL2550XX_S_SHIFT;
1046 writel_relaxed(tmp, pll->con_reg);
1051 /* Set PLL lock time. */
1052 writel_relaxed(rate->pdiv * PLL2550XX_LOCK_FACTOR, pll->lock_reg);
1054 /* Change PLL PMS values */
1055 tmp &= ~((PLL2550XX_M_MASK << PLL2550XX_M_SHIFT) |
1056 (PLL2550XX_P_MASK << PLL2550XX_P_SHIFT) |
1057 (PLL2550XX_S_MASK << PLL2550XX_S_SHIFT));
1058 tmp |= (rate->mdiv << PLL2550XX_M_SHIFT) |
1059 (rate->pdiv << PLL2550XX_P_SHIFT) |
1060 (rate->sdiv << PLL2550XX_S_SHIFT);
1061 writel_relaxed(tmp, pll->con_reg);
1063 /* Wait for PLL lock */
1064 return samsung_pll_lock_wait(pll,
1065 PLL2550XX_LOCK_STAT_MASK << PLL2550XX_LOCK_STAT_SHIFT);
1068 static const struct clk_ops samsung_pll2550xx_clk_ops = {
1069 .recalc_rate = samsung_pll2550xx_recalc_rate,
1070 .round_rate = samsung_pll_round_rate,
1071 .set_rate = samsung_pll2550xx_set_rate,
1074 static const struct clk_ops samsung_pll2550xx_clk_min_ops = {
1075 .recalc_rate = samsung_pll2550xx_recalc_rate,
1079 * PLL2650x Clock Type
1082 /* Maximum lock time can be 3000 * PDIV cycles */
1083 #define PLL2650X_LOCK_FACTOR 3000
1085 #define PLL2650X_M_MASK 0x1ff
1086 #define PLL2650X_P_MASK 0x3f
1087 #define PLL2650X_S_MASK 0x7
1088 #define PLL2650X_K_MASK 0xffff
1089 #define PLL2650X_LOCK_STAT_MASK 0x1
1090 #define PLL2650X_M_SHIFT 16
1091 #define PLL2650X_P_SHIFT 8
1092 #define PLL2650X_S_SHIFT 0
1093 #define PLL2650X_K_SHIFT 0
1094 #define PLL2650X_LOCK_STAT_SHIFT 29
1095 #define PLL2650X_PLL_ENABLE_SHIFT 31
1097 static unsigned long samsung_pll2650x_recalc_rate(struct clk_hw *hw,
1098 unsigned long parent_rate)
1100 struct samsung_clk_pll *pll = to_clk_pll(hw);
1101 u64 fout = parent_rate;
1102 u32 mdiv, pdiv, sdiv, pll_con0, pll_con1;
1105 pll_con0 = readl_relaxed(pll->con_reg);
1106 mdiv = (pll_con0 >> PLL2650X_M_SHIFT) & PLL2650X_M_MASK;
1107 pdiv = (pll_con0 >> PLL2650X_P_SHIFT) & PLL2650X_P_MASK;
1108 sdiv = (pll_con0 >> PLL2650X_S_SHIFT) & PLL2650X_S_MASK;
1110 pll_con1 = readl_relaxed(pll->con_reg + 4);
1111 kdiv = (s16)((pll_con1 >> PLL2650X_K_SHIFT) & PLL2650X_K_MASK);
1113 fout *= (mdiv << 16) + kdiv;
1114 do_div(fout, (pdiv << sdiv));
1117 return (unsigned long)fout;
1120 static int samsung_pll2650x_set_rate(struct clk_hw *hw, unsigned long drate,
1121 unsigned long prate)
1123 struct samsung_clk_pll *pll = to_clk_pll(hw);
1124 const struct samsung_pll_rate_table *rate;
1127 /* Get required rate settings from table */
1128 rate = samsung_get_pll_settings(pll, drate);
1130 pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__,
1131 drate, clk_hw_get_name(hw));
1135 con0 = readl_relaxed(pll->con_reg);
1136 con1 = readl_relaxed(pll->con_reg + 4);
1138 /* Set PLL lock time. */
1139 writel_relaxed(rate->pdiv * PLL2650X_LOCK_FACTOR, pll->lock_reg);
1141 /* Change PLL PMS values */
1142 con0 &= ~((PLL2650X_M_MASK << PLL2650X_M_SHIFT) |
1143 (PLL2650X_P_MASK << PLL2650X_P_SHIFT) |
1144 (PLL2650X_S_MASK << PLL2650X_S_SHIFT));
1145 con0 |= (rate->mdiv << PLL2650X_M_SHIFT) |
1146 (rate->pdiv << PLL2650X_P_SHIFT) |
1147 (rate->sdiv << PLL2650X_S_SHIFT);
1148 con0 |= (1 << PLL2650X_PLL_ENABLE_SHIFT);
1149 writel_relaxed(con0, pll->con_reg);
1151 con1 &= ~(PLL2650X_K_MASK << PLL2650X_K_SHIFT);
1152 con1 |= ((rate->kdiv & PLL2650X_K_MASK) << PLL2650X_K_SHIFT);
1153 writel_relaxed(con1, pll->con_reg + 4);
1155 /* Wait for PLL lock */
1156 return samsung_pll_lock_wait(pll,
1157 PLL2650X_LOCK_STAT_MASK << PLL2650X_LOCK_STAT_SHIFT);
1160 static const struct clk_ops samsung_pll2650x_clk_ops = {
1161 .recalc_rate = samsung_pll2650x_recalc_rate,
1162 .round_rate = samsung_pll_round_rate,
1163 .set_rate = samsung_pll2650x_set_rate,
1166 static const struct clk_ops samsung_pll2650x_clk_min_ops = {
1167 .recalc_rate = samsung_pll2650x_recalc_rate,
1171 * PLL2650XX Clock Type
1174 /* Maximum lock time can be 3000 * PDIV cycles */
1175 #define PLL2650XX_LOCK_FACTOR 3000
1177 #define PLL2650XX_MDIV_SHIFT 9
1178 #define PLL2650XX_PDIV_SHIFT 3
1179 #define PLL2650XX_SDIV_SHIFT 0
1180 #define PLL2650XX_KDIV_SHIFT 0
1181 #define PLL2650XX_MDIV_MASK 0x1ff
1182 #define PLL2650XX_PDIV_MASK 0x3f
1183 #define PLL2650XX_SDIV_MASK 0x7
1184 #define PLL2650XX_KDIV_MASK 0xffff
1185 #define PLL2650XX_PLL_ENABLE_SHIFT 23
1186 #define PLL2650XX_PLL_LOCKTIME_SHIFT 21
1187 #define PLL2650XX_PLL_FOUTMASK_SHIFT 31
1189 static unsigned long samsung_pll2650xx_recalc_rate(struct clk_hw *hw,
1190 unsigned long parent_rate)
1192 struct samsung_clk_pll *pll = to_clk_pll(hw);
1193 u32 mdiv, pdiv, sdiv, pll_con0, pll_con2;
1195 u64 fvco = parent_rate;
1197 pll_con0 = readl_relaxed(pll->con_reg);
1198 pll_con2 = readl_relaxed(pll->con_reg + 8);
1199 mdiv = (pll_con0 >> PLL2650XX_MDIV_SHIFT) & PLL2650XX_MDIV_MASK;
1200 pdiv = (pll_con0 >> PLL2650XX_PDIV_SHIFT) & PLL2650XX_PDIV_MASK;
1201 sdiv = (pll_con0 >> PLL2650XX_SDIV_SHIFT) & PLL2650XX_SDIV_MASK;
1202 kdiv = (s16)(pll_con2 & PLL2650XX_KDIV_MASK);
1204 fvco *= (mdiv << 16) + kdiv;
1205 do_div(fvco, (pdiv << sdiv));
1208 return (unsigned long)fvco;
1211 static int samsung_pll2650xx_set_rate(struct clk_hw *hw, unsigned long drate,
1212 unsigned long parent_rate)
1214 struct samsung_clk_pll *pll = to_clk_pll(hw);
1215 u32 pll_con0, pll_con2;
1216 const struct samsung_pll_rate_table *rate;
1218 rate = samsung_get_pll_settings(pll, drate);
1220 pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__,
1221 drate, clk_hw_get_name(hw));
1225 pll_con0 = readl_relaxed(pll->con_reg);
1226 pll_con2 = readl_relaxed(pll->con_reg + 8);
1228 /* Change PLL PMS values */
1229 pll_con0 &= ~(PLL2650XX_MDIV_MASK << PLL2650XX_MDIV_SHIFT |
1230 PLL2650XX_PDIV_MASK << PLL2650XX_PDIV_SHIFT |
1231 PLL2650XX_SDIV_MASK << PLL2650XX_SDIV_SHIFT);
1232 pll_con0 |= rate->mdiv << PLL2650XX_MDIV_SHIFT;
1233 pll_con0 |= rate->pdiv << PLL2650XX_PDIV_SHIFT;
1234 pll_con0 |= rate->sdiv << PLL2650XX_SDIV_SHIFT;
1235 pll_con0 |= 1 << PLL2650XX_PLL_ENABLE_SHIFT;
1236 pll_con0 |= 1 << PLL2650XX_PLL_FOUTMASK_SHIFT;
1238 pll_con2 &= ~(PLL2650XX_KDIV_MASK << PLL2650XX_KDIV_SHIFT);
1239 pll_con2 |= ((~(rate->kdiv) + 1) & PLL2650XX_KDIV_MASK)
1240 << PLL2650XX_KDIV_SHIFT;
1242 /* Set PLL lock time. */
1243 writel_relaxed(PLL2650XX_LOCK_FACTOR * rate->pdiv, pll->lock_reg);
1245 writel_relaxed(pll_con0, pll->con_reg);
1246 writel_relaxed(pll_con2, pll->con_reg + 8);
1248 return samsung_pll_lock_wait(pll, 0x1 << PLL2650XX_PLL_LOCKTIME_SHIFT);
1251 static const struct clk_ops samsung_pll2650xx_clk_ops = {
1252 .recalc_rate = samsung_pll2650xx_recalc_rate,
1253 .set_rate = samsung_pll2650xx_set_rate,
1254 .round_rate = samsung_pll_round_rate,
1257 static const struct clk_ops samsung_pll2650xx_clk_min_ops = {
1258 .recalc_rate = samsung_pll2650xx_recalc_rate,
1261 static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx,
1262 const struct samsung_pll_clock *pll_clk)
1264 struct samsung_clk_pll *pll;
1265 struct clk_init_data init;
1268 pll = kzalloc(sizeof(*pll), GFP_KERNEL);
1270 pr_err("%s: could not allocate pll clk %s\n",
1271 __func__, pll_clk->name);
1275 init.name = pll_clk->name;
1276 init.flags = pll_clk->flags;
1277 init.parent_names = &pll_clk->parent_name;
1278 init.num_parents = 1;
1280 if (pll_clk->rate_table) {
1281 /* find count of rates in rate_table */
1282 for (len = 0; pll_clk->rate_table[len].rate != 0; )
1285 pll->rate_count = len;
1286 pll->rate_table = kmemdup(pll_clk->rate_table,
1288 sizeof(struct samsung_pll_rate_table),
1290 WARN(!pll->rate_table,
1291 "%s: could not allocate rate table for %s\n",
1292 __func__, pll_clk->name);
1295 switch (pll_clk->type) {
1297 init.ops = &samsung_pll2126_clk_ops;
1300 init.ops = &samsung_pll3000_clk_ops;
1302 /* clk_ops for 35xx and 2550 are similar */
1309 pll->enable_offs = PLL35XX_ENABLE_SHIFT;
1310 pll->lock_offs = PLL35XX_LOCK_STAT_SHIFT;
1311 if (!pll->rate_table)
1312 init.ops = &samsung_pll35xx_clk_min_ops;
1314 init.ops = &samsung_pll35xx_clk_ops;
1319 pll->enable_offs = PLL0822X_ENABLE_SHIFT;
1320 pll->lock_offs = PLL0822X_LOCK_STAT_SHIFT;
1321 if (!pll->rate_table)
1322 init.ops = &samsung_pll0822x_clk_min_ops;
1324 init.ops = &samsung_pll0822x_clk_ops;
1327 init.ops = &samsung_pll45xx_clk_min_ops;
1331 if (!pll->rate_table)
1332 init.ops = &samsung_pll45xx_clk_min_ops;
1334 init.ops = &samsung_pll45xx_clk_ops;
1336 /* clk_ops for 36xx and 2650 are similar */
1339 pll->enable_offs = PLL36XX_ENABLE_SHIFT;
1340 pll->lock_offs = PLL36XX_LOCK_STAT_SHIFT;
1341 if (!pll->rate_table)
1342 init.ops = &samsung_pll36xx_clk_min_ops;
1344 init.ops = &samsung_pll36xx_clk_ops;
1347 pll->enable_offs = PLL0831X_ENABLE_SHIFT;
1348 pll->lock_offs = PLL0831X_LOCK_STAT_SHIFT;
1349 if (!pll->rate_table)
1350 init.ops = &samsung_pll0831x_clk_min_ops;
1352 init.ops = &samsung_pll0831x_clk_ops;
1355 case pll_6552_s3c2416:
1356 init.ops = &samsung_pll6552_clk_ops;
1359 init.ops = &samsung_pll6553_clk_ops;
1365 if (!pll->rate_table)
1366 init.ops = &samsung_pll46xx_clk_min_ops;
1368 init.ops = &samsung_pll46xx_clk_ops;
1371 init.ops = &samsung_pll2550x_clk_ops;
1374 if (!pll->rate_table)
1375 init.ops = &samsung_pll2550xx_clk_min_ops;
1377 init.ops = &samsung_pll2550xx_clk_ops;
1380 if (!pll->rate_table)
1381 init.ops = &samsung_pll2650x_clk_min_ops;
1383 init.ops = &samsung_pll2650x_clk_ops;
1386 if (!pll->rate_table)
1387 init.ops = &samsung_pll2650xx_clk_min_ops;
1389 init.ops = &samsung_pll2650xx_clk_ops;
1392 pr_warn("%s: Unknown pll type for pll clk %s\n",
1393 __func__, pll_clk->name);
1396 pll->hw.init = &init;
1397 pll->type = pll_clk->type;
1398 pll->lock_reg = ctx->reg_base + pll_clk->lock_offset;
1399 pll->con_reg = ctx->reg_base + pll_clk->con_offset;
1401 ret = clk_hw_register(ctx->dev, &pll->hw);
1403 pr_err("%s: failed to register pll clock %s : %d\n",
1404 __func__, pll_clk->name, ret);
1405 kfree(pll->rate_table);
1410 samsung_clk_add_lookup(ctx, &pll->hw, pll_clk->id);
1413 void __init samsung_clk_register_pll(struct samsung_clk_provider *ctx,
1414 const struct samsung_pll_clock *pll_list,
1415 unsigned int nr_pll)
1419 for (cnt = 0; cnt < nr_pll; cnt++)
1420 _samsung_clk_register_pll(ctx, &pll_list[cnt]);