drivers/clk/samsung/clk-exynos5433.c

   1 /*
   2  * Copyright (c) 2014 Samsung Electronics Co., Ltd.
   3  * Author: Chanwoo Choi <cw00.choi@samsung.com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License version 2 as
   7  * published by the Free Software Foundation.
   8  *
   9  * Common Clock Framework support for Exynos5443 SoC.
  10  */
  11
  12 #include <linux/clk.h>
  13 #include <linux/clkdev.h>
  14 #include <linux/clk-provider.h>
  15 #include <linux/of.h>
  16 #include <linux/of_address.h>
  17 #include <linux/soc/samsung/pm_domain.h>
  18
  19 #include <dt-bindings/clock/exynos5433.h>
  20
  21 #include "clk.h"
  22 #include "clk-pll.h"
  23
  24 struct exynos5433_cmu_pd_handler {
  25         struct list_head entry;
  26         struct notifier_block nb;
  27         struct of_phandle_args pd_args;
  28         struct samsung_clock_reg_cache *regcache;
  29         struct clk **reqd_clks;
  30         unsigned int nr_reqd_clks;
  31 } typedef CMU_PD_H;
  32
  33 static int exynos5433_cmu_pd_notifier(struct notifier_block *nb, unsigned long val,
  34                                         void *data)
  35 {
  36         CMU_PD_H *handler = container_of(nb, CMU_PD_H, nb);
  37         struct samsung_clock_reg_cache *regcache = handler->regcache;
  38         int i;
  39
  40         switch (val) {
  41         case EXYNOS_PD_ADD:
  42                 if ((struct generic_pm_domain *)data ==
  43                         of_genpd_get_from_provider(&handler->pd_args)) {
  44                         exynos_pd_notifier_unregister(NULL, nb);
  45                         exynos_pd_notifier_register(data, nb);
  46                 }
  47                 break;
  48         case EXYNOS_PD_PRE_ON:
  49                 if (handler->nr_reqd_clks)
  50                         for (i = 0; i < handler->nr_reqd_clks; i++)
  51                                 clk_prepare_enable(handler->reqd_clks[i]);
  52                 break;
  53         case EXYNOS_PD_POST_ON:
  54                 if (regcache)
  55                         samsung_clk_restore(regcache->reg_base, regcache->rdump,
  56                                         regcache->rd_num);
  57                 if (handler->nr_reqd_clks)
  58                         for (i = 0; i < handler->nr_reqd_clks; i++)
  59                                 clk_disable_unprepare(handler->reqd_clks[i]);
  60                 break;
  61         case EXYNOS_PD_PRE_OFF:
  62                 if (handler->nr_reqd_clks)
  63                         for (i = 0; i < handler->nr_reqd_clks; i++)
  64                                 clk_prepare_enable(handler->reqd_clks[i]);
  65                 if (regcache)
  66                         samsung_clk_save(regcache->reg_base, regcache->rdump,
  67                                 regcache->rd_num);
  68                 break;
  69         case EXYNOS_PD_POST_OFF:
  70                 if (handler->nr_reqd_clks)
  71                         for (i = 0; i < handler->nr_reqd_clks; i++)
  72                                 clk_disable_unprepare(handler->reqd_clks[i]);
  73                 break;
  74         }
  75
  76         return NOTIFY_OK;
  77 }
  78
  79 static void __init exynos5433_cmu_pd_handler_init(struct device_node *np,
  80                                         unsigned long *regs, int nr_regs)
  81 {
  82         CMU_PD_H *handler;
  83         struct generic_pm_domain *domain;
  84         int ret, nr_clks;
  85
  86         handler = kzalloc(sizeof(*handler), GFP_KERNEL);
  87         if (!handler)
  88                 return;
  89
  90         ret = of_parse_phandle_with_args(np, "power-domains",
  91                                         "#power-domain-cells", 0,
  92                                         &handler->pd_args);
  93         if (ret < 0)
  94                 goto err;
  95
  96         domain = of_genpd_get_from_provider(&handler->pd_args);
  97
  98         handler->nb.notifier_call = exynos5433_cmu_pd_notifier;
  99
 100         if (nr_regs) {
 101                 struct samsung_clock_reg_cache *regcache;
 102
 103                 regcache = kzalloc(sizeof(*regcache), GFP_KERNEL);
 104                 if (!regcache)
 105                         goto err;
 106
 107                 regcache->reg_base = of_iomap(np, 0);
 108                 regcache->rdump = samsung_clk_alloc_reg_dump(regs, nr_regs);
 109                 regcache->rd_num = nr_regs;
 110                 handler->regcache = regcache;
 111         }
 112
 113         nr_clks = of_count_phandle_with_args(np, "clocks","#clock-cells");
 114         if (nr_clks > 0) {
 115                 struct clk *clk;
 116                 int i;
 117
 118                 handler->reqd_clks = kcalloc(sizeof(struct clk *),
 119                                                 nr_clks, GFP_KERNEL);
 120
 121                 for (i = 0; i < nr_clks; i++) {
 122                         clk = of_clk_get(np, i);
 123                         if (IS_ERR(clk))
 124                                 goto err;
 125
 126                         handler->reqd_clks[i] = clk;
 127                 }
 128
 129                 handler->nr_reqd_clks = nr_clks;
 130         }
 131
 132         if (IS_ERR(domain))
 133                 exynos_pd_notifier_register(NULL, &handler->nb);
 134         else
 135                 exynos_pd_notifier_register(domain, &handler->nb);
 136
 137         return;
 138 err:
 139         kfree(handler);
 140         return;
 141 }
 142
 143 /*
 144  * Register offset definitions for CMU_TOP
 145  */
 146 #define ISP_PLL_LOCK                    0x0000
 147 #define AUD_PLL_LOCK                    0x0004
 148 #define ISP_PLL_CON0                    0x0100
 149 #define ISP_PLL_CON1                    0x0104
 150 #define ISP_PLL_FREQ_DET                0x0108
 151 #define AUD_PLL_CON0                    0x0110
 152 #define AUD_PLL_CON1                    0x0114
 153 #define AUD_PLL_CON2                    0x0118
 154 #define AUD_PLL_FREQ_DET                0x011c
 155 #define MUX_SEL_TOP0                    0x0200
 156 #define MUX_SEL_TOP1                    0x0204
 157 #define MUX_SEL_TOP2                    0x0208
 158 #define MUX_SEL_TOP3                    0x020c
 159 #define MUX_SEL_TOP4                    0x0210
 160 #define MUX_SEL_TOP_MSCL                0x0220
 161 #define MUX_SEL_TOP_CAM1                0x0224
 162 #define MUX_SEL_TOP_DISP                0x0228
 163 #define MUX_SEL_TOP_FSYS0               0x0230
 164 #define MUX_SEL_TOP_FSYS1               0x0234
 165 #define MUX_SEL_TOP_PERIC0              0x0238
 166 #define MUX_SEL_TOP_PERIC1              0x023c
 167 #define MUX_ENABLE_TOP0                 0x0300
 168 #define MUX_ENABLE_TOP1                 0x0304
 169 #define MUX_ENABLE_TOP2                 0x0308
 170 #define MUX_ENABLE_TOP3                 0x030c
 171 #define MUX_ENABLE_TOP4                 0x0310
 172 #define MUX_ENABLE_TOP_MSCL             0x0320
 173 #define MUX_ENABLE_TOP_CAM1             0x0324
 174 #define MUX_ENABLE_TOP_DISP             0x0328
 175 #define MUX_ENABLE_TOP_FSYS0            0x0330
 176 #define MUX_ENABLE_TOP_FSYS1            0x0334
 177 #define MUX_ENABLE_TOP_PERIC0           0x0338
 178 #define MUX_ENABLE_TOP_PERIC1           0x033c
 179 #define MUX_STAT_TOP0                   0x0400
 180 #define MUX_STAT_TOP1                   0x0404
 181 #define MUX_STAT_TOP2                   0x0408
 182 #define MUX_STAT_TOP3                   0x040c
 183 #define MUX_STAT_TOP4                   0x0410
 184 #define MUX_STAT_TOP_MSCL               0x0420
 185 #define MUX_STAT_TOP_CAM1               0x0424
 186 #define MUX_STAT_TOP_FSYS0              0x0430
 187 #define MUX_STAT_TOP_FSYS1              0x0434
 188 #define MUX_STAT_TOP_PERIC0             0x0438
 189 #define MUX_STAT_TOP_PERIC1             0x043c
 190 #define DIV_TOP0                        0x0600
 191 #define DIV_TOP1                        0x0604
 192 #define DIV_TOP2                        0x0608
 193 #define DIV_TOP3                        0x060c
 194 #define DIV_TOP4                        0x0610
 195 #define DIV_TOP_MSCL                    0x0618
 196 #define DIV_TOP_CAM10                   0x061c
 197 #define DIV_TOP_CAM11                   0x0620
 198 #define DIV_TOP_FSYS0                   0x062c
 199 #define DIV_TOP_FSYS1                   0x0630
 200 #define DIV_TOP_FSYS2                   0x0634
 201 #define DIV_TOP_PERIC0                  0x0638
 202 #define DIV_TOP_PERIC1                  0x063c
 203 #define DIV_TOP_PERIC2                  0x0640
 204 #define DIV_TOP_PERIC3                  0x0644
 205 #define DIV_TOP_PERIC4                  0x0648
 206 #define DIV_TOP_PLL_FREQ_DET            0x064c
 207 #define DIV_STAT_TOP0                   0x0700
 208 #define DIV_STAT_TOP1                   0x0704
 209 #define DIV_STAT_TOP2                   0x0708
 210 #define DIV_STAT_TOP3                   0x070c
 211 #define DIV_STAT_TOP4                   0x0710
 212 #define DIV_STAT_TOP_MSCL               0x0718
 213 #define DIV_STAT_TOP_CAM10              0x071c
 214 #define DIV_STAT_TOP_CAM11              0x0720
 215 #define DIV_STAT_TOP_FSYS0              0x072c
 216 #define DIV_STAT_TOP_FSYS1              0x0730
 217 #define DIV_STAT_TOP_FSYS2              0x0734
 218 #define DIV_STAT_TOP_PERIC0             0x0738
 219 #define DIV_STAT_TOP_PERIC1             0x073c
 220 #define DIV_STAT_TOP_PERIC2             0x0740
 221 #define DIV_STAT_TOP_PERIC3             0x0744
 222 #define DIV_STAT_TOP_PLL_FREQ_DET       0x074c
 223 #define ENABLE_ACLK_TOP                 0x0800
 224 #define ENABLE_SCLK_TOP                 0x0a00
 225 #define ENABLE_SCLK_TOP_MSCL            0x0a04
 226 #define ENABLE_SCLK_TOP_CAM1            0x0a08
 227 #define ENABLE_SCLK_TOP_DISP            0x0a0c
 228 #define ENABLE_SCLK_TOP_FSYS            0x0a10
 229 #define ENABLE_SCLK_TOP_PERIC           0x0a14
 230 #define ENABLE_IP_TOP                   0x0b00
 231 #define ENABLE_CMU_TOP                  0x0c00
 232 #define ENABLE_CMU_TOP_DIV_STAT         0x0c04
 233
 234 static unsigned long top_clk_regs[] __initdata = {
 235         ISP_PLL_LOCK,
 236         AUD_PLL_LOCK,
 237         ISP_PLL_CON0,
 238         ISP_PLL_CON1,
 239         ISP_PLL_FREQ_DET,
 240         AUD_PLL_CON0,
 241         AUD_PLL_CON1,
 242         AUD_PLL_CON2,
 243         AUD_PLL_FREQ_DET,
 244         MUX_SEL_TOP0,
 245         MUX_SEL_TOP1,
 246         MUX_SEL_TOP2,
 247         MUX_SEL_TOP3,
 248         MUX_SEL_TOP4,
 249         MUX_SEL_TOP_MSCL,
 250         MUX_SEL_TOP_CAM1,
 251         MUX_SEL_TOP_DISP,
 252         MUX_SEL_TOP_FSYS0,
 253         MUX_SEL_TOP_FSYS1,
 254         MUX_SEL_TOP_PERIC0,
 255         MUX_SEL_TOP_PERIC1,
 256         MUX_ENABLE_TOP0,
 257         MUX_ENABLE_TOP1,
 258         MUX_ENABLE_TOP2,
 259         MUX_ENABLE_TOP3,
 260         MUX_ENABLE_TOP4,
 261         MUX_ENABLE_TOP_MSCL,
 262         MUX_ENABLE_TOP_CAM1,
 263         MUX_ENABLE_TOP_DISP,
 264         MUX_ENABLE_TOP_FSYS0,
 265         MUX_ENABLE_TOP_FSYS1,
 266         MUX_ENABLE_TOP_PERIC0,
 267         MUX_ENABLE_TOP_PERIC1,
 268         DIV_TOP0,
 269         DIV_TOP1,
 270         DIV_TOP2,
 271         DIV_TOP3,
 272         DIV_TOP4,
 273         DIV_TOP_MSCL,
 274         DIV_TOP_CAM10,
 275         DIV_TOP_CAM11,
 276         DIV_TOP_FSYS0,
 277         DIV_TOP_FSYS1,
 278         DIV_TOP_FSYS2,
 279         DIV_TOP_PERIC0,
 280         DIV_TOP_PERIC1,
 281         DIV_TOP_PERIC2,
 282         DIV_TOP_PERIC3,
 283         DIV_TOP_PERIC4,
 284         DIV_TOP_PLL_FREQ_DET,
 285         ENABLE_ACLK_TOP,
 286         ENABLE_SCLK_TOP,
 287         ENABLE_SCLK_TOP_MSCL,
 288         ENABLE_SCLK_TOP_CAM1,
 289         ENABLE_SCLK_TOP_DISP,
 290         ENABLE_SCLK_TOP_FSYS,
 291         ENABLE_SCLK_TOP_PERIC,
 292         ENABLE_IP_TOP,
 293         ENABLE_CMU_TOP,
 294         ENABLE_CMU_TOP_DIV_STAT,
 295 };
 296
 297 /* list of all parent clock list */
 298 PNAME(mout_aud_pll_p)           = { "oscclk", "fout_aud_pll", };
 299 PNAME(mout_isp_pll_p)           = { "oscclk", "fout_isp_pll", };
 300 PNAME(mout_aud_pll_user_p)      = { "oscclk", "mout_aud_pll", };
 301 PNAME(mout_mphy_pll_user_p)     = { "oscclk", "sclk_mphy_pll", };
 302 PNAME(mout_mfc_pll_user_p)      = { "oscclk", "sclk_mfc_pll", };
 303 PNAME(mout_bus_pll_user_p)      = { "oscclk", "sclk_bus_pll", };
 304 PNAME(mout_bus_pll_user_t_p)    = { "oscclk", "mout_bus_pll_user", };
 305 PNAME(mout_mphy_pll_user_t_p)   = { "oscclk", "mout_mphy_pll_user", };
 306
 307 PNAME(mout_bus_mfc_pll_user_p)  = { "mout_bus_pll_user", "mout_mfc_pll_user",};
 308 PNAME(mout_mfc_bus_pll_user_p)  = { "mout_mfc_pll_user", "mout_bus_pll_user",};
 309 PNAME(mout_aclk_cam1_552_b_p)   = { "mout_aclk_cam1_552_a",
 310                                     "mout_mfc_pll_user", };
 311 PNAME(mout_aclk_cam1_552_a_p)   = { "mout_isp_pll", "mout_bus_pll_user", };
 312
 313 PNAME(mout_aclk_mfc_400_c_p)    = { "mout_aclk_mfc_400_b",
 314                                     "mout_mphy_pll_user", };
 315 PNAME(mout_aclk_mfc_400_b_p)    = { "mout_aclk_mfc_400_a",
 316                                     "mout_bus_pll_user", };
 317 PNAME(mout_aclk_mfc_400_a_p)    = { "mout_mfc_pll_user", "mout_isp_pll", };
 318
 319 PNAME(mout_bus_mphy_pll_user_p) = { "mout_bus_pll_user",
 320                                     "mout_mphy_pll_user", };
 321 PNAME(mout_aclk_mscl_b_p)       = { "mout_aclk_mscl_400_a",
 322                                     "mout_mphy_pll_user", };
 323 PNAME(mout_aclk_g2d_400_b_p)    = { "mout_aclk_g2d_400_a",
 324                                     "mout_mphy_pll_user", };
 325
 326 PNAME(mout_sclk_jpeg_c_p)       = { "mout_sclk_jpeg_b", "mout_mphy_pll_user",};
 327 PNAME(mout_sclk_jpeg_b_p)       = { "mout_sclk_jpeg_a", "mout_mfc_pll_user", };
 328
 329 PNAME(mout_sclk_mmc2_b_p)       = { "mout_sclk_mmc2_a", "mout_mfc_pll_user",};
 330 PNAME(mout_sclk_mmc1_b_p)       = { "mout_sclk_mmc1_a", "mout_mfc_pll_user",};
 331 PNAME(mout_sclk_mmc0_d_p)       = { "mout_sclk_mmc0_c", "mout_isp_pll", };
 332 PNAME(mout_sclk_mmc0_c_p)       = { "mout_sclk_mmc0_b", "mout_mphy_pll_user",};
 333 PNAME(mout_sclk_mmc0_b_p)       = { "mout_sclk_mmc0_a", "mout_mfc_pll_user", };
 334
 335 PNAME(mout_sclk_spdif_p)        = { "sclk_audio0", "sclk_audio1",
 336                                     "oscclk", "ioclk_spdif_extclk", };
 337 PNAME(mout_sclk_audio1_p)       = { "ioclk_audiocdclk1", "oscclk",
 338                                     "mout_aud_pll_user_t",};
 339 PNAME(mout_sclk_audio0_p)       = { "ioclk_audiocdclk0", "oscclk",
 340                                     "mout_aud_pll_user_t",};
 341
 342 PNAME(mout_sclk_hdmi_spdif_p)   = { "sclk_audio1", "ioclk_spdif_extclk", };
 343
 344 static struct samsung_fixed_factor_clock top_fixed_factor_clks[] __initdata = {
 345         FFACTOR(0, "oscclk_efuse_common", "oscclk", 1, 1, 0),
 346 };
 347
 348 static struct samsung_fixed_rate_clock top_fixed_clks[] __initdata = {
 349         /* Xi2s{0|1}CDCLK input clock for I2S/PCM */
 350         FRATE(0, "ioclk_audiocdclk1", NULL, CLK_IS_ROOT, 100000000),
 351         FRATE(0, "ioclk_audiocdclk0", NULL, CLK_IS_ROOT, 100000000),
 352         /* Xi2s1SDI input clock for SPDIF */
 353         FRATE(0, "ioclk_spdif_extclk", NULL, CLK_IS_ROOT, 100000000),
 354         /* XspiCLK[4:0] input clock for SPI */
 355         FRATE(0, "ioclk_spi4_clk_in", NULL, CLK_IS_ROOT, 50000000),
 356         FRATE(0, "ioclk_spi3_clk_in", NULL, CLK_IS_ROOT, 50000000),
 357         FRATE(0, "ioclk_spi2_clk_in", NULL, CLK_IS_ROOT, 50000000),
 358         FRATE(0, "ioclk_spi1_clk_in", NULL, CLK_IS_ROOT, 50000000),
 359         FRATE(0, "ioclk_spi0_clk_in", NULL, CLK_IS_ROOT, 50000000),
 360         /* Xi2s1SCLK input clock for I2S1_BCLK */
 361         FRATE(0, "ioclk_i2s1_bclk_in", NULL, CLK_IS_ROOT, 12288000),
 362 };
 363
 364 static struct samsung_mux_clock top_mux_clks[] __initdata = {
 365         /* MUX_SEL_TOP0 */
 366         MUX(CLK_MOUT_AUD_PLL, "mout_aud_pll", mout_aud_pll_p, MUX_SEL_TOP0,
 367                         4, 1),
 368         MUX(CLK_MOUT_ISP_PLL, "mout_isp_pll", mout_isp_pll_p, MUX_SEL_TOP0,
 369                         0, 1),
 370
 371         /* MUX_SEL_TOP1 */
 372         MUX(CLK_MOUT_AUD_PLL_USER_T, "mout_aud_pll_user_t",
 373                         mout_aud_pll_user_p, MUX_SEL_TOP1, 12, 1),
 374         MUX(CLK_MOUT_MPHY_PLL_USER, "mout_mphy_pll_user", mout_mphy_pll_user_p,
 375                         MUX_SEL_TOP1, 8, 1),
 376         MUX(CLK_MOUT_MFC_PLL_USER, "mout_mfc_pll_user", mout_mfc_pll_user_p,
 377                         MUX_SEL_TOP1, 4, 1),
 378         MUX(CLK_MOUT_BUS_PLL_USER, "mout_bus_pll_user", mout_bus_pll_user_p,
 379                         MUX_SEL_TOP1, 0, 1),
 380
 381         /* MUX_SEL_TOP2 */
 382         MUX(CLK_MOUT_ACLK_HEVC_400, "mout_aclk_hevc_400",
 383                         mout_bus_mfc_pll_user_p, MUX_SEL_TOP2, 28, 1),
 384         MUX(CLK_MOUT_ACLK_CAM1_333, "mout_aclk_cam1_333",
 385                         mout_mfc_bus_pll_user_p, MUX_SEL_TOP2, 16, 1),
 386         MUX(CLK_MOUT_ACLK_CAM1_552_B, "mout_aclk_cam1_552_b",
 387                         mout_aclk_cam1_552_b_p, MUX_SEL_TOP2, 12, 1),
 388         MUX(CLK_MOUT_ACLK_CAM1_552_A, "mout_aclk_cam1_552_a",
 389                         mout_aclk_cam1_552_a_p, MUX_SEL_TOP2, 8, 1),
 390         MUX(CLK_MOUT_ACLK_ISP_DIS_400, "mout_aclk_isp_dis_400",
 391                         mout_bus_mfc_pll_user_p, MUX_SEL_TOP2, 4, 1),
 392         MUX(CLK_MOUT_ACLK_ISP_400, "mout_aclk_isp_400",
 393                         mout_bus_mfc_pll_user_p, MUX_SEL_TOP2, 0, 1),
 394
 395         /* MUX_SEL_TOP3 */
 396         MUX(CLK_MOUT_ACLK_BUS0_400, "mout_aclk_bus0_400",
 397                         mout_bus_mphy_pll_user_p, MUX_SEL_TOP3, 20, 1),
 398         MUX(CLK_MOUT_ACLK_MSCL_400_B, "mout_aclk_mscl_400_b",
 399                         mout_aclk_mscl_b_p, MUX_SEL_TOP3, 16, 1),
 400         MUX(CLK_MOUT_ACLK_MSCL_400_A, "mout_aclk_mscl_400_a",
 401                         mout_bus_mfc_pll_user_p, MUX_SEL_TOP3, 12, 1),
 402         MUX(CLK_MOUT_ACLK_GSCL_333, "mout_aclk_gscl_333",
 403                         mout_mfc_bus_pll_user_p, MUX_SEL_TOP3, 8, 1),
 404         MUX(CLK_MOUT_ACLK_G2D_400_B, "mout_aclk_g2d_400_b",
 405                         mout_aclk_g2d_400_b_p, MUX_SEL_TOP3, 4, 1),
 406         MUX(CLK_MOUT_ACLK_G2D_400_A, "mout_aclk_g2d_400_a",
 407                         mout_bus_mfc_pll_user_p, MUX_SEL_TOP3, 0, 1),
 408
 409         /* MUX_SEL_TOP4 */
 410         MUX(CLK_MOUT_ACLK_MFC_400_C, "mout_aclk_mfc_400_c",
 411                         mout_aclk_mfc_400_c_p, MUX_SEL_TOP4, 8, 1),
 412         MUX(CLK_MOUT_ACLK_MFC_400_B, "mout_aclk_mfc_400_b",
 413                         mout_aclk_mfc_400_b_p, MUX_SEL_TOP4, 4, 1),
 414         MUX(CLK_MOUT_ACLK_MFC_400_A, "mout_aclk_mfc_400_a",
 415                         mout_aclk_mfc_400_a_p, MUX_SEL_TOP4, 0, 1),
 416
 417         /* MUX_SEL_TOP_MSCL */
 418         MUX(CLK_MOUT_SCLK_JPEG_C, "mout_sclk_jpeg_c", mout_sclk_jpeg_c_p,
 419                         MUX_SEL_TOP_MSCL, 8, 1),
 420         MUX(CLK_MOUT_SCLK_JPEG_B, "mout_sclk_jpeg_b", mout_sclk_jpeg_b_p,
 421                         MUX_SEL_TOP_MSCL, 4, 1),
 422         MUX(CLK_MOUT_SCLK_JPEG_A, "mout_sclk_jpeg_a", mout_bus_pll_user_t_p,
 423                         MUX_SEL_TOP_MSCL, 0, 1),
 424
 425         /* MUX_SEL_TOP_CAM1 */
 426         MUX(CLK_MOUT_SCLK_ISP_SENSOR2, "mout_sclk_isp_sensor2",
 427                         mout_bus_pll_user_t_p, MUX_SEL_TOP_CAM1, 24, 1),
 428         MUX(CLK_MOUT_SCLK_ISP_SENSOR1, "mout_sclk_isp_sensor1",
 429                         mout_bus_pll_user_t_p, MUX_SEL_TOP_CAM1, 20, 1),
 430         MUX(CLK_MOUT_SCLK_ISP_SENSOR0, "mout_sclk_isp_sensor0",
 431                         mout_bus_pll_user_t_p, MUX_SEL_TOP_CAM1, 16, 1),
 432         MUX(CLK_MOUT_SCLK_ISP_UART, "mout_sclk_isp_uart",
 433                         mout_bus_pll_user_t_p, MUX_SEL_TOP_CAM1, 8, 1),
 434         MUX(CLK_MOUT_SCLK_ISP_SPI1, "mout_sclk_isp_spi1",
 435                         mout_bus_pll_user_t_p, MUX_SEL_TOP_CAM1, 4, 1),
 436         MUX(CLK_MOUT_SCLK_ISP_SPI0, "mout_sclk_isp_spi0",
 437                         mout_bus_pll_user_t_p, MUX_SEL_TOP_CAM1, 0, 1),
 438
 439         /* MUX_SEL_TOP_FSYS0 */
 440         MUX(CLK_MOUT_SCLK_MMC2_B, "mout_sclk_mmc2_b", mout_sclk_mmc2_b_p,
 441                         MUX_SEL_TOP_FSYS0, 28, 1),
 442         MUX(CLK_MOUT_SCLK_MMC2_A, "mout_sclk_mmc2_a", mout_bus_pll_user_t_p,
 443                         MUX_SEL_TOP_FSYS0, 24, 1),
 444         MUX(CLK_MOUT_SCLK_MMC1_B, "mout_sclk_mmc1_b", mout_sclk_mmc1_b_p,
 445                         MUX_SEL_TOP_FSYS0, 20, 1),
 446         MUX(CLK_MOUT_SCLK_MMC1_A, "mout_sclk_mmc1_a", mout_bus_pll_user_t_p,
 447                         MUX_SEL_TOP_FSYS0, 16, 1),
 448         MUX(CLK_MOUT_SCLK_MMC0_D, "mout_sclk_mmc0_d", mout_sclk_mmc0_d_p,
 449                         MUX_SEL_TOP_FSYS0, 12, 1),
 450         MUX(CLK_MOUT_SCLK_MMC0_C, "mout_sclk_mmc0_c", mout_sclk_mmc0_c_p,
 451                         MUX_SEL_TOP_FSYS0, 8, 1),
 452         MUX(CLK_MOUT_SCLK_MMC0_B, "mout_sclk_mmc0_b", mout_sclk_mmc0_b_p,
 453                         MUX_SEL_TOP_FSYS0, 4, 1),
 454         MUX(CLK_MOUT_SCLK_MMC0_A, "mout_sclk_mmc0_a", mout_bus_pll_user_t_p,
 455                         MUX_SEL_TOP_FSYS0, 0, 1),
 456
 457         /* MUX_SEL_TOP_FSYS1 */
 458         MUX(CLK_MOUT_SCLK_PCIE_100, "mout_sclk_pcie_100", mout_bus_pll_user_t_p,
 459                         MUX_SEL_TOP_FSYS1, 12, 1),
 460         MUX(CLK_MOUT_SCLK_UFSUNIPRO, "mout_sclk_ufsunipro",
 461                         mout_mphy_pll_user_t_p, MUX_SEL_TOP_FSYS1, 8, 1),
 462         MUX(CLK_MOUT_SCLK_USBHOST30, "mout_sclk_usbhost30",
 463                         mout_bus_pll_user_t_p, MUX_SEL_TOP_FSYS1, 4, 1),
 464         MUX(CLK_MOUT_SCLK_USBDRD30, "mout_sclk_usbdrd30",
 465                         mout_bus_pll_user_t_p, MUX_SEL_TOP_FSYS1, 0, 1),
 466
 467         /* MUX_SEL_TOP_PERIC0 */
 468         MUX(CLK_MOUT_SCLK_SPI4, "mout_sclk_spi4", mout_bus_pll_user_t_p,
 469                         MUX_SEL_TOP_PERIC0, 28, 1),
 470         MUX(CLK_MOUT_SCLK_SPI3, "mout_sclk_spi3", mout_bus_pll_user_t_p,
 471                         MUX_SEL_TOP_PERIC0, 24, 1),
 472         MUX(CLK_MOUT_SCLK_UART2, "mout_sclk_uart2", mout_bus_pll_user_t_p,
 473                         MUX_SEL_TOP_PERIC0, 20, 1),
 474         MUX(CLK_MOUT_SCLK_UART1, "mout_sclk_uart1", mout_bus_pll_user_t_p,
 475                         MUX_SEL_TOP_PERIC0, 16, 1),
 476         MUX(CLK_MOUT_SCLK_UART0, "mout_sclk_uart0", mout_bus_pll_user_t_p,
 477                         MUX_SEL_TOP_PERIC0, 12, 1),
 478         MUX(CLK_MOUT_SCLK_SPI2, "mout_sclk_spi2", mout_bus_pll_user_t_p,
 479                         MUX_SEL_TOP_PERIC0, 8, 1),
 480         MUX(CLK_MOUT_SCLK_SPI1, "mout_sclk_spi1", mout_bus_pll_user_t_p,
 481                         MUX_SEL_TOP_PERIC0, 4, 1),
 482         MUX(CLK_MOUT_SCLK_SPI0, "mout_sclk_spi0", mout_bus_pll_user_t_p,
 483                         MUX_SEL_TOP_PERIC0, 0, 1),
 484
 485         /* MUX_SEL_TOP_PERIC1 */
 486         MUX(CLK_MOUT_SCLK_SLIMBUS, "mout_sclk_slimbus", mout_aud_pll_user_p,
 487                         MUX_SEL_TOP_PERIC1, 16, 1),
 488         MUX(CLK_MOUT_SCLK_SPDIF, "mout_sclk_spdif", mout_sclk_spdif_p,
 489                         MUX_SEL_TOP_PERIC1, 12, 2),
 490         MUX(CLK_MOUT_SCLK_AUDIO1, "mout_sclk_audio1", mout_sclk_audio1_p,
 491                         MUX_SEL_TOP_PERIC1, 4, 2),
 492         MUX(CLK_MOUT_SCLK_AUDIO0, "mout_sclk_audio0", mout_sclk_audio0_p,
 493                         MUX_SEL_TOP_PERIC1, 0, 2),
 494
 495         /* MUX_SEL_TOP_DISP */
 496         MUX(CLK_MOUT_SCLK_HDMI_SPDIF, "mout_sclk_hdmi_spdif",
 497                         mout_sclk_hdmi_spdif_p, MUX_SEL_TOP_DISP, 0, 1),
 498 };
 499
 500 static struct samsung_div_clock top_div_clks[] __initdata = {
 501         /* DIV_TOP0 */
 502         DIV(CLK_DIV_ACLK_CAM1_333, "div_aclk_cam1_333", "mout_aclk_cam1_333",
 503                         DIV_TOP0, 28, 3),
 504         DIV(CLK_DIV_ACLK_CAM1_400, "div_aclk_cam1_400", "mout_bus_pll_user",
 505                         DIV_TOP0, 24, 3),
 506         DIV(CLK_DIV_ACLK_CAM1_552, "div_aclk_cam1_552", "mout_aclk_cam1_552_b",
 507                         DIV_TOP0, 20, 3),
 508         DIV(CLK_DIV_ACLK_CAM0_333, "div_aclk_cam0_333", "mout_mfc_pll_user",
 509                         DIV_TOP0, 16, 3),
 510         DIV(CLK_DIV_ACLK_CAM0_400, "div_aclk_cam0_400", "mout_bus_pll_user",
 511                         DIV_TOP0, 12, 3),
 512         DIV(CLK_DIV_ACLK_CAM0_552, "div_aclk_cam0_552", "mout_isp_pll",
 513                         DIV_TOP0, 8, 3),
 514         DIV(CLK_DIV_ACLK_ISP_DIS_400, "div_aclk_isp_dis_400",
 515                         "mout_aclk_isp_dis_400", DIV_TOP0, 4, 4),
 516         DIV(CLK_DIV_ACLK_ISP_400, "div_aclk_isp_400",
 517                         "mout_aclk_isp_400", DIV_TOP0, 0, 4),
 518
 519         /* DIV_TOP1 */
 520         DIV(CLK_DIV_ACLK_GSCL_111, "div_aclk_gscl_111", "mout_aclk_gscl_333",
 521                         DIV_TOP1, 28, 3),
 522         DIV(CLK_DIV_ACLK_GSCL_333, "div_aclk_gscl_333", "mout_aclk_gscl_333",
 523                         DIV_TOP1, 24, 3),
 524         DIV(CLK_DIV_ACLK_HEVC_400, "div_aclk_hevc_400", "mout_aclk_hevc_400",
 525                         DIV_TOP1, 20, 3),
 526         DIV(CLK_DIV_ACLK_MFC_400, "div_aclk_mfc_400", "mout_aclk_mfc_400_c",
 527                         DIV_TOP1, 12, 3),
 528         DIV(CLK_DIV_ACLK_G2D_266, "div_aclk_g2d_266", "mout_bus_pll_user",
 529                         DIV_TOP1, 8, 3),
 530         DIV(CLK_DIV_ACLK_G2D_400, "div_aclk_g2d_400", "mout_aclk_g2d_400_b",
 531                         DIV_TOP1, 0, 3),
 532
 533         /* DIV_TOP2 */
 534         DIV(CLK_DIV_ACLK_MSCL_400, "div_aclk_mscl_400", "mout_aclk_mscl_400_b",
 535                         DIV_TOP2, 4, 3),
 536         DIV(CLK_DIV_ACLK_FSYS_200, "div_aclk_fsys_200", "mout_bus_pll_user",
 537                         DIV_TOP2, 0, 3),
 538
 539         /* DIV_TOP3 */
 540         DIV(CLK_DIV_ACLK_IMEM_SSSX_266, "div_aclk_imem_sssx_266",
 541                         "mout_bus_pll_user", DIV_TOP3, 24, 3),
 542         DIV(CLK_DIV_ACLK_IMEM_200, "div_aclk_imem_200",
 543                         "mout_bus_pll_user", DIV_TOP3, 20, 3),
 544         DIV(CLK_DIV_ACLK_IMEM_266, "div_aclk_imem_266",
 545                         "mout_bus_pll_user", DIV_TOP3, 16, 3),
 546         DIV(CLK_DIV_ACLK_PERIC_66_B, "div_aclk_peric_66_b",
 547                         "div_aclk_peric_66_a", DIV_TOP3, 12, 3),
 548         DIV(CLK_DIV_ACLK_PERIC_66_A, "div_aclk_peric_66_a",
 549                         "mout_bus_pll_user", DIV_TOP3, 8, 3),
 550         DIV(CLK_DIV_ACLK_PERIS_66_B, "div_aclk_peris_66_b",
 551                         "div_aclk_peris_66_a", DIV_TOP3, 4, 3),
 552         DIV(CLK_DIV_ACLK_PERIS_66_A, "div_aclk_peris_66_a",
 553                         "mout_bus_pll_user", DIV_TOP3, 0, 3),
 554
 555         /* DIV_TOP4 */
 556         DIV(CLK_DIV_ACLK_G3D_400, "div_aclk_g3d_400", "mout_bus_pll_user",
 557                         DIV_TOP4, 8, 3),
 558         DIV(CLK_DIV_ACLK_BUS0_400, "div_aclk_bus0_400", "mout_aclk_bus0_400",
 559                         DIV_TOP4, 4, 3),
 560         DIV(CLK_DIV_ACLK_BUS1_400, "div_aclk_bus1_400", "mout_bus_pll_user",
 561                         DIV_TOP4, 0, 3),
 562
 563         /* DIV_TOP_MSCL */
 564         DIV(CLK_DIV_SCLK_JPEG, "div_sclk_jpeg", "mout_sclk_jpeg_c",
 565                         DIV_TOP_MSCL, 0, 4),
 566
 567         /* DIV_TOP_CAM10 */
 568         DIV(CLK_DIV_SCLK_ISP_UART, "div_sclk_isp_uart", "mout_sclk_isp_uart",
 569                         DIV_TOP_CAM10, 24, 5),
 570         DIV(CLK_DIV_SCLK_ISP_SPI1_B, "div_sclk_isp_spi1_b",
 571                         "div_sclk_isp_spi1_a", DIV_TOP_CAM10, 16, 8),
 572         DIV(CLK_DIV_SCLK_ISP_SPI1_A, "div_sclk_isp_spi1_a",
 573                         "mout_sclk_isp_spi1", DIV_TOP_CAM10, 12, 4),
 574         DIV(CLK_DIV_SCLK_ISP_SPI0_B, "div_sclk_isp_spi0_b",
 575                         "div_sclk_isp_spi0_a", DIV_TOP_CAM10, 4, 8),
 576         DIV(CLK_DIV_SCLK_ISP_SPI0_A, "div_sclk_isp_spi0_a",
 577                         "mout_sclk_isp_spi0", DIV_TOP_CAM10, 0, 4),
 578
 579         /* DIV_TOP_CAM11 */
 580         DIV(CLK_DIV_SCLK_ISP_SENSOR2_B, "div_sclk_isp_sensor2_b",
 581                         "div_sclk_isp_sensor2_a", DIV_TOP_CAM11, 20, 4),
 582         DIV(CLK_DIV_SCLK_ISP_SENSOR2_A, "div_sclk_isp_sensor2_a",
 583                         "mout_sclk_isp_sensor2", DIV_TOP_CAM11, 16, 4),
 584         DIV(CLK_DIV_SCLK_ISP_SENSOR1_B, "div_sclk_isp_sensor1_b",
 585                         "div_sclk_isp_sensor1_a", DIV_TOP_CAM11, 12, 4),
 586         DIV(CLK_DIV_SCLK_ISP_SENSOR1_A, "div_sclk_isp_sensor1_a",
 587                         "mout_sclk_isp_sensor1", DIV_TOP_CAM11, 8, 4),
 588         DIV(CLK_DIV_SCLK_ISP_SENSOR0_B, "div_sclk_isp_sensor0_b",
 589                         "div_sclk_isp_sensor0_a", DIV_TOP_CAM11, 4, 4),
 590         DIV(CLK_DIV_SCLK_ISP_SENSOR0_A, "div_sclk_isp_sensor0_a",
 591                         "mout_sclk_isp_sensor0", DIV_TOP_CAM11, 0, 4),
 592
 593         /* DIV_TOP_FSYS0 */
 594         DIV(CLK_DIV_SCLK_MMC1_B, "div_sclk_mmc1_b", "div_sclk_mmc1_a",
 595                         DIV_TOP_FSYS0, 16, 8),
 596         DIV(CLK_DIV_SCLK_MMC1_A, "div_sclk_mmc1_a", "mout_sclk_mmc1_b",
 597                         DIV_TOP_FSYS0, 12, 4),
 598         DIV_F(CLK_DIV_SCLK_MMC0_B, "div_sclk_mmc0_b", "div_sclk_mmc0_a",
 599                         DIV_TOP_FSYS0, 4, 8, CLK_SET_RATE_PARENT, 0),
 600         DIV_F(CLK_DIV_SCLK_MMC0_A, "div_sclk_mmc0_a", "mout_sclk_mmc0_d",
 601                         DIV_TOP_FSYS0, 0, 4, CLK_SET_RATE_PARENT, 0),
 602
 603         /* DIV_TOP_FSYS1 */
 604         DIV(CLK_DIV_SCLK_MMC2_B, "div_sclk_mmc2_b", "div_sclk_mmc2_a",
 605                         DIV_TOP_FSYS1, 4, 8),
 606         DIV(CLK_DIV_SCLK_MMC2_A, "div_sclk_mmc2_a", "mout_sclk_mmc2_b",
 607                         DIV_TOP_FSYS1, 0, 4),
 608
 609         /* DIV_TOP_FSYS2 */
 610         DIV(CLK_DIV_SCLK_PCIE_100, "div_sclk_pcie_100", "mout_sclk_pcie_100",
 611                         DIV_TOP_FSYS2, 12, 3),
 612         DIV(CLK_DIV_SCLK_USBHOST30, "div_sclk_usbhost30",
 613                         "mout_sclk_usbhost30", DIV_TOP_FSYS2, 8, 4),
 614         DIV(CLK_DIV_SCLK_UFSUNIPRO, "div_sclk_ufsunipro",
 615                         "mout_sclk_ufsunipro", DIV_TOP_FSYS2, 4, 4),
 616         DIV(CLK_DIV_SCLK_USBDRD30, "div_sclk_usbdrd30", "mout_sclk_usbdrd30",
 617                         DIV_TOP_FSYS2, 0, 4),
 618
 619         /* DIV_TOP_PERIC0 */
 620         DIV(CLK_DIV_SCLK_SPI1_B, "div_sclk_spi1_b", "div_sclk_spi1_a",
 621                         DIV_TOP_PERIC0, 16, 8),
 622         DIV(CLK_DIV_SCLK_SPI1_A, "div_sclk_spi1_a", "mout_sclk_spi1",
 623                         DIV_TOP_PERIC0, 12, 4),
 624         DIV(CLK_DIV_SCLK_SPI0_B, "div_sclk_spi0_b", "div_sclk_spi0_a",
 625                         DIV_TOP_PERIC0, 4, 8),
 626         DIV(CLK_DIV_SCLK_SPI0_A, "div_sclk_spi0_a", "mout_sclk_spi0",
 627                         DIV_TOP_PERIC0, 0, 4),
 628
 629         /* DIV_TOP_PERIC1 */
 630         DIV(CLK_DIV_SCLK_SPI2_B, "div_sclk_spi2_b", "div_sclk_spi2_a",
 631                         DIV_TOP_PERIC1, 4, 8),
 632         DIV(CLK_DIV_SCLK_SPI2_A, "div_sclk_spi2_a", "mout_sclk_spi2",
 633                         DIV_TOP_PERIC1, 0, 4),
 634
 635         /* DIV_TOP_PERIC2 */
 636         DIV(CLK_DIV_SCLK_UART2, "div_sclk_uart2", "mout_sclk_uart2",
 637                         DIV_TOP_PERIC2, 8, 4),
 638         DIV(CLK_DIV_SCLK_UART1, "div_sclk_uart1", "mout_sclk_uart0",
 639                         DIV_TOP_PERIC2, 4, 4),
 640         DIV(CLK_DIV_SCLK_UART0, "div_sclk_uart0", "mout_sclk_uart1",
 641                         DIV_TOP_PERIC2, 0, 4),
 642
 643         /* DIV_TOP_PERIC3 */
 644         DIV(CLK_DIV_SCLK_I2S1, "div_sclk_i2s1", "sclk_audio1",
 645                         DIV_TOP_PERIC3, 16, 6),
 646         DIV(CLK_DIV_SCLK_PCM1, "div_sclk_pcm1", "sclk_audio1",
 647                         DIV_TOP_PERIC3, 8, 8),
 648         DIV(CLK_DIV_SCLK_AUDIO1, "div_sclk_audio1", "mout_sclk_audio1",
 649                         DIV_TOP_PERIC3, 4, 4),
 650         DIV(CLK_DIV_SCLK_AUDIO0, "div_sclk_audio0", "mout_sclk_audio0",
 651                         DIV_TOP_PERIC3, 0, 4),
 652
 653         /* DIV_TOP_PERIC4 */
 654         DIV(CLK_DIV_SCLK_SPI4_B, "div_sclk_spi4_b", "div_sclk_spi4_a",
 655                         DIV_TOP_PERIC4, 16, 8),
 656         DIV(CLK_DIV_SCLK_SPI4_A, "div_sclk_spi4_a", "mout_sclk_spi4",
 657                         DIV_TOP_PERIC4, 12, 4),
 658         DIV(CLK_DIV_SCLK_SPI3_B, "div_sclk_spi3_b", "div_sclk_spi3_a",
 659                         DIV_TOP_PERIC4, 4, 8),
 660         DIV(CLK_DIV_SCLK_SPI3_A, "div_sclk_spi3_a", "mout_sclk_spi3",
 661                         DIV_TOP_PERIC4, 0, 4),
 662 };
 663
 664 static struct samsung_gate_clock top_gate_clks[] __initdata = {
 665         /* ENABLE_ACLK_TOP */
 666         GATE(CLK_ACLK_G3D_400, "aclk_g3d_400", "div_aclk_g3d_400",
 667                         ENABLE_ACLK_TOP, 30, 0, 0),
 668         GATE(CLK_ACLK_IMEM_SSX_266, "aclk_imem_ssx_266",
 669                         "div_aclk_imem_sssx_266", ENABLE_ACLK_TOP,
 670                         29, CLK_IGNORE_UNUSED, 0),
 671         GATE(CLK_ACLK_BUS0_400, "aclk_bus0_400", "div_aclk_bus0_400",
 672                         ENABLE_ACLK_TOP, 26,
 673                         CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
 674         GATE(CLK_ACLK_BUS1_400, "aclk_bus1_400", "div_aclk_bus1_400",
 675                         ENABLE_ACLK_TOP, 25,
 676                         CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
 677         GATE(CLK_ACLK_IMEM_200, "aclk_imem_200", "div_aclk_imem_266",
 678                         ENABLE_ACLK_TOP, 24,
 679                         CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
 680         GATE(CLK_ACLK_IMEM_266, "aclk_imem_266", "div_aclk_imem_200",
 681                         ENABLE_ACLK_TOP, 23,
 682                         CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
 683         GATE(CLK_ACLK_PERIC_66, "aclk_peric_66", "div_aclk_peric_66_b",
 684                         ENABLE_ACLK_TOP, 22,
 685                         CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
 686         GATE(CLK_ACLK_PERIS_66, "aclk_peris_66", "div_aclk_peris_66_b",
 687                         ENABLE_ACLK_TOP, 21,
 688                         CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
 689         GATE(CLK_ACLK_MSCL_400, "aclk_mscl_400", "div_aclk_mscl_400",
 690                         ENABLE_ACLK_TOP, 19,
 691                         CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
 692         GATE(CLK_ACLK_FSYS_200, "aclk_fsys_200", "div_aclk_fsys_200",
 693                         ENABLE_ACLK_TOP, 18,
 694                         CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
 695         GATE(CLK_ACLK_GSCL_111, "aclk_gscl_111", "div_aclk_gscl_111",
 696                         ENABLE_ACLK_TOP, 15,
 697                         CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
 698         GATE(CLK_ACLK_GSCL_333, "aclk_gscl_333", "div_aclk_gscl_333",
 699                         ENABLE_ACLK_TOP, 14,
 700                         CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
 701         GATE(CLK_ACLK_CAM1_333, "aclk_cam1_333", "div_aclk_cam1_333",
 702                         ENABLE_ACLK_TOP, 13,
 703                         CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
 704         GATE(CLK_ACLK_CAM1_400, "aclk_cam1_400", "div_aclk_cam1_400",
 705                         ENABLE_ACLK_TOP, 12,
 706                         CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
 707         GATE(CLK_ACLK_CAM1_552, "aclk_cam1_552", "div_aclk_cam1_552",
 708                         ENABLE_ACLK_TOP, 11,
 709                         CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
 710         GATE(CLK_ACLK_CAM0_333, "aclk_cam0_333", "div_aclk_cam0_333",
 711                         ENABLE_ACLK_TOP, 10,
 712                         CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
 713         GATE(CLK_ACLK_CAM0_400, "aclk_cam0_400", "div_aclk_cam0_400",
 714                         ENABLE_ACLK_TOP, 9,
 715                         CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
 716         GATE(CLK_ACLK_CAM0_552, "aclk_cam0_552", "div_aclk_cam0_552",
 717                         ENABLE_ACLK_TOP, 8,
 718                         CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
 719         GATE(CLK_ACLK_ISP_DIS_400, "aclk_isp_dis_400", "div_aclk_isp_dis_400",
 720                         ENABLE_ACLK_TOP, 7,
 721                         CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
 722         GATE(CLK_ACLK_ISP_400, "aclk_isp_400", "div_aclk_isp_400",
 723                         ENABLE_ACLK_TOP, 6,
 724                         CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
 725         GATE(CLK_ACLK_HEVC_400, "aclk_hevc_400", "div_aclk_hevc_400",
 726                         ENABLE_ACLK_TOP, 5,
 727                         CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
 728         GATE(CLK_ACLK_MFC_400, "aclk_mfc_400", "div_aclk_mfc_400",
 729                         ENABLE_ACLK_TOP, 3,
 730                         CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
 731         GATE(CLK_ACLK_G2D_266, "aclk_g2d_266", "div_aclk_g2d_266",
 732                         ENABLE_ACLK_TOP, 2,
 733                         CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
 734         GATE(CLK_ACLK_G2D_400, "aclk_g2d_400", "div_aclk_g2d_400",
 735                         ENABLE_ACLK_TOP, 0,
 736                         CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
 737
 738         /* ENABLE_SCLK_TOP_MSCL */
 739         GATE(CLK_SCLK_JPEG_MSCL, "sclk_jpeg_mscl", "div_sclk_jpeg",
 740                         ENABLE_SCLK_TOP_MSCL, 0, 0, 0),
 741
 742         /* ENABLE_SCLK_TOP_CAM1 */
 743         GATE(CLK_SCLK_ISP_SENSOR2, "sclk_isp_sensor2", "div_sclk_isp_sensor2_b",
 744                         ENABLE_SCLK_TOP_CAM1, 7, 0, 0),
 745         GATE(CLK_SCLK_ISP_SENSOR1, "sclk_isp_sensor1", "div_sclk_isp_sensor1_b",
 746                         ENABLE_SCLK_TOP_CAM1, 6, 0, 0),
 747         GATE(CLK_SCLK_ISP_SENSOR0, "sclk_isp_sensor0", "div_sclk_isp_sensor0_b",
 748                         ENABLE_SCLK_TOP_CAM1, 5, 0, 0),
 749         GATE(CLK_SCLK_ISP_MCTADC_CAM1, "sclk_isp_mctadc_cam1", "oscclk",
 750                         ENABLE_SCLK_TOP_CAM1, 4, 0, 0),
 751         GATE(CLK_SCLK_ISP_UART_CAM1, "sclk_isp_uart_cam1", "div_sclk_isp_uart",
 752                         ENABLE_SCLK_TOP_CAM1, 2, 0, 0),
 753         GATE(CLK_SCLK_ISP_SPI1_CAM1, "sclk_isp_spi1_cam1", "div_sclk_isp_spi1_b",
 754                         ENABLE_SCLK_TOP_CAM1, 1, 0, 0),
 755         GATE(CLK_SCLK_ISP_SPI0_CAM1, "sclk_isp_spi0_cam1", "div_sclk_isp_spi0_b",
 756                         ENABLE_SCLK_TOP_CAM1, 0, 0, 0),
 757
 758         /* ENABLE_SCLK_TOP_DISP */
 759         GATE(CLK_SCLK_HDMI_SPDIF_DISP, "sclk_hdmi_spdif_disp",
 760                         "mout_sclk_hdmi_spdif", ENABLE_SCLK_TOP_DISP, 0,
 761                         CLK_IGNORE_UNUSED, 0),
 762
 763         /* ENABLE_SCLK_TOP_FSYS */
 764         GATE(CLK_SCLK_PCIE_100_FSYS, "sclk_pcie_100_fsys", "div_sclk_pcie_100",
 765                         ENABLE_SCLK_TOP_FSYS, 7, CLK_IGNORE_UNUSED, 0),
 766         GATE(CLK_SCLK_MMC2_FSYS, "sclk_mmc2_fsys", "div_sclk_mmc2_b",
 767                         ENABLE_SCLK_TOP_FSYS, 6, CLK_SET_RATE_PARENT, 0),
 768         GATE(CLK_SCLK_MMC1_FSYS, "sclk_mmc1_fsys", "div_sclk_mmc1_b",
 769                         ENABLE_SCLK_TOP_FSYS, 5, CLK_SET_RATE_PARENT, 0),
 770         GATE(CLK_SCLK_MMC0_FSYS, "sclk_mmc0_fsys", "div_sclk_mmc0_b",
 771                         ENABLE_SCLK_TOP_FSYS, 4, CLK_SET_RATE_PARENT, 0),
 772         GATE(CLK_SCLK_UFSUNIPRO_FSYS, "sclk_ufsunipro_fsys",
 773                         "div_sclk_ufsunipro", ENABLE_SCLK_TOP_FSYS,
 774                         3, CLK_SET_RATE_PARENT, 0),
 775         GATE(CLK_SCLK_USBHOST30_FSYS, "sclk_usbhost30_fsys",
 776                         "div_sclk_usbhost30", ENABLE_SCLK_TOP_FSYS,
 777                         1, CLK_SET_RATE_PARENT, 0),
 778         GATE(CLK_SCLK_USBDRD30_FSYS, "sclk_usbdrd30_fsys",
 779                         "div_sclk_usbdrd30", ENABLE_SCLK_TOP_FSYS,
 780                         0, CLK_SET_RATE_PARENT, 0),
 781
 782         /* ENABLE_SCLK_TOP_PERIC */
 783         GATE(CLK_SCLK_SPI4_PERIC, "sclk_spi4_peric", "div_sclk_spi4_b",
 784                         ENABLE_SCLK_TOP_PERIC, 12, CLK_SET_RATE_PARENT, 0),
 785         GATE(CLK_SCLK_SPI3_PERIC, "sclk_spi3_peric", "div_sclk_spi3_b",
 786                         ENABLE_SCLK_TOP_PERIC, 11, CLK_SET_RATE_PARENT, 0),
 787         GATE(CLK_SCLK_SPDIF_PERIC, "sclk_spdif_peric", "mout_sclk_spdif",
 788                         ENABLE_SCLK_TOP_PERIC, 9, CLK_SET_RATE_PARENT, 0),
 789         GATE(CLK_SCLK_I2S1_PERIC, "sclk_i2s1_peric", "div_sclk_i2s1",
 790                         ENABLE_SCLK_TOP_PERIC, 8, CLK_SET_RATE_PARENT, 0),
 791         GATE(CLK_SCLK_PCM1_PERIC, "sclk_pcm1_peric", "div_sclk_pcm1",
 792                         ENABLE_SCLK_TOP_PERIC, 7, CLK_SET_RATE_PARENT, 0),
 793         GATE(CLK_SCLK_UART2_PERIC, "sclk_uart2_peric", "div_sclk_uart2",
 794                         ENABLE_SCLK_TOP_PERIC, 5, CLK_SET_RATE_PARENT |
 795                         CLK_IGNORE_UNUSED, 0),
 796         GATE(CLK_SCLK_UART1_PERIC, "sclk_uart1_peric", "div_sclk_uart1",
 797                         ENABLE_SCLK_TOP_PERIC, 4, CLK_SET_RATE_PARENT |
 798                         CLK_IGNORE_UNUSED, 0),
 799         GATE(CLK_SCLK_UART0_PERIC, "sclk_uart0_peric", "div_sclk_uart0",
 800                         ENABLE_SCLK_TOP_PERIC, 3, CLK_SET_RATE_PARENT |
 801                         CLK_IGNORE_UNUSED, 0),
 802         GATE(CLK_SCLK_SPI2_PERIC, "sclk_spi2_peric", "div_sclk_spi2_b",
 803                         ENABLE_SCLK_TOP_PERIC, 2, CLK_SET_RATE_PARENT, 0),
 804         GATE(CLK_SCLK_SPI1_PERIC, "sclk_spi1_peric", "div_sclk_spi1_b",
 805                         ENABLE_SCLK_TOP_PERIC, 1, CLK_SET_RATE_PARENT, 0),
 806         GATE(CLK_SCLK_SPI0_PERIC, "sclk_spi0_peric", "div_sclk_spi0_b",
 807                         ENABLE_SCLK_TOP_PERIC, 0, CLK_SET_RATE_PARENT, 0),
 808
 809         /* MUX_ENABLE_TOP_PERIC1 */
 810         GATE(CLK_SCLK_SLIMBUS, "sclk_slimbus", "mout_sclk_slimbus",
 811                         MUX_ENABLE_TOP_PERIC1, 16, 0, 0),
 812         GATE(CLK_SCLK_AUDIO1, "sclk_audio1", "div_sclk_audio1",
 813                         MUX_ENABLE_TOP_PERIC1, 4, 0, 0),
 814         GATE(CLK_SCLK_AUDIO0, "sclk_audio0", "div_sclk_audio0",
 815                         MUX_ENABLE_TOP_PERIC1, 0, 0, 0),
 816 };
 817
 818 /*
 819  * ATLAS_PLL & APOLLO_PLL & MEM0_PLL & MEM1_PLL & BUS_PLL & MFC_PLL
 820  * & MPHY_PLL & G3D_PLL & DISP_PLL & ISP_PLL
 821  */
 822 static struct samsung_pll_rate_table exynos5443_pll_rates[] = {
 823         PLL_35XX_RATE(2500000000U, 625, 6,  0),
 824         PLL_35XX_RATE(2400000000U, 500, 5,  0),
 825         PLL_35XX_RATE(2300000000U, 575, 6,  0),
 826         PLL_35XX_RATE(2200000000U, 550, 6,  0),
 827         PLL_35XX_RATE(2100000000U, 350, 4,  0),
 828         PLL_35XX_RATE(2000000000U, 500, 6,  0),
 829         PLL_35XX_RATE(1900000000U, 475, 6,  0),
 830         PLL_35XX_RATE(1800000000U, 375, 5,  0),
 831         PLL_35XX_RATE(1700000000U, 425, 6,  0),
 832         PLL_35XX_RATE(1600000000U, 400, 6,  0),
 833         PLL_35XX_RATE(1500000000U, 250, 4,  0),
 834         PLL_35XX_RATE(1400000000U, 350, 6,  0),
 835         PLL_35XX_RATE(1332000000U, 222, 4,  0),
 836         PLL_35XX_RATE(1300000000U, 325, 6,  0),
 837         PLL_35XX_RATE(1200000000U, 500, 5,  1),
 838         PLL_35XX_RATE(1100000000U, 550, 6,  1),
 839         PLL_35XX_RATE(1086000000U, 362, 4,  1),
 840         PLL_35XX_RATE(1066000000U, 533, 6,  1),
 841         PLL_35XX_RATE(1000000000U, 500, 6,  1),
 842         PLL_35XX_RATE(933000000U,  311, 4,  1),
 843         PLL_35XX_RATE(921000000U,  307, 4,  1),
 844         PLL_35XX_RATE(900000000U,  375, 5,  1),
 845         PLL_35XX_RATE(825000000U,  275, 4,  1),
 846         PLL_35XX_RATE(800000000U,  400, 6,  1),
 847         PLL_35XX_RATE(733000000U,  733, 12, 1),
 848         PLL_35XX_RATE(700000000U,  175, 3,  1),
 849         PLL_35XX_RATE(667000000U,  222, 4,  1),
 850         PLL_35XX_RATE(633000000U,  211, 4,  1),
 851         PLL_35XX_RATE(600000000U,  500, 5,  2),
 852         PLL_35XX_RATE(552000000U,  460, 5,  2),
 853         PLL_35XX_RATE(550000000U,  550, 6,  2),
 854         PLL_35XX_RATE(543000000U,  362, 4,  2),
 855         PLL_35XX_RATE(533000000U,  533, 6,  2),
 856         PLL_35XX_RATE(500000000U,  500, 6,  2),
 857         PLL_35XX_RATE(444000000U,  370, 5,  2),
 858         PLL_35XX_RATE(420000000U,  350, 5,  2),
 859         PLL_35XX_RATE(400000000U,  400, 6,  2),
 860         PLL_35XX_RATE(350000000U,  350, 6,  2),
 861         PLL_35XX_RATE(333000000U,  222, 4,  2),
 862         PLL_35XX_RATE(300000000U,  500, 5,  3),
 863         PLL_35XX_RATE(266000000U,  532, 6,  3),
 864         PLL_35XX_RATE(200000000U,  400, 6,  3),
 865         PLL_35XX_RATE(166000000U,  332, 6,  3),
 866         PLL_35XX_RATE(160000000U,  320, 6,  3),
 867         PLL_35XX_RATE(133000000U,  532, 6,  4),
 868         PLL_35XX_RATE(100000000U,  400, 6,  4),
 869         { /* sentinel */ }
 870 };
 871
 872 /* AUD_PLL */
 873 static struct samsung_pll_rate_table exynos5443_aud_pll_rates[] = {
 874         PLL_36XX_RATE(400000000U, 200, 3, 2,      0),
 875         PLL_36XX_RATE(393216000U, 197, 3, 2, -25690),
 876         PLL_36XX_RATE(384000000U, 128, 2, 2,      0),
 877         PLL_36XX_RATE(368640000U, 246, 4, 2, -15729),
 878         PLL_36XX_RATE(361507200U, 181, 3, 2, -16148),
 879         PLL_36XX_RATE(338688000U, 113, 2, 2,  -6816),
 880         PLL_36XX_RATE(294912000U,  98, 1, 3,  19923),
 881         PLL_36XX_RATE(288000000U,  96, 1, 3,      0),
 882         PLL_36XX_RATE(252000000U,  84, 1, 3,      0),
 883         { /* sentinel */ }
 884 };
 885
 886 static struct samsung_pll_clock top_pll_clks[] __initdata = {
 887         PLL(pll_35xx, CLK_FOUT_ISP_PLL, "fout_isp_pll", "oscclk",
 888                 ISP_PLL_LOCK, ISP_PLL_CON0, exynos5443_pll_rates),
 889         PLL(pll_36xx, CLK_FOUT_AUD_PLL, "fout_aud_pll", "oscclk",
 890                 AUD_PLL_LOCK, AUD_PLL_CON0, exynos5443_aud_pll_rates),
 891 };
 892
 893 static struct samsung_cmu_info top_cmu_info __initdata = {
 894         .pll_clks               = top_pll_clks,
 895         .nr_pll_clks            = ARRAY_SIZE(top_pll_clks),
 896         .mux_clks               = top_mux_clks,
 897         .nr_mux_clks            = ARRAY_SIZE(top_mux_clks),
 898         .div_clks               = top_div_clks,
 899         .nr_div_clks            = ARRAY_SIZE(top_div_clks),
 900         .gate_clks              = top_gate_clks,
 901         .nr_gate_clks           = ARRAY_SIZE(top_gate_clks),
 902         .fixed_clks             = top_fixed_clks,
 903         .nr_fixed_clks          = ARRAY_SIZE(top_fixed_clks),
 904         .fixed_factor_clks      = top_fixed_factor_clks,
 905         .nr_fixed_factor_clks   = ARRAY_SIZE(top_fixed_factor_clks),
 906         .nr_clk_ids             = TOP_NR_CLK,
 907         .clk_regs               = top_clk_regs,
 908         .nr_clk_regs            = ARRAY_SIZE(top_clk_regs),
 909 };
 910
 911 static void __init exynos5433_cmu_top_init(struct device_node *np)
 912 {
 913         samsung_cmu_register_one(np, &top_cmu_info);
 914 }
 915 CLK_OF_DECLARE(exynos5433_cmu_top, "samsung,exynos5433-cmu-top",
 916                 exynos5433_cmu_top_init);
 917
 918 /*
 919  * Register offset definitions for CMU_CPIF
 920  */
 921 #define MPHY_PLL_LOCK           0x0000
 922 #define MPHY_PLL_CON0           0x0100
 923 #define MPHY_PLL_CON1           0x0104
 924 #define MPHY_PLL_FREQ_DET       0x010c
 925 #define MUX_SEL_CPIF0           0x0200
 926 #define DIV_CPIF                0x0600
 927 #define ENABLE_SCLK_CPIF        0x0a00
 928
 929 static unsigned long cpif_clk_regs[] __initdata = {
 930         MPHY_PLL_LOCK,
 931         MPHY_PLL_CON0,
 932         MPHY_PLL_CON1,
 933         MPHY_PLL_FREQ_DET,
 934         MUX_SEL_CPIF0,
 935         DIV_CPIF,
 936         ENABLE_SCLK_CPIF,
 937 };
 938
 939 /* list of all parent clock list */
 940 PNAME(mout_mphy_pll_p)          = { "oscclk", "fout_mphy_pll", };
 941
 942 static struct samsung_pll_clock cpif_pll_clks[] __initdata = {
 943         PLL(pll_35xx, CLK_FOUT_MPHY_PLL, "fout_mphy_pll", "oscclk",
 944                 MPHY_PLL_LOCK, MPHY_PLL_CON0, exynos5443_pll_rates),
 945 };
 946
 947 static struct samsung_mux_clock cpif_mux_clks[] __initdata = {
 948         /* MUX_SEL_CPIF0 */
 949         MUX(CLK_MOUT_MPHY_PLL, "mout_mphy_pll", mout_mphy_pll_p, MUX_SEL_CPIF0,
 950                         0, 1),
 951 };
 952
 953 static struct samsung_div_clock cpif_div_clks[] __initdata = {
 954         /* DIV_CPIF */
 955         DIV(CLK_DIV_SCLK_MPHY, "div_sclk_mphy", "mout_mphy_pll", DIV_CPIF,
 956                         0, 6),
 957 };
 958
 959 static struct samsung_gate_clock cpif_gate_clks[] __initdata = {
 960         /* ENABLE_SCLK_CPIF */
 961         GATE(CLK_SCLK_MPHY_PLL, "sclk_mphy_pll", "mout_mphy_pll",
 962                         ENABLE_SCLK_CPIF, 9, CLK_IGNORE_UNUSED, 0),
 963         GATE(CLK_SCLK_UFS_MPHY, "sclk_ufs_mphy", "div_sclk_mphy",
 964                         ENABLE_SCLK_CPIF, 4, 0, 0),
 965 };
 966
 967 static struct samsung_cmu_info cpif_cmu_info __initdata = {
 968         .pll_clks               = cpif_pll_clks,
 969         .nr_pll_clks            = ARRAY_SIZE(cpif_pll_clks),
 970         .mux_clks               = cpif_mux_clks,
 971         .nr_mux_clks            = ARRAY_SIZE(cpif_mux_clks),
 972         .div_clks               = cpif_div_clks,
 973         .nr_div_clks            = ARRAY_SIZE(cpif_div_clks),
 974         .gate_clks              = cpif_gate_clks,
 975         .nr_gate_clks           = ARRAY_SIZE(cpif_gate_clks),
 976         .nr_clk_ids             = CPIF_NR_CLK,
 977         .clk_regs               = cpif_clk_regs,
 978         .nr_clk_regs            = ARRAY_SIZE(cpif_clk_regs),
 979 };
 980
 981 static void __init exynos5433_cmu_cpif_init(struct device_node *np)
 982 {
 983         samsung_cmu_register_one(np, &cpif_cmu_info);
 984 }
 985 CLK_OF_DECLARE(exynos5433_cmu_cpif, "samsung,exynos5433-cmu-cpif",
 986                 exynos5433_cmu_cpif_init);
 987
 988 /*
 989  * Register offset definitions for CMU_MIF
 990  */
 991 #define MEM0_PLL_LOCK                   0x0000
 992 #define MEM1_PLL_LOCK                   0x0004
 993 #define BUS_PLL_LOCK                    0x0008
 994 #define MFC_PLL_LOCK                    0x000c
 995 #define MEM0_PLL_CON0                   0x0100
 996 #define MEM0_PLL_CON1                   0x0104
 997 #define MEM0_PLL_FREQ_DET               0x010c
 998 #define MEM1_PLL_CON0                   0x0110
 999 #define MEM1_PLL_CON1                   0x0114
1000 #define MEM1_PLL_FREQ_DET               0x011c
1001 #define BUS_PLL_CON0                    0x0120
1002 #define BUS_PLL_CON1                    0x0124
1003 #define BUS_PLL_FREQ_DET                0x012c
1004 #define MFC_PLL_CON0                    0x0130
1005 #define MFC_PLL_CON1                    0x0134
1006 #define MFC_PLL_FREQ_DET                0x013c
1007 #define MUX_SEL_MIF0                    0x0200
1008 #define MUX_SEL_MIF1                    0x0204
1009 #define MUX_SEL_MIF2                    0x0208
1010 #define MUX_SEL_MIF3                    0x020c
1011 #define MUX_SEL_MIF4                    0x0210
1012 #define MUX_SEL_MIF5                    0x0214
1013 #define MUX_SEL_MIF6                    0x0218
1014 #define MUX_SEL_MIF7                    0x021c
1015 #define MUX_ENABLE_MIF0                 0x0300
1016 #define MUX_ENABLE_MIF1                 0x0304
1017 #define MUX_ENABLE_MIF2                 0x0308
1018 #define MUX_ENABLE_MIF3                 0x030c
1019 #define MUX_ENABLE_MIF4                 0x0310
1020 #define MUX_ENABLE_MIF5                 0x0314
1021 #define MUX_ENABLE_MIF6                 0x0318
1022 #define MUX_ENABLE_MIF7                 0x031c
1023 #define MUX_STAT_MIF0                   0x0400
1024 #define MUX_STAT_MIF1                   0x0404
1025 #define MUX_STAT_MIF2                   0x0408
1026 #define MUX_STAT_MIF3                   0x040c
1027 #define MUX_STAT_MIF4                   0x0410
1028 #define MUX_STAT_MIF5                   0x0414
1029 #define MUX_STAT_MIF6                   0x0418
1030 #define MUX_STAT_MIF7                   0x041c
1031 #define DIV_MIF1                        0x0604
1032 #define DIV_MIF2                        0x0608
1033 #define DIV_MIF3                        0x060c
1034 #define DIV_MIF4                        0x0610
1035 #define DIV_MIF5                        0x0614
1036 #define DIV_MIF_PLL_FREQ_DET            0x0618
1037 #define DIV_STAT_MIF1                   0x0704
1038 #define DIV_STAT_MIF2                   0x0708
1039 #define DIV_STAT_MIF3                   0x070c
1040 #define DIV_STAT_MIF4                   0x0710
1041 #define DIV_STAT_MIF5                   0x0714
1042 #define DIV_STAT_MIF_PLL_FREQ_DET       0x0718
1043 #define ENABLE_ACLK_MIF0                0x0800
1044 #define ENABLE_ACLK_MIF1                0x0804
1045 #define ENABLE_ACLK_MIF2                0x0808
1046 #define ENABLE_ACLK_MIF3                0x080c
1047 #define ENABLE_PCLK_MIF                 0x0900
1048 #define ENABLE_PCLK_MIF_SECURE_DREX0_TZ 0x0904
1049 #define ENABLE_PCLK_MIF_SECURE_DREX1_TZ 0x0908
1050 #define ENABLE_PCLK_MIF_SECURE_MONOTONIC_CNT    0x090c
1051 #define ENABLE_PCLK_MIF_SECURE_RTC      0x0910
1052 #define ENABLE_SCLK_MIF                 0x0a00
1053 #define ENABLE_IP_MIF0                  0x0b00
1054 #define ENABLE_IP_MIF1                  0x0b04
1055 #define ENABLE_IP_MIF2                  0x0b08
1056 #define ENABLE_IP_MIF3                  0x0b0c
1057 #define ENABLE_IP_MIF_SECURE_DREX0_TZ   0x0b10
1058 #define ENABLE_IP_MIF_SECURE_DREX1_TZ   0x0b14
1059 #define ENABLE_IP_MIF_SECURE_MONOTONIC_CNT      0x0b18
1060 #define ENABLE_IP_MIF_SECURE_RTC        0x0b1c
1061 #define CLKOUT_CMU_MIF                  0x0c00
1062 #define CLKOUT_CMU_MIF_DIV_STAT         0x0c04
1063 #define DREX_FREQ_CTRL0                 0x1000
1064 #define DREX_FREQ_CTRL1                 0x1004
1065 #define PAUSE                           0x1008
1066 #define DDRPHY_LOCK_CTRL                0x100c
1067
1068 static unsigned long mif_clk_regs[] __initdata = {
1069         MEM0_PLL_LOCK,
1070         MEM1_PLL_LOCK,
1071         BUS_PLL_LOCK,
1072         MFC_PLL_LOCK,
1073         MEM0_PLL_CON0,
1074         MEM0_PLL_CON1,
1075         MEM0_PLL_FREQ_DET,
1076         MEM1_PLL_CON0,
1077         MEM1_PLL_CON1,
1078         MEM1_PLL_FREQ_DET,
1079         BUS_PLL_CON0,
1080         BUS_PLL_CON1,
1081         BUS_PLL_FREQ_DET,
1082         MFC_PLL_CON0,
1083         MFC_PLL_CON1,
1084         MFC_PLL_FREQ_DET,
1085         MUX_SEL_MIF0,
1086         MUX_SEL_MIF1,
1087         MUX_SEL_MIF2,
1088         MUX_SEL_MIF3,
1089         MUX_SEL_MIF4,
1090         MUX_SEL_MIF5,
1091         MUX_SEL_MIF6,
1092         MUX_SEL_MIF7,
1093         MUX_ENABLE_MIF0,
1094         MUX_ENABLE_MIF1,
1095         MUX_ENABLE_MIF2,
1096         MUX_ENABLE_MIF3,
1097         MUX_ENABLE_MIF4,
1098         MUX_ENABLE_MIF5,
1099         MUX_ENABLE_MIF6,
1100         MUX_ENABLE_MIF7,
1101         DIV_MIF1,
1102         DIV_MIF2,
1103         DIV_MIF3,
1104         DIV_MIF4,
1105         DIV_MIF5,
1106         DIV_MIF_PLL_FREQ_DET,
1107         ENABLE_ACLK_MIF0,
1108         ENABLE_ACLK_MIF1,
1109         ENABLE_ACLK_MIF2,
1110         ENABLE_ACLK_MIF3,
1111         ENABLE_PCLK_MIF,
1112         ENABLE_PCLK_MIF_SECURE_DREX0_TZ,
1113         ENABLE_PCLK_MIF_SECURE_DREX1_TZ,
1114         ENABLE_PCLK_MIF_SECURE_MONOTONIC_CNT,
1115         ENABLE_PCLK_MIF_SECURE_RTC,
1116         ENABLE_SCLK_MIF,
1117         ENABLE_IP_MIF0,
1118         ENABLE_IP_MIF1,
1119         ENABLE_IP_MIF2,
1120         ENABLE_IP_MIF3,
1121         ENABLE_IP_MIF_SECURE_DREX0_TZ,
1122         ENABLE_IP_MIF_SECURE_DREX1_TZ,
1123         ENABLE_IP_MIF_SECURE_MONOTONIC_CNT,
1124         ENABLE_IP_MIF_SECURE_RTC,
1125         CLKOUT_CMU_MIF,
1126         CLKOUT_CMU_MIF_DIV_STAT,
1127         DREX_FREQ_CTRL0,
1128         DREX_FREQ_CTRL1,
1129         PAUSE,
1130         DDRPHY_LOCK_CTRL,
1131 };
1132
1133 static struct samsung_pll_clock mif_pll_clks[] __initdata = {
1134         PLL(pll_35xx, CLK_FOUT_MEM0_PLL, "fout_mem0_pll", "oscclk",
1135                 MEM0_PLL_LOCK, MEM0_PLL_CON0, exynos5443_pll_rates),
1136         PLL(pll_35xx, CLK_FOUT_MEM1_PLL, "fout_mem1_pll", "oscclk",
1137                 MEM1_PLL_LOCK, MEM1_PLL_CON0, exynos5443_pll_rates),
1138         PLL(pll_35xx, CLK_FOUT_BUS_PLL, "fout_bus_pll", "oscclk",
1139                 BUS_PLL_LOCK, BUS_PLL_CON0, exynos5443_pll_rates),
1140         PLL(pll_35xx, CLK_FOUT_MFC_PLL, "fout_mfc_pll", "oscclk",
1141                 MFC_PLL_LOCK, MFC_PLL_CON0, exynos5443_pll_rates),
1142 };
1143
1144 /* list of all parent clock list */
1145 PNAME(mout_mfc_pll_div2_p)      = { "mout_mfc_pll", "dout_mfc_pll", };
1146 PNAME(mout_bus_pll_div2_p)      = { "mout_bus_pll", "dout_bus_pll", };
1147 PNAME(mout_mem1_pll_div2_p)     = { "mout_mem1_pll", "dout_mem1_pll", };
1148 PNAME(mout_mem0_pll_div2_p)     = { "mout_mem0_pll", "dout_mem0_pll", };
1149 PNAME(mout_mfc_pll_p)           = { "oscclk", "fout_mfc_pll", };
1150 PNAME(mout_bus_pll_p)           = { "oscclk", "fout_bus_pll", };
1151 PNAME(mout_mem1_pll_p)          = { "oscclk", "fout_mem1_pll", };
1152 PNAME(mout_mem0_pll_p)          = { "oscclk", "fout_mem0_pll", };
1153
1154 PNAME(mout_clk2x_phy_c_p)       = { "mout_mem0_pll_div2", "mout_clkm_phy_b", };
1155 PNAME(mout_clk2x_phy_b_p)       = { "mout_bus_pll_div2", "mout_clkm_phy_a", };
1156 PNAME(mout_clk2x_phy_a_p)       = { "mout_bus_pll_div2", "mout_mfc_pll_div2", };
1157 PNAME(mout_clkm_phy_b_p)        = { "mout_mem1_pll_div2", "mout_clkm_phy_a", };
1158
1159 PNAME(mout_aclk_mifnm_200_p)    = { "mout_mem0_pll_div2", "div_mif_pre", };
1160 PNAME(mout_aclk_mifnm_400_p)    = { "mout_mem1_pll_div2", "mout_bus_pll_div2",};
1161
1162 PNAME(mout_aclk_disp_333_b_p)   = { "mout_aclk_disp_333_a",
1163                                     "mout_bus_pll_div2", };
1164 PNAME(mout_aclk_disp_333_a_p)   = { "mout_mfc_pll_div2", "sclk_mphy_pll", };
1165
1166 PNAME(mout_sclk_decon_vclk_c_p) = { "mout_sclk_decon_vclk_b",
1167                                     "sclk_mphy_pll", };
1168 PNAME(mout_sclk_decon_vclk_b_p) = { "mout_sclk_decon_vclk_a",
1169                                     "mout_mfc_pll_div2", };
1170 PNAME(mout_sclk_decon_p)        = { "oscclk", "mout_bus_pll_div2", };
1171 PNAME(mout_sclk_decon_eclk_c_p) = { "mout_sclk_decon_eclk_b",
1172                                     "sclk_mphy_pll", };
1173 PNAME(mout_sclk_decon_eclk_b_p) = { "mout_sclk_decon_eclk_a",
1174                                     "mout_mfc_pll_div2", };
1175
1176 PNAME(mout_sclk_decon_tv_eclk_c_p) = { "mout_sclk_decon_tv_eclk_b",
1177                                        "sclk_mphy_pll", };
1178 PNAME(mout_sclk_decon_tv_eclk_b_p) = { "mout_sclk_decon_tv_eclk_a",
1179                                        "mout_mfc_pll_div2", };
1180 PNAME(mout_sclk_dsd_c_p)        = { "mout_sclk_dsd_b", "mout_bus_pll_div2", };
1181 PNAME(mout_sclk_dsd_b_p)        = { "mout_sclk_dsd_a", "sclk_mphy_pll", };
1182 PNAME(mout_sclk_dsd_a_p)        = { "oscclk", "mout_mfc_pll_div2", };
1183
1184 PNAME(mout_sclk_dsim0_c_p)      = { "mout_sclk_dsim0_b", "sclk_mphy_pll", };
1185 PNAME(mout_sclk_dsim0_b_p)      = { "mout_sclk_dsim0_a", "mout_mfc_pll_div2" };
1186
1187 PNAME(mout_sclk_decon_tv_vclk_c_p) = { "mout_sclk_decon_tv_vclk_b",
1188                                        "sclk_mphy_pll", };
1189 PNAME(mout_sclk_decon_tv_vclk_b_p) = { "mout_sclk_decon_tv_vclk_a",
1190                                        "mout_mfc_pll_div2", };
1191 PNAME(mout_sclk_dsim1_c_p)      = { "mout_sclk_dsim1_b", "sclk_mphy_pll", };
1192 PNAME(mout_sclk_dsim1_b_p)      = { "mout_sclk_dsim1_a", "mout_mfc_pll_div2",};
1193
1194 static struct samsung_fixed_factor_clock mif_fixed_factor_clks[] __initdata = {
1195         /* dout_{mfc|bus|mem1|mem0}_pll is half fixed rate from parent mux */
1196         FFACTOR(CLK_DOUT_MFC_PLL, "dout_mfc_pll", "mout_mfc_pll", 1, 1, 0),
1197         FFACTOR(CLK_DOUT_BUS_PLL, "dout_bus_pll", "mout_bus_pll", 1, 1, 0),
1198         FFACTOR(CLK_DOUT_MEM1_PLL, "dout_mem1_pll", "mout_mem1_pll", 1, 1, 0),
1199         FFACTOR(CLK_DOUT_MEM0_PLL, "dout_mem0_pll", "mout_mem0_pll", 1, 1, 0),
1200 };
1201
1202 static struct samsung_mux_clock mif_mux_clks[] __initdata = {
1203         /* MUX_SEL_MIF0 */
1204         MUX(CLK_MOUT_MFC_PLL_DIV2, "mout_mfc_pll_div2", mout_mfc_pll_div2_p,
1205                         MUX_SEL_MIF0, 28, 1),
1206         MUX(CLK_MOUT_BUS_PLL_DIV2, "mout_bus_pll_div2", mout_bus_pll_div2_p,
1207                         MUX_SEL_MIF0, 24, 1),
1208         MUX(CLK_MOUT_MEM1_PLL_DIV2, "mout_mem1_pll_div2", mout_mem1_pll_div2_p,
1209                         MUX_SEL_MIF0, 20, 1),
1210         MUX(CLK_MOUT_MEM0_PLL_DIV2, "mout_mem0_pll_div2", mout_mem0_pll_div2_p,
1211                         MUX_SEL_MIF0, 16, 1),
1212         MUX(CLK_MOUT_MFC_PLL, "mout_mfc_pll", mout_mfc_pll_p, MUX_SEL_MIF0,
1213                         12, 1),
1214         MUX(CLK_MOUT_BUS_PLL, "mout_bus_pll", mout_bus_pll_p, MUX_SEL_MIF0,
1215                         8, 1),
1216         MUX(CLK_MOUT_MEM1_PLL, "mout_mem1_pll", mout_mem1_pll_p, MUX_SEL_MIF0,
1217                         4, 1),
1218         MUX(CLK_MOUT_MEM0_PLL, "mout_mem0_pll", mout_mem0_pll_p, MUX_SEL_MIF0,
1219                         0, 1),
1220
1221         /* MUX_SEL_MIF1 */
1222         MUX(CLK_MOUT_CLK2X_PHY_C, "mout_clk2x_phy_c", mout_clk2x_phy_c_p,
1223                         MUX_SEL_MIF1, 24, 1),
1224         MUX(CLK_MOUT_CLK2X_PHY_B, "mout_clk2x_phy_b", mout_clk2x_phy_b_p,
1225                         MUX_SEL_MIF1, 20, 1),
1226         MUX(CLK_MOUT_CLK2X_PHY_A, "mout_clk2x_phy_a", mout_clk2x_phy_a_p,
1227                         MUX_SEL_MIF1, 16, 1),
1228         MUX(CLK_MOUT_CLKM_PHY_C, "mout_clkm_phy_c", mout_clk2x_phy_c_p,
1229                         MUX_SEL_MIF1, 12, 1),
1230         MUX(CLK_MOUT_CLKM_PHY_B, "mout_clkm_phy_b", mout_clkm_phy_b_p,
1231                         MUX_SEL_MIF1, 8, 1),
1232         MUX(CLK_MOUT_CLKM_PHY_A, "mout_clkm_phy_a", mout_clk2x_phy_a_p,
1233                         MUX_SEL_MIF1, 4, 1),
1234
1235         /* MUX_SEL_MIF2 */
1236         MUX(CLK_MOUT_ACLK_MIFNM_200, "mout_aclk_mifnm_200",
1237                         mout_aclk_mifnm_200_p, MUX_SEL_MIF2, 8, 1),
1238         MUX(CLK_MOUT_ACLK_MIFNM_400, "mout_aclk_mifnm_400",
1239                         mout_aclk_mifnm_400_p, MUX_SEL_MIF2, 0, 1),
1240
1241         /* MUX_SEL_MIF3 */
1242         MUX(CLK_MOUT_ACLK_DISP_333_B, "mout_aclk_disp_333_b",
1243                         mout_aclk_disp_333_b_p, MUX_SEL_MIF3, 4, 1),
1244         MUX(CLK_MOUT_ACLK_DISP_333_A, "mout_aclk_disp_333_a",
1245                         mout_aclk_disp_333_a_p, MUX_SEL_MIF3, 0, 1),
1246
1247         /* MUX_SEL_MIF4 */
1248         MUX(CLK_MOUT_SCLK_DECON_VCLK_C, "mout_sclk_decon_vclk_c",
1249                         mout_sclk_decon_vclk_c_p, MUX_SEL_MIF4, 24, 1),
1250         MUX(CLK_MOUT_SCLK_DECON_VCLK_B, "mout_sclk_decon_vclk_b",
1251                         mout_sclk_decon_vclk_b_p, MUX_SEL_MIF4, 20, 1),
1252         MUX(CLK_MOUT_SCLK_DECON_VCLK_A, "mout_sclk_decon_vclk_a",
1253                         mout_sclk_decon_p, MUX_SEL_MIF4, 16, 1),
1254         MUX(CLK_MOUT_SCLK_DECON_ECLK_C, "mout_sclk_decon_eclk_c",
1255                         mout_sclk_decon_eclk_c_p, MUX_SEL_MIF4, 8, 1),
1256         MUX(CLK_MOUT_SCLK_DECON_ECLK_B, "mout_sclk_decon_eclk_b",
1257                         mout_sclk_decon_eclk_b_p, MUX_SEL_MIF4, 4, 1),
1258         MUX(CLK_MOUT_SCLK_DECON_ECLK_A, "mout_sclk_decon_eclk_a",
1259                         mout_sclk_decon_p, MUX_SEL_MIF4, 0, 1),
1260
1261         /* MUX_SEL_MIF5 */
1262         MUX(CLK_MOUT_SCLK_DECON_TV_ECLK_C, "mout_sclk_decon_tv_eclk_c",
1263                         mout_sclk_decon_tv_eclk_c_p, MUX_SEL_MIF5, 24, 1),
1264         MUX(CLK_MOUT_SCLK_DECON_TV_ECLK_B, "mout_sclk_decon_tv_eclk_b",
1265                         mout_sclk_decon_tv_eclk_b_p, MUX_SEL_MIF5, 20, 1),
1266         MUX(CLK_MOUT_SCLK_DECON_TV_ECLK_A, "mout_sclk_decon_tv_eclk_a",
1267                         mout_sclk_decon_p, MUX_SEL_MIF5, 16, 1),
1268         MUX(CLK_MOUT_SCLK_DSD_C, "mout_sclk_dsd_c", mout_sclk_dsd_c_p,
1269                         MUX_SEL_MIF5, 8, 1),
1270         MUX(CLK_MOUT_SCLK_DSD_B, "mout_sclk_dsd_b", mout_sclk_dsd_b_p,
1271                         MUX_SEL_MIF5, 4, 1),
1272         MUX(CLK_MOUT_SCLK_DSD_A, "mout_sclk_dsd_a", mout_sclk_dsd_a_p,
1273                         MUX_SEL_MIF5, 0, 1),
1274
1275         /* MUX_SEL_MIF6 */
1276         MUX(CLK_MOUT_SCLK_DSIM0_C, "mout_sclk_dsim0_c", mout_sclk_dsim0_c_p,
1277                         MUX_SEL_MIF6, 8, 1),
1278         MUX(CLK_MOUT_SCLK_DSIM0_B, "mout_sclk_dsim0_b", mout_sclk_dsim0_b_p,
1279                         MUX_SEL_MIF6, 4, 1),
1280         MUX(CLK_MOUT_SCLK_DSIM0_A, "mout_sclk_dsim0_a", mout_sclk_decon_p,
1281                         MUX_SEL_MIF6, 0, 1),
1282
1283         /* MUX_SEL_MIF7 */
1284         MUX(CLK_MOUT_SCLK_DECON_TV_VCLK_C, "mout_sclk_decon_tv_vclk_c",
1285                         mout_sclk_decon_tv_vclk_c_p, MUX_SEL_MIF7, 24, 1),
1286         MUX(CLK_MOUT_SCLK_DECON_TV_VCLK_B, "mout_sclk_decon_tv_vclk_b",
1287                         mout_sclk_decon_tv_vclk_b_p, MUX_SEL_MIF7, 20, 1),
1288         MUX(CLK_MOUT_SCLK_DECON_TV_VCLK_A, "mout_sclk_decon_tv_vclk_a",
1289                         mout_sclk_decon_p, MUX_SEL_MIF7, 16, 1),
1290         MUX(CLK_MOUT_SCLK_DSIM1_C, "mout_sclk_dsim1_c", mout_sclk_dsim1_c_p,
1291                         MUX_SEL_MIF7, 8, 1),
1292         MUX(CLK_MOUT_SCLK_DSIM1_B, "mout_sclk_dsim1_b", mout_sclk_dsim1_b_p,
1293                         MUX_SEL_MIF7, 4, 1),
1294         MUX(CLK_MOUT_SCLK_DSIM1_A, "mout_sclk_dsim1_a", mout_sclk_decon_p,
1295                         MUX_SEL_MIF7, 0, 1),
1296 };
1297
1298 static struct samsung_div_clock mif_div_clks[] __initdata = {
1299         /* DIV_MIF1 */
1300         DIV(CLK_DIV_SCLK_HPM_MIF, "div_sclk_hpm_mif", "div_clk2x_phy",
1301                         DIV_MIF1, 16, 2),
1302         DIV(CLK_DIV_ACLK_DREX1, "div_aclk_drex1", "div_clk2x_phy", DIV_MIF1,
1303                         12, 2),
1304         DIV(CLK_DIV_ACLK_DREX0, "div_aclk_drex0", "div_clk2x_phy", DIV_MIF1,
1305                         8, 2),
1306         DIV(CLK_DIV_CLK2XPHY, "div_clk2x_phy", "mout_clk2x_phy_c", DIV_MIF1,
1307                         4, 4),
1308
1309         /* DIV_MIF2 */
1310         DIV(CLK_DIV_ACLK_MIF_266, "div_aclk_mif_266", "mout_bus_pll_div2",
1311                         DIV_MIF2, 20, 3),
1312         DIV(CLK_DIV_ACLK_MIFND_133, "div_aclk_mifnd_133", "div_mif_pre",
1313                         DIV_MIF2, 16, 4),
1314         DIV(CLK_DIV_ACLK_MIF_133, "div_aclk_mif_133", "div_mif_pre",
1315                         DIV_MIF2, 12, 4),
1316         DIV(CLK_DIV_ACLK_MIFNM_200, "div_aclk_mifnm_200",
1317                         "mout_aclk_mifnm_200", DIV_MIF2, 8, 3),
1318         DIV(CLK_DIV_ACLK_MIF_200, "div_aclk_mif_200", "div_aclk_mif_400",
1319                         DIV_MIF2, 4, 2),
1320         DIV(CLK_DIV_ACLK_MIF_400, "div_aclk_mif_400", "mout_aclk_mifnm_400",
1321                         DIV_MIF2, 0, 3),
1322
1323         /* DIV_MIF3 */
1324         DIV(CLK_DIV_ACLK_BUS2_400, "div_aclk_bus2_400", "div_mif_pre",
1325                         DIV_MIF3, 16, 4),
1326         DIV(CLK_DIV_ACLK_DISP_333, "div_aclk_disp_333", "mout_aclk_disp_333_b",
1327                         DIV_MIF3, 4, 3),
1328         DIV(CLK_DIV_ACLK_CPIF_200, "div_aclk_cpif_200", "mout_aclk_mifnm_200",
1329                         DIV_MIF3, 0, 3),
1330
1331         /* DIV_MIF4 */
1332         DIV(CLK_DIV_SCLK_DSIM1, "div_sclk_dsim1", "mout_sclk_dsim1_c",
1333                         DIV_MIF4, 24, 4),
1334         DIV(CLK_DIV_SCLK_DECON_TV_VCLK, "div_sclk_decon_tv_vclk",
1335                         "mout_sclk_decon_tv_vclk_c", DIV_MIF4, 20, 4),
1336         DIV(CLK_DIV_SCLK_DSIM0, "div_sclk_dsim0", "mout_sclk_dsim0_c",
1337                         DIV_MIF4, 16, 4),
1338         DIV(CLK_DIV_SCLK_DSD, "div_sclk_dsd", "mout_sclk_dsd_c",
1339                         DIV_MIF4, 12, 4),
1340         DIV(CLK_DIV_SCLK_DECON_TV_ECLK, "div_sclk_decon_tv_eclk",
1341                         "mout_sclk_decon_tv_eclk_c", DIV_MIF4, 8, 4),
1342         DIV(CLK_DIV_SCLK_DECON_VCLK, "div_sclk_decon_vclk",
1343                         "mout_sclk_decon_vclk_c", DIV_MIF4, 4, 4),
1344         DIV(CLK_DIV_SCLK_DECON_ECLK, "div_sclk_decon_eclk",
1345                         "mout_sclk_decon_eclk_c", DIV_MIF4, 0, 4),
1346
1347         /* DIV_MIF5 */
1348         DIV(CLK_DIV_MIF_PRE, "div_mif_pre", "mout_bus_pll_div2", DIV_MIF5,
1349                         0, 3),
1350 };
1351
1352 static struct samsung_gate_clock mif_gate_clks[] __initdata = {
1353         /* ENABLE_ACLK_MIF0 */
1354         GATE(CLK_CLK2X_PHY1, "clk2k_phy1", "div_clk2x_phy", ENABLE_ACLK_MIF0,
1355                         19, CLK_IGNORE_UNUSED, 0),
1356         GATE(CLK_CLK2X_PHY0, "clk2x_phy0", "div_clk2x_phy", ENABLE_ACLK_MIF0,
1357                         18, CLK_IGNORE_UNUSED, 0),
1358         GATE(CLK_CLKM_PHY1, "clkm_phy1", "mout_clkm_phy_c", ENABLE_ACLK_MIF0,
1359                         17, CLK_IGNORE_UNUSED, 0),
1360         GATE(CLK_CLKM_PHY0, "clkm_phy0", "mout_clkm_phy_c", ENABLE_ACLK_MIF0,
1361                         16, CLK_IGNORE_UNUSED, 0),
1362         GATE(CLK_RCLK_DREX1, "rclk_drex1", "oscclk", ENABLE_ACLK_MIF0,
1363                         15, CLK_IGNORE_UNUSED, 0),
1364         GATE(CLK_RCLK_DREX0, "rclk_drex0", "oscclk", ENABLE_ACLK_MIF0,
1365                         14, CLK_IGNORE_UNUSED, 0),
1366         GATE(CLK_ACLK_DREX1_TZ, "aclk_drex1_tz", "div_aclk_drex1",
1367                         ENABLE_ACLK_MIF0, 13, CLK_IGNORE_UNUSED, 0),
1368         GATE(CLK_ACLK_DREX0_TZ, "aclk_drex0_tz", "div_aclk_drex0",
1369                         ENABLE_ACLK_MIF0, 12, CLK_IGNORE_UNUSED, 0),
1370         GATE(CLK_ACLK_DREX1_PEREV, "aclk_drex1_perev", "div_aclk_drex1",
1371                         ENABLE_ACLK_MIF0, 11, CLK_IGNORE_UNUSED, 0),
1372         GATE(CLK_ACLK_DREX0_PEREV, "aclk_drex0_perev", "div_aclk_drex0",
1373                         ENABLE_ACLK_MIF0, 10, CLK_IGNORE_UNUSED, 0),
1374         GATE(CLK_ACLK_DREX1_MEMIF, "aclk_drex1_memif", "div_aclk_drex1",
1375                         ENABLE_ACLK_MIF0, 9, CLK_IGNORE_UNUSED, 0),
1376         GATE(CLK_ACLK_DREX0_MEMIF, "aclk_drex0_memif", "div_aclk_drex0",
1377                         ENABLE_ACLK_MIF0, 8, CLK_IGNORE_UNUSED, 0),
1378         GATE(CLK_ACLK_DREX1_SCH, "aclk_drex1_sch", "div_aclk_drex1",
1379                         ENABLE_ACLK_MIF0, 7, CLK_IGNORE_UNUSED, 0),
1380         GATE(CLK_ACLK_DREX0_SCH, "aclk_drex0_sch", "div_aclk_drex0",
1381                         ENABLE_ACLK_MIF0, 6, CLK_IGNORE_UNUSED, 0),
1382         GATE(CLK_ACLK_DREX1_BUSIF, "aclk_drex1_busif", "div_aclk_drex1",
1383                         ENABLE_ACLK_MIF0, 5, CLK_IGNORE_UNUSED, 0),
1384         GATE(CLK_ACLK_DREX0_BUSIF, "aclk_drex0_busif", "div_aclk_drex0",
1385                         ENABLE_ACLK_MIF0, 4, CLK_IGNORE_UNUSED, 0),
1386         GATE(CLK_ACLK_DREX1_BUSIF_RD, "aclk_drex1_busif_rd", "div_aclk_drex1",
1387                         ENABLE_ACLK_MIF0, 3, CLK_IGNORE_UNUSED, 0),
1388         GATE(CLK_ACLK_DREX0_BUSIF_RD, "aclk_drex0_busif_rd", "div_aclk_drex0",
1389                         ENABLE_ACLK_MIF0, 2, CLK_IGNORE_UNUSED, 0),
1390         GATE(CLK_ACLK_DREX1, "aclk_drex1", "div_aclk_drex1",
1391                         ENABLE_ACLK_MIF0, 2, CLK_IGNORE_UNUSED, 0),
1392         GATE(CLK_ACLK_DREX0, "aclk_drex0", "div_aclk_drex0",
1393                         ENABLE_ACLK_MIF0, 1, CLK_IGNORE_UNUSED, 0),
1394
1395         /* ENABLE_ACLK_MIF1 */
1396         GATE(CLK_ACLK_ASYNCAXIS_MIF_IMEM, "aclk_asyncaxis_mif_imem",
1397                         "div_aclk_mif_200", ENABLE_ACLK_MIF1, 28,
1398                         CLK_IGNORE_UNUSED, 0),
1399         GATE(CLK_ACLK_ASYNCAXIS_NOC_P_CCI, "aclk_asyncaxis_noc_p_cci",
1400                         "div_aclk_mif_200", ENABLE_ACLK_MIF1,
1401                         27, CLK_IGNORE_UNUSED, 0),
1402         GATE(CLK_ACLK_ASYNCAXIM_NOC_P_CCI, "aclk_asyncaxim_noc_p_cci",
1403                         "div_aclk_mif_133", ENABLE_ACLK_MIF1,
1404                         26, CLK_IGNORE_UNUSED, 0),
1405         GATE(CLK_ACLK_ASYNCAXIS_CP1, "aclk_asyncaxis_cp1",
1406                         "div_aclk_mifnm_200", ENABLE_ACLK_MIF1,
1407                         25, CLK_IGNORE_UNUSED, 0),
1408         GATE(CLK_ACLK_ASYNCAXIM_CP1, "aclk_asyncaxim_cp1",
1409                         "div_aclk_drex1", ENABLE_ACLK_MIF1,
1410                         24, CLK_IGNORE_UNUSED, 0),
1411         GATE(CLK_ACLK_ASYNCAXIS_CP0, "aclk_asyncaxis_cp0",
1412                         "div_aclk_mifnm_200", ENABLE_ACLK_MIF1,
1413                         23, CLK_IGNORE_UNUSED, 0),
1414         GATE(CLK_ACLK_ASYNCAXIM_CP0, "aclk_asyncaxim_cp0",
1415                         "div_aclk_drex0", ENABLE_ACLK_MIF1,
1416                         22, CLK_IGNORE_UNUSED, 0),
1417         GATE(CLK_ACLK_ASYNCAXIS_DREX1_3, "aclk_asyncaxis_drex1_3",
1418                         "div_aclk_mif_133", ENABLE_ACLK_MIF1,
1419                         21, CLK_IGNORE_UNUSED, 0),
1420         GATE(CLK_ACLK_ASYNCAXIM_DREX1_3, "aclk_asyncaxim_drex1_3",
1421                         "div_aclk_drex1", ENABLE_ACLK_MIF1,
1422                         20, CLK_IGNORE_UNUSED, 0),
1423         GATE(CLK_ACLK_ASYNCAXIS_DREX1_1, "aclk_asyncaxis_drex1_1",
1424                         "div_aclk_mif_133", ENABLE_ACLK_MIF1,
1425                         19, CLK_IGNORE_UNUSED, 0),
1426         GATE(CLK_ACLK_ASYNCAXIM_DREX1_1, "aclk_asyncaxim_drex1_1",
1427                         "div_aclk_drex1", ENABLE_ACLK_MIF1,
1428                         18, CLK_IGNORE_UNUSED, 0),
1429         GATE(CLK_ACLK_ASYNCAXIS_DREX1_0, "aclk_asyncaxis_drex1_0",
1430                         "div_aclk_mif_133", ENABLE_ACLK_MIF1,
1431                         17, CLK_IGNORE_UNUSED, 0),
1432         GATE(CLK_ACLK_ASYNCAXIM_DREX1_0, "aclk_asyncaxim_drex1_0",
1433                         "div_aclk_drex1", ENABLE_ACLK_MIF1,
1434                         16, CLK_IGNORE_UNUSED, 0),
1435         GATE(CLK_ACLK_ASYNCAXIS_DREX0_3, "aclk_asyncaxis_drex0_3",
1436                         "div_aclk_mif_133", ENABLE_ACLK_MIF1,
1437                         15, CLK_IGNORE_UNUSED, 0),
1438         GATE(CLK_ACLK_ASYNCAXIM_DREX0_3, "aclk_asyncaxim_drex0_3",
1439                         "div_aclk_drex0", ENABLE_ACLK_MIF1,
1440                         14, CLK_IGNORE_UNUSED, 0),
1441         GATE(CLK_ACLK_ASYNCAXIS_DREX0_1, "aclk_asyncaxis_drex0_1",
1442                         "div_aclk_mif_133", ENABLE_ACLK_MIF1,
1443                         13, CLK_IGNORE_UNUSED, 0),
1444         GATE(CLK_ACLK_ASYNCAXIM_DREX0_1, "aclk_asyncaxim_drex0_1",
1445                         "div_aclk_drex0", ENABLE_ACLK_MIF1,
1446                         12, CLK_IGNORE_UNUSED, 0),
1447         GATE(CLK_ACLK_ASYNCAXIS_DREX0_0, "aclk_asyncaxis_drex0_0",
1448                         "div_aclk_mif_133", ENABLE_ACLK_MIF1,
1449                         11, CLK_IGNORE_UNUSED, 0),
1450         GATE(CLK_ACLK_ASYNCAXIM_DREX0_0, "aclk_asyncaxim_drex0_0",
1451                         "div_aclk_drex0", ENABLE_ACLK_MIF1,
1452                         10, CLK_IGNORE_UNUSED, 0),
1453         GATE(CLK_ACLK_AHB2APB_MIF2P, "aclk_ahb2apb_mif2p", "div_aclk_mif_133",
1454                         ENABLE_ACLK_MIF1, 9, CLK_IGNORE_UNUSED, 0),
1455         GATE(CLK_ACLK_AHB2APB_MIF1P, "aclk_ahb2apb_mif1p", "div_aclk_mif_133",
1456                         ENABLE_ACLK_MIF1, 8, CLK_IGNORE_UNUSED, 0),
1457         GATE(CLK_ACLK_AHB2APB_MIF0P, "aclk_ahb2apb_mif0p", "div_aclk_mif_133",
1458                         ENABLE_ACLK_MIF1, 7, CLK_IGNORE_UNUSED, 0),
1459         GATE(CLK_ACLK_IXIU_CCI, "aclk_ixiu_cci", "div_aclk_mif_400",
1460                         ENABLE_ACLK_MIF1, 6, CLK_IGNORE_UNUSED, 0),
1461         GATE(CLK_ACLK_XIU_MIFSFRX, "aclk_xiu_mifsfrx", "div_aclk_mif_200",
1462                         ENABLE_ACLK_MIF1, 5, CLK_IGNORE_UNUSED, 0),
1463         GATE(CLK_ACLK_MIFNP_133, "aclk_mifnp_133", "div_aclk_mif_133",
1464                         ENABLE_ACLK_MIF1, 4, CLK_IGNORE_UNUSED, 0),
1465         GATE(CLK_ACLK_MIFNM_200, "aclk_mifnm_200", "div_aclk_mifnm_200",
1466                         ENABLE_ACLK_MIF1, 3, CLK_IGNORE_UNUSED, 0),
1467         GATE(CLK_ACLK_MIFND_133, "aclk_mifnd_133", "div_aclk_mifnd_133",
1468                         ENABLE_ACLK_MIF1, 2, CLK_IGNORE_UNUSED, 0),
1469         GATE(CLK_ACLK_MIFND_400, "aclk_mifnd_400", "div_aclk_mif_400",
1470                         ENABLE_ACLK_MIF1, 1, CLK_IGNORE_UNUSED, 0),
1471         GATE(CLK_ACLK_CCI, "aclk_cci", "div_aclk_mif_400", ENABLE_ACLK_MIF1,
1472                         0, CLK_IGNORE_UNUSED, 0),
1473
1474         /* ENABLE_ACLK_MIF2 */
1475         GATE(CLK_ACLK_MIFND_266, "aclk_mifnd_266", "div_aclk_mif_266",
1476                         ENABLE_ACLK_MIF2, 20, CLK_IGNORE_UNUSED, 0),
1477         GATE(CLK_ACLK_PPMU_DREX1S3, "aclk_ppmu_drex1s3", "div_aclk_drex1",
1478                         ENABLE_ACLK_MIF2, 17, CLK_IGNORE_UNUSED, 0),
1479         GATE(CLK_ACLK_PPMU_DREX1S1, "aclk_ppmu_drex1s1", "div_aclk_drex1",
1480                         ENABLE_ACLK_MIF2, 16, CLK_IGNORE_UNUSED, 0),
1481         GATE(CLK_ACLK_PPMU_DREX1S0, "aclk_ppmu_drex1s0", "div_aclk_drex1",
1482                         ENABLE_ACLK_MIF2, 15, CLK_IGNORE_UNUSED, 0),
1483         GATE(CLK_ACLK_PPMU_DREX0S3, "aclk_ppmu_drex0s3", "div_aclk_drex0",
1484                         ENABLE_ACLK_MIF2, 14, CLK_IGNORE_UNUSED, 0),
1485         GATE(CLK_ACLK_PPMU_DREX0S1, "aclk_ppmu_drex0s1", "div_aclk_drex0",
1486                         ENABLE_ACLK_MIF2, 13, CLK_IGNORE_UNUSED, 0),
1487         GATE(CLK_ACLK_PPMU_DREX0S0, "aclk_ppmu_drex0s0", "div_aclk_drex0",
1488                         ENABLE_ACLK_MIF2, 12, CLK_IGNORE_UNUSED, 0),
1489         GATE(CLK_ACLK_AXIDS_CCI_MIFSFRX, "aclk_axids_cci_mifsfrx",
1490                         "div_aclk_mif_200", ENABLE_ACLK_MIF2, 7,
1491                         CLK_IGNORE_UNUSED, 0),
1492         GATE(CLK_ACLK_AXISYNCDNS_CCI, "aclk_axisyncdns_cci",
1493                         "div_aclk_mif_400", ENABLE_ACLK_MIF2,
1494                         5, CLK_IGNORE_UNUSED, 0),
1495         GATE(CLK_ACLK_AXISYNCDN_CCI, "aclk_axisyncdn_cci", "div_aclk_mif_400",
1496                         ENABLE_ACLK_MIF2, 4, CLK_IGNORE_UNUSED, 0),
1497         GATE(CLK_ACLK_AXISYNCDN_NOC_D, "aclk_axisyncdn_noc_d",
1498                         "div_aclk_mif_200", ENABLE_ACLK_MIF2,
1499                         3, CLK_IGNORE_UNUSED, 0),
1500         GATE(CLK_ACLK_ASYNCAPBS_MIF_CSSYS, "aclk_asyncapbs_mif_cssys",
1501                         "div_aclk_mifnd_133", ENABLE_ACLK_MIF2, 0, 0, 0),
1502
1503         /* ENABLE_ACLK_MIF3 */
1504         GATE(CLK_ACLK_BUS2_400, "aclk_bus2_400", "div_aclk_bus2_400",
1505                         ENABLE_ACLK_MIF3, 4,
1506                         CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
1507         GATE(CLK_ACLK_DISP_333, "aclk_disp_333", "div_aclk_disp_333",
1508                         ENABLE_ACLK_MIF3, 1,
1509                         CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
1510         GATE(CLK_ACLK_CPIF_200, "aclk_cpif_200", "div_aclk_cpif_200",
1511                         ENABLE_ACLK_MIF3, 0,
1512                         CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
1513
1514         /* ENABLE_PCLK_MIF */
1515         GATE(CLK_PCLK_PPMU_DREX1S3, "pclk_ppmu_drex1s3", "div_aclk_drex1",
1516                         ENABLE_PCLK_MIF, 29, CLK_IGNORE_UNUSED, 0),
1517         GATE(CLK_PCLK_PPMU_DREX1S1, "pclk_ppmu_drex1s1", "div_aclk_drex1",
1518                         ENABLE_PCLK_MIF, 28, CLK_IGNORE_UNUSED, 0),
1519         GATE(CLK_PCLK_PPMU_DREX1S0, "pclk_ppmu_drex1s0", "div_aclk_drex1",
1520                         ENABLE_PCLK_MIF, 27, CLK_IGNORE_UNUSED, 0),
1521         GATE(CLK_PCLK_PPMU_DREX0S3, "pclk_ppmu_drex0s3", "div_aclk_drex0",
1522                         ENABLE_PCLK_MIF, 26, CLK_IGNORE_UNUSED, 0),
1523         GATE(CLK_PCLK_PPMU_DREX0S1, "pclk_ppmu_drex0s1", "div_aclk_drex0",
1524                         ENABLE_PCLK_MIF, 25, CLK_IGNORE_UNUSED, 0),
1525         GATE(CLK_PCLK_PPMU_DREX0S0, "pclk_ppmu_drex0s0", "div_aclk_drex0",
1526                         ENABLE_PCLK_MIF, 24, CLK_IGNORE_UNUSED, 0),
1527         GATE(CLK_PCLK_ASYNCAXI_NOC_P_CCI, "pclk_asyncaxi_noc_p_cci",
1528                         "div_aclk_mif_133", ENABLE_PCLK_MIF, 21,
1529                         CLK_IGNORE_UNUSED, 0),
1530
1531         GATE(CLK_PCLK_ASYNCAXI_CP1, "pclk_asyncaxi_cp1", "div_aclk_mif_133",
1532                         ENABLE_PCLK_MIF, 19, 0, 0),
1533         GATE(CLK_PCLK_ASYNCAXI_CP0, "pclk_asyncaxi_cp0", "div_aclk_mif_133",
1534                         ENABLE_PCLK_MIF, 18, 0, 0),
1535         GATE(CLK_PCLK_ASYNCAXI_DREX1_3, "pclk_asyncaxi_drex1_3",
1536                         "div_aclk_mif_133", ENABLE_PCLK_MIF, 17, 0, 0),
1537         GATE(CLK_PCLK_ASYNCAXI_DREX1_1, "pclk_asyncaxi_drex1_1",
1538                         "div_aclk_mif_133", ENABLE_PCLK_MIF, 16, 0, 0),
1539         GATE(CLK_PCLK_ASYNCAXI_DREX1_0, "pclk_asyncaxi_drex1_0",
1540                         "div_aclk_mif_133", ENABLE_PCLK_MIF, 15, 0, 0),
1541         GATE(CLK_PCLK_ASYNCAXI_DREX0_3, "pclk_asyncaxi_drex0_3",
1542                         "div_aclk_mif_133", ENABLE_PCLK_MIF, 14, 0, 0),
1543         GATE(CLK_PCLK_ASYNCAXI_DREX0_1, "pclk_asyncaxi_drex0_1",
1544                         "div_aclk_mif_133", ENABLE_PCLK_MIF, 13, 0, 0),
1545         GATE(CLK_PCLK_ASYNCAXI_DREX0_0, "pclk_asyncaxi_drex0_0",
1546                         "div_aclk_mif_133", ENABLE_PCLK_MIF, 12, 0, 0),
1547         GATE(CLK_PCLK_MIFSRVND_133, "pclk_mifsrvnd_133", "div_aclk_mif_133",
1548                         ENABLE_PCLK_MIF, 11, 0, 0),
1549         GATE(CLK_PCLK_PMU_MIF, "pclk_pmu_mif", "div_aclk_mif_133",
1550                         ENABLE_PCLK_MIF, 10, CLK_IGNORE_UNUSED, 0),
1551         GATE(CLK_PCLK_SYSREG_MIF, "pclk_sysreg_mif", "div_aclk_mif_133",
1552                         ENABLE_PCLK_MIF, 9, CLK_IGNORE_UNUSED, 0),
1553         GATE(CLK_PCLK_GPIO_ALIVE, "pclk_gpio_alive", "div_aclk_mif_133",
1554                         ENABLE_PCLK_MIF, 8, CLK_IGNORE_UNUSED, 0),
1555         GATE(CLK_PCLK_ABB, "pclk_abb", "div_aclk_mif_133",
1556                         ENABLE_PCLK_MIF, 7, 0, 0),
1557         GATE(CLK_PCLK_PMU_APBIF, "pclk_pmu_apbif", "div_aclk_mif_133",
1558                         ENABLE_PCLK_MIF, 6, CLK_IGNORE_UNUSED, 0),
1559         GATE(CLK_PCLK_DDR_PHY1, "pclk_ddr_phy1", "div_aclk_mif_133",
1560                         ENABLE_PCLK_MIF, 5, 0, 0),
1561         GATE(CLK_PCLK_DREX1, "pclk_drex1", "div_aclk_mif_133",
1562                         ENABLE_PCLK_MIF, 3, CLK_IGNORE_UNUSED, 0),
1563         GATE(CLK_PCLK_DDR_PHY0, "pclk_ddr_phy0", "div_aclk_mif_133",
1564                         ENABLE_PCLK_MIF, 2, 0, 0),
1565         GATE(CLK_PCLK_DREX0, "pclk_drex0", "div_aclk_mif_133",
1566                         ENABLE_PCLK_MIF, 0, CLK_IGNORE_UNUSED, 0),
1567
1568         /* ENABLE_PCLK_MIF_SECURE_DREX0_TZ */
1569         GATE(CLK_PCLK_DREX0_TZ, "pclk_drex0_tz", "div_aclk_mif_133",
1570                 ENABLE_PCLK_MIF_SECURE_DREX0_TZ, 0, CLK_IGNORE_UNUSED, 0),
1571
1572         /* ENABLE_PCLK_MIF_SECURE_DREX1_TZ */
1573         GATE(CLK_PCLK_DREX1_TZ, "pclk_drex1_tz", "div_aclk_mif_133",
1574                 ENABLE_PCLK_MIF_SECURE_DREX1_TZ, 0, CLK_IGNORE_UNUSED, 0),
1575
1576         /* ENABLE_PCLK_MIF_SECURE_MONOTONIC_CNT */
1577         GATE(CLK_PCLK_MONOTONIC_CNT, "pclk_monotonic_cnt", "div_aclk_mif_133",
1578                         ENABLE_PCLK_MIF_SECURE_MONOTONIC_CNT, 0, 0, 0),
1579
1580         /* ENABLE_PCLK_MIF_SECURE_RTC */
1581         GATE(CLK_PCLK_RTC, "pclk_rtc", "div_aclk_mif_133",
1582                         ENABLE_PCLK_MIF_SECURE_RTC, 0, 0, 0),
1583
1584         /* ENABLE_SCLK_MIF */
1585         GATE(CLK_SCLK_DSIM1_DISP, "sclk_dsim1_disp", "div_sclk_dsim1",
1586                         ENABLE_SCLK_MIF, 15, CLK_IGNORE_UNUSED, 0),
1587         GATE(CLK_SCLK_DECON_TV_VCLK_DISP, "sclk_decon_tv_vclk_disp",
1588                         "div_sclk_decon_tv_vclk", ENABLE_SCLK_MIF,
1589                         14, CLK_IGNORE_UNUSED, 0),
1590         GATE(CLK_SCLK_DSIM0_DISP, "sclk_dsim0_disp", "div_sclk_dsim0",
1591                         ENABLE_SCLK_MIF, 9, CLK_IGNORE_UNUSED, 0),
1592         GATE(CLK_SCLK_DSD_DISP, "sclk_dsd_disp", "div_sclk_dsd",
1593                         ENABLE_SCLK_MIF, 8, CLK_IGNORE_UNUSED, 0),
1594         GATE(CLK_SCLK_DECON_TV_ECLK_DISP, "sclk_decon_tv_eclk_disp",
1595                         "div_sclk_decon_tv_eclk", ENABLE_SCLK_MIF,
1596                         7, CLK_IGNORE_UNUSED, 0),
1597         GATE(CLK_SCLK_DECON_VCLK_DISP, "sclk_decon_vclk_disp",
1598                         "div_sclk_decon_vclk", ENABLE_SCLK_MIF,
1599                         6, CLK_IGNORE_UNUSED, 0),
1600         GATE(CLK_SCLK_DECON_ECLK_DISP, "sclk_decon_eclk_disp",
1601                         "div_sclk_decon_eclk", ENABLE_SCLK_MIF,
1602                         5, CLK_IGNORE_UNUSED, 0),
1603         GATE(CLK_SCLK_HPM_MIF, "sclk_hpm_mif", "div_sclk_hpm_mif",
1604                         ENABLE_SCLK_MIF, 4,
1605                         CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
1606         GATE(CLK_SCLK_MFC_PLL, "sclk_mfc_pll", "mout_mfc_pll_div2",
1607                         ENABLE_SCLK_MIF, 3, CLK_IGNORE_UNUSED, 0),
1608         GATE(CLK_SCLK_BUS_PLL, "sclk_bus_pll", "mout_bus_pll_div2",
1609                         ENABLE_SCLK_MIF, 2, CLK_IGNORE_UNUSED, 0),
1610         GATE(CLK_SCLK_BUS_PLL_APOLLO, "sclk_bus_pll_apollo", "sclk_bus_pll",
1611                         ENABLE_SCLK_MIF, 1, CLK_IGNORE_UNUSED, 0),
1612         GATE(CLK_SCLK_BUS_PLL_ATLAS, "sclk_bus_pll_atlas", "sclk_bus_pll",
1613                         ENABLE_SCLK_MIF, 0, CLK_IGNORE_UNUSED, 0),
1614 };
1615
1616 static struct samsung_cmu_info mif_cmu_info __initdata = {
1617         .pll_clks               = mif_pll_clks,
1618         .nr_pll_clks            = ARRAY_SIZE(mif_pll_clks),
1619         .mux_clks               = mif_mux_clks,
1620         .nr_mux_clks            = ARRAY_SIZE(mif_mux_clks),
1621         .div_clks               = mif_div_clks,
1622         .nr_div_clks            = ARRAY_SIZE(mif_div_clks),
1623         .gate_clks              = mif_gate_clks,
1624         .nr_gate_clks           = ARRAY_SIZE(mif_gate_clks),
1625         .fixed_factor_clks      = mif_fixed_factor_clks,
1626         .nr_fixed_factor_clks   = ARRAY_SIZE(mif_fixed_factor_clks),
1627         .nr_clk_ids             = MIF_NR_CLK,
1628         .clk_regs               = mif_clk_regs,
1629         .nr_clk_regs            = ARRAY_SIZE(mif_clk_regs),
1630 };
1631
1632 static void __init exynos5433_cmu_mif_init(struct device_node *np)
1633 {
1634         samsung_cmu_register_one(np, &mif_cmu_info);
1635 }
1636 CLK_OF_DECLARE(exynos5433_cmu_mif, "samsung,exynos5433-cmu-mif",
1637                 exynos5433_cmu_mif_init);
1638
1639 /*
1640  * Register offset definitions for CMU_PERIC
1641  */
1642 #define DIV_PERIC                       0x0600
1643 #define DIV_STAT_PERIC                  0x0700
1644 #define ENABLE_ACLK_PERIC               0x0800
1645 #define ENABLE_PCLK_PERIC0              0x0900
1646 #define ENABLE_PCLK_PERIC1              0x0904
1647 #define ENABLE_SCLK_PERIC               0x0A00
1648 #define ENABLE_IP_PERIC0                0x0B00
1649 #define ENABLE_IP_PERIC1                0x0B04
1650 #define ENABLE_IP_PERIC2                0x0B08
1651
1652 static unsigned long peric_clk_regs[] __initdata = {
1653         DIV_PERIC,
1654         ENABLE_ACLK_PERIC,
1655         ENABLE_PCLK_PERIC0,
1656         ENABLE_PCLK_PERIC1,
1657         ENABLE_SCLK_PERIC,
1658         ENABLE_IP_PERIC0,
1659         ENABLE_IP_PERIC1,
1660         ENABLE_IP_PERIC2,
1661 };
1662
1663 static struct samsung_div_clock peric_div_clks[] __initdata = {
1664         /* DIV_PERIC */
1665         DIV(CLK_DIV_SCLK_SCI, "div_sclk_sci", "oscclk", DIV_PERIC, 4, 4),
1666         DIV(CLK_DIV_SCLK_SC_IN, "div_sclk_sc_in", "oscclk", DIV_PERIC, 0, 4),
1667 };
1668
1669 static struct samsung_gate_clock peric_gate_clks[] __initdata = {
1670         /* ENABLE_ACLK_PERIC */
1671         GATE(CLK_ACLK_AHB2APB_PERIC2P, "aclk_ahb2apb_peric2p", "aclk_peric_66",
1672                         ENABLE_ACLK_PERIC, 3, CLK_IGNORE_UNUSED, 0),
1673         GATE(CLK_ACLK_AHB2APB_PERIC1P, "aclk_ahb2apb_peric1p", "aclk_peric_66",
1674                         ENABLE_ACLK_PERIC, 2, CLK_IGNORE_UNUSED, 0),
1675         GATE(CLK_ACLK_AHB2APB_PERIC0P, "aclk_ahb2apb_peric0p", "aclk_peric_66",
1676                         ENABLE_ACLK_PERIC, 1, CLK_IGNORE_UNUSED, 0),
1677         GATE(CLK_ACLK_PERICNP_66, "aclk_pericnp_66", "aclk_peric_66",
1678                         ENABLE_ACLK_PERIC, 0, CLK_IGNORE_UNUSED, 0),
1679
1680         /* ENABLE_PCLK_PERIC0 */
1681         GATE(CLK_PCLK_SCI, "pclk_sci", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1682                         31, CLK_SET_RATE_PARENT, 0),
1683         GATE(CLK_PCLK_GPIO_FINGER, "pclk_gpio_finger", "aclk_peric_66",
1684                         ENABLE_PCLK_PERIC0, 30, CLK_IGNORE_UNUSED, 0),
1685         GATE(CLK_PCLK_GPIO_ESE, "pclk_gpio_ese", "aclk_peric_66",
1686                         ENABLE_PCLK_PERIC0, 29, CLK_IGNORE_UNUSED, 0),
1687         GATE(CLK_PCLK_PWM, "pclk_pwm", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1688                         28, CLK_SET_RATE_PARENT, 0),
1689         GATE(CLK_PCLK_SPDIF, "pclk_spdif", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1690                         26, CLK_SET_RATE_PARENT, 0),
1691         GATE(CLK_PCLK_PCM1, "pclk_pcm1", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1692                         25, CLK_SET_RATE_PARENT, 0),
1693         GATE(CLK_PCLK_I2S1, "pclk_i2s", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1694                         24, CLK_SET_RATE_PARENT, 0),
1695         GATE(CLK_PCLK_SPI2, "pclk_spi2", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1696                         23, CLK_SET_RATE_PARENT, 0),
1697         GATE(CLK_PCLK_SPI1, "pclk_spi1", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1698                         22, CLK_SET_RATE_PARENT, 0),
1699         GATE(CLK_PCLK_SPI0, "pclk_spi0", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1700                         21, CLK_SET_RATE_PARENT, 0),
1701         GATE(CLK_PCLK_ADCIF, "pclk_adcif", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1702                         20, CLK_SET_RATE_PARENT, 0),
1703         GATE(CLK_PCLK_GPIO_TOUCH, "pclk_gpio_touch", "aclk_peric_66",
1704                         ENABLE_PCLK_PERIC0, 19, CLK_IGNORE_UNUSED, 0),
1705         GATE(CLK_PCLK_GPIO_NFC, "pclk_gpio_nfc", "aclk_peric_66",
1706                         ENABLE_PCLK_PERIC0, 18, CLK_IGNORE_UNUSED, 0),
1707         GATE(CLK_PCLK_GPIO_PERIC, "pclk_gpio_peric", "aclk_peric_66",
1708                         ENABLE_PCLK_PERIC0, 17, CLK_IGNORE_UNUSED, 0),
1709         GATE(CLK_PCLK_PMU_PERIC, "pclk_pmu_peric", "aclk_peric_66",
1710                         ENABLE_PCLK_PERIC0, 16, CLK_SET_RATE_PARENT, 0),
1711         GATE(CLK_PCLK_SYSREG_PERIC, "pclk_sysreg_peric", "aclk_peric_66",
1712                         ENABLE_PCLK_PERIC0, 15,
1713                         CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
1714         GATE(CLK_PCLK_UART2, "pclk_uart2", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1715                         14, CLK_SET_RATE_PARENT, 0),
1716         GATE(CLK_PCLK_UART1, "pclk_uart1", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1717                         13, CLK_SET_RATE_PARENT, 0),
1718         GATE(CLK_PCLK_UART0, "pclk_uart0", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1719                         12, CLK_SET_RATE_PARENT, 0),
1720         GATE(CLK_PCLK_HSI2C3, "pclk_hsi2c3", "aclk_peric_66",
1721                         ENABLE_PCLK_PERIC0, 11, CLK_SET_RATE_PARENT, 0),
1722         GATE(CLK_PCLK_HSI2C2, "pclk_hsi2c2", "aclk_peric_66",
1723                         ENABLE_PCLK_PERIC0, 10, CLK_SET_RATE_PARENT, 0),
1724         GATE(CLK_PCLK_HSI2C1, "pclk_hsi2c1", "aclk_peric_66",
1725                         ENABLE_PCLK_PERIC0, 9, CLK_SET_RATE_PARENT, 0),
1726         GATE(CLK_PCLK_HSI2C0, "pclk_hsi2c0", "aclk_peric_66",
1727                         ENABLE_PCLK_PERIC0, 8, CLK_SET_RATE_PARENT, 0),
1728         GATE(CLK_PCLK_I2C7, "pclk_i2c7", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1729                         7, CLK_SET_RATE_PARENT, 0),
1730         GATE(CLK_PCLK_I2C6, "pclk_i2c6", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1731                         6, CLK_SET_RATE_PARENT, 0),
1732         GATE(CLK_PCLK_I2C5, "pclk_i2c5", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1733                         5, CLK_SET_RATE_PARENT, 0),
1734         GATE(CLK_PCLK_I2C4, "pclk_i2c4", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1735                         4, CLK_SET_RATE_PARENT, 0),
1736         GATE(CLK_PCLK_I2C3, "pclk_i2c3", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1737                         3, CLK_SET_RATE_PARENT, 0),
1738         GATE(CLK_PCLK_I2C2, "pclk_i2c2", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1739                         2, CLK_SET_RATE_PARENT, 0),
1740         GATE(CLK_PCLK_I2C1, "pclk_i2c1", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1741                         1, CLK_SET_RATE_PARENT, 0),
1742         GATE(CLK_PCLK_I2C0, "pclk_i2c0", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1743                         0, CLK_SET_RATE_PARENT, 0),
1744
1745         /* ENABLE_PCLK_PERIC1 */
1746         GATE(CLK_PCLK_SPI4, "pclk_spi4", "aclk_peric_66", ENABLE_PCLK_PERIC1,
1747                         9, CLK_SET_RATE_PARENT, 0),
1748         GATE(CLK_PCLK_SPI3, "pclk_spi3", "aclk_peric_66", ENABLE_PCLK_PERIC1,
1749                         8, CLK_SET_RATE_PARENT, 0),
1750         GATE(CLK_PCLK_HSI2C11, "pclk_hsi2c11", "aclk_peric_66",
1751                         ENABLE_PCLK_PERIC1, 7, CLK_SET_RATE_PARENT, 0),
1752         GATE(CLK_PCLK_HSI2C10, "pclk_hsi2c10", "aclk_peric_66",
1753                         ENABLE_PCLK_PERIC1, 6, CLK_SET_RATE_PARENT, 0),
1754         GATE(CLK_PCLK_HSI2C9, "pclk_hsi2c9", "aclk_peric_66",
1755                         ENABLE_PCLK_PERIC1, 5, CLK_SET_RATE_PARENT, 0),
1756         GATE(CLK_PCLK_HSI2C8, "pclk_hsi2c8", "aclk_peric_66",
1757                         ENABLE_PCLK_PERIC1, 4, CLK_SET_RATE_PARENT, 0),
1758         GATE(CLK_PCLK_HSI2C7, "pclk_hsi2c7", "aclk_peric_66",
1759                         ENABLE_PCLK_PERIC1, 3, CLK_SET_RATE_PARENT, 0),
1760         GATE(CLK_PCLK_HSI2C6, "pclk_hsi2c6", "aclk_peric_66",
1761                         ENABLE_PCLK_PERIC1, 2, CLK_SET_RATE_PARENT, 0),
1762         GATE(CLK_PCLK_HSI2C5, "pclk_hsi2c5", "aclk_peric_66",
1763                         ENABLE_PCLK_PERIC1, 1, CLK_SET_RATE_PARENT, 0),
1764         GATE(CLK_PCLK_HSI2C4, "pclk_hsi2c4", "aclk_peric_66",
1765                         ENABLE_PCLK_PERIC1, 0, CLK_SET_RATE_PARENT, 0),
1766
1767         /* ENABLE_SCLK_PERIC */
1768         GATE(CLK_SCLK_IOCLK_SPI4, "sclk_ioclk_spi4", "ioclk_spi4_clk_in",
1769                         ENABLE_SCLK_PERIC, 21, CLK_SET_RATE_PARENT, 0),
1770         GATE(CLK_SCLK_IOCLK_SPI3, "sclk_ioclk_spi3", "ioclk_spi3_clk_in",
1771                         ENABLE_SCLK_PERIC, 20, CLK_SET_RATE_PARENT, 0),
1772         GATE(CLK_SCLK_SPI4, "sclk_spi4", "sclk_spi4_peric", ENABLE_SCLK_PERIC,
1773                         19, CLK_SET_RATE_PARENT, 0),
1774         GATE(CLK_SCLK_SPI3, "sclk_spi3", "sclk_spi3_peric", ENABLE_SCLK_PERIC,
1775                         18, CLK_SET_RATE_PARENT, 0),
1776         GATE(CLK_SCLK_SCI, "sclk_sci", "div_sclk_sci", ENABLE_SCLK_PERIC,
1777                         17, 0, 0),
1778         GATE(CLK_SCLK_SC_IN, "sclk_sc_in", "div_sclk_sc_in", ENABLE_SCLK_PERIC,
1779                         16, 0, 0),
1780         GATE(CLK_SCLK_PWM, "sclk_pwm", "oscclk", ENABLE_SCLK_PERIC, 15, 0, 0),
1781         GATE(CLK_SCLK_IOCLK_SPI2, "sclk_ioclk_spi2", "ioclk_spi2_clk_in",
1782                         ENABLE_SCLK_PERIC, 13, CLK_SET_RATE_PARENT, 0),
1783         GATE(CLK_SCLK_IOCLK_SPI1, "sclk_ioclk_spi1", "ioclk_spi1_clk_in",
1784                         ENABLE_SCLK_PERIC, 12,
1785                         CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
1786         GATE(CLK_SCLK_IOCLK_SPI0, "sclk_ioclk_spi0", "ioclk_spi0_clk_in",
1787                         ENABLE_SCLK_PERIC, 11, CLK_SET_RATE_PARENT, 0),
1788         GATE(CLK_SCLK_IOCLK_I2S1_BCLK, "sclk_ioclk_i2s1_bclk",
1789                         "ioclk_i2s1_bclk_in", ENABLE_SCLK_PERIC, 10,
1790                         CLK_SET_RATE_PARENT, 0),
1791         GATE(CLK_SCLK_SPDIF, "sclk_spdif", "sclk_spdif_peric",
1792                         ENABLE_SCLK_PERIC, 8, CLK_SET_RATE_PARENT, 0),
1793         GATE(CLK_SCLK_PCM1, "sclk_pcm1", "sclk_pcm1_peric",
1794                         ENABLE_SCLK_PERIC, 7, CLK_SET_RATE_PARENT, 0),
1795         GATE(CLK_SCLK_I2S1, "sclk_i2s1", "sclk_i2s1_peric",
1796                         ENABLE_SCLK_PERIC, 6, CLK_SET_RATE_PARENT, 0),
1797         GATE(CLK_SCLK_SPI2, "sclk_spi2", "sclk_spi2_peric", ENABLE_SCLK_PERIC,
1798                         5, CLK_SET_RATE_PARENT, 0),
1799         GATE(CLK_SCLK_SPI1, "sclk_spi1", "sclk_spi1_peric", ENABLE_SCLK_PERIC,
1800                         4, CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
1801         GATE(CLK_SCLK_SPI0, "sclk_spi0", "sclk_spi0_peric", ENABLE_SCLK_PERIC,
1802                         3, CLK_SET_RATE_PARENT, 0),
1803         GATE(CLK_SCLK_UART2, "sclk_uart2", "sclk_uart2_peric",
1804                         ENABLE_SCLK_PERIC, 2,
1805                         CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
1806         GATE(CLK_SCLK_UART1, "sclk_uart1", "sclk_uart1_peric",
1807                         ENABLE_SCLK_PERIC, 1,
1808                         CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
1809         GATE(CLK_SCLK_UART0, "sclk_uart0", "sclk_uart0_peric",
1810                         ENABLE_SCLK_PERIC, 0,
1811                         CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
1812 };
1813
1814 static struct samsung_cmu_info peric_cmu_info __initdata = {
1815         .div_clks               = peric_div_clks,
1816         .nr_div_clks            = ARRAY_SIZE(peric_div_clks),
1817         .gate_clks              = peric_gate_clks,
1818         .nr_gate_clks           = ARRAY_SIZE(peric_gate_clks),
1819         .nr_clk_ids             = PERIC_NR_CLK,
1820         .clk_regs               = peric_clk_regs,
1821         .nr_clk_regs            = ARRAY_SIZE(peric_clk_regs),
1822 };
1823
1824 static void __init exynos5433_cmu_peric_init(struct device_node *np)
1825 {
1826         samsung_cmu_register_one(np, &peric_cmu_info);
1827 }
1828
1829 CLK_OF_DECLARE(exynos5433_cmu_peric, "samsung,exynos5433-cmu-peric",
1830                 exynos5433_cmu_peric_init);
1831
1832 /*
1833  * Register offset definitions for CMU_PERIS
1834  */
1835 #define ENABLE_ACLK_PERIS                               0x0800
1836 #define ENABLE_PCLK_PERIS                               0x0900
1837 #define ENABLE_PCLK_PERIS_SECURE_TZPC                   0x0904
1838 #define ENABLE_PCLK_PERIS_SECURE_SECKEY_APBIF           0x0908
1839 #define ENABLE_PCLK_PERIS_SECURE_CHIPID_APBIF           0x090c
1840 #define ENABLE_PCLK_PERIS_SECURE_TOPRTC                 0x0910
1841 #define ENABLE_PCLK_PERIS_SECURE_CUSTOM_EFUSE_APBIF     0x0914
1842 #define ENABLE_PCLK_PERIS_SECURE_ANTIRBK_CNT_APBIF      0x0918
1843 #define ENABLE_PCLK_PERIS_SECURE_OTP_CON_APBIF          0x091c
1844 #define ENABLE_SCLK_PERIS                               0x0a00
1845 #define ENABLE_SCLK_PERIS_SECURE_SECKEY                 0x0a04
1846 #define ENABLE_SCLK_PERIS_SECURE_CHIPID                 0x0a08
1847 #define ENABLE_SCLK_PERIS_SECURE_TOPRTC                 0x0a0c
1848 #define ENABLE_SCLK_PERIS_SECURE_CUSTOM_EFUSE           0x0a10
1849 #define ENABLE_SCLK_PERIS_SECURE_ANTIRBK_CNT            0x0a14
1850 #define ENABLE_SCLK_PERIS_SECURE_OTP_CON                0x0a18
1851 #define ENABLE_IP_PERIS0                                0x0b00
1852 #define ENABLE_IP_PERIS1                                0x0b04
1853 #define ENABLE_IP_PERIS_SECURE_TZPC                     0x0b08
1854 #define ENABLE_IP_PERIS_SECURE_SECKEY                   0x0b0c
1855 #define ENABLE_IP_PERIS_SECURE_CHIPID                   0x0b10
1856 #define ENABLE_IP_PERIS_SECURE_TOPRTC                   0x0b14
1857 #define ENABLE_IP_PERIS_SECURE_CUSTOM_EFUSE             0x0b18
1858 #define ENABLE_IP_PERIS_SECURE_ANTIBRK_CNT              0x0b1c
1859 #define ENABLE_IP_PERIS_SECURE_OTP_CON                  0x0b20
1860
1861 static unsigned long peris_clk_regs[] __initdata = {
1862         ENABLE_ACLK_PERIS,
1863         ENABLE_PCLK_PERIS,
1864         ENABLE_PCLK_PERIS_SECURE_TZPC,
1865         ENABLE_PCLK_PERIS_SECURE_SECKEY_APBIF,
1866         ENABLE_PCLK_PERIS_SECURE_CHIPID_APBIF,
1867         ENABLE_PCLK_PERIS_SECURE_TOPRTC,
1868         ENABLE_PCLK_PERIS_SECURE_CUSTOM_EFUSE_APBIF,
1869         ENABLE_PCLK_PERIS_SECURE_ANTIRBK_CNT_APBIF,
1870         ENABLE_PCLK_PERIS_SECURE_OTP_CON_APBIF,
1871         ENABLE_SCLK_PERIS,
1872         ENABLE_SCLK_PERIS_SECURE_SECKEY,
1873         ENABLE_SCLK_PERIS_SECURE_CHIPID,
1874         ENABLE_SCLK_PERIS_SECURE_TOPRTC,
1875         ENABLE_SCLK_PERIS_SECURE_CUSTOM_EFUSE,
1876         ENABLE_SCLK_PERIS_SECURE_ANTIRBK_CNT,
1877         ENABLE_SCLK_PERIS_SECURE_OTP_CON,
1878         ENABLE_IP_PERIS0,
1879         ENABLE_IP_PERIS1,
1880         ENABLE_IP_PERIS_SECURE_TZPC,
1881         ENABLE_IP_PERIS_SECURE_SECKEY,
1882         ENABLE_IP_PERIS_SECURE_CHIPID,
1883         ENABLE_IP_PERIS_SECURE_TOPRTC,
1884         ENABLE_IP_PERIS_SECURE_CUSTOM_EFUSE,
1885         ENABLE_IP_PERIS_SECURE_ANTIBRK_CNT,
1886         ENABLE_IP_PERIS_SECURE_OTP_CON,
1887 };
1888
1889 static struct samsung_gate_clock peris_gate_clks[] __initdata = {
1890         /* ENABLE_ACLK_PERIS */
1891         GATE(CLK_ACLK_AHB2APB_PERIS1P, "aclk_ahb2apb_peris1p", "aclk_peris_66",
1892                         ENABLE_ACLK_PERIS, 2, CLK_IGNORE_UNUSED, 0),
1893         GATE(CLK_ACLK_AHB2APB_PERIS0P, "aclk_ahb2apb_peris0p", "aclk_peris_66",
1894                         ENABLE_ACLK_PERIS, 1, CLK_IGNORE_UNUSED, 0),
1895         GATE(CLK_ACLK_PERISNP_66, "aclk_perisnp_66", "aclk_peris_66",
1896                         ENABLE_ACLK_PERIS, 0, CLK_IGNORE_UNUSED, 0),
1897
1898         /* ENABLE_PCLK_PERIS */
1899         GATE(CLK_PCLK_HPM_APBIF, "pclk_hpm_apbif", "aclk_peris_66",
1900                         ENABLE_PCLK_PERIS, 30, CLK_IGNORE_UNUSED, 0),
1901         GATE(CLK_PCLK_TMU1_APBIF, "pclk_tmu1_apbif", "aclk_peris_66",
1902                         ENABLE_PCLK_PERIS, 24, CLK_IGNORE_UNUSED, 0),
1903         GATE(CLK_PCLK_TMU0_APBIF, "pclk_tmu0_apbif", "aclk_peris_66",
1904                         ENABLE_PCLK_PERIS, 23, CLK_IGNORE_UNUSED, 0),
1905         GATE(CLK_PCLK_PMU_PERIS, "pclk_pmu_peris", "aclk_peris_66",
1906                         ENABLE_PCLK_PERIS, 22, CLK_IGNORE_UNUSED, 0),
1907         GATE(CLK_PCLK_SYSREG_PERIS, "pclk_sysreg_peris", "aclk_peris_66",
1908                         ENABLE_PCLK_PERIS, 21, CLK_IGNORE_UNUSED, 0),
1909         GATE(CLK_PCLK_CMU_TOP_APBIF, "pclk_cmu_top_apbif", "aclk_peris_66",
1910                         ENABLE_PCLK_PERIS, 20, CLK_IGNORE_UNUSED, 0),
1911         GATE(CLK_PCLK_WDT_APOLLO, "pclk_wdt_apollo", "aclk_peris_66",
1912                         ENABLE_PCLK_PERIS, 17, CLK_IGNORE_UNUSED, 0),
1913         GATE(CLK_PCLK_WDT_ATLAS, "pclk_wdt_atlas", "aclk_peris_66",
1914                         ENABLE_PCLK_PERIS, 16, CLK_IGNORE_UNUSED, 0),
1915         GATE(CLK_PCLK_MCT, "pclk_mct", "aclk_peris_66",
1916                         ENABLE_PCLK_PERIS, 15, CLK_IGNORE_UNUSED, 0),
1917         GATE(CLK_PCLK_HDMI_CEC, "pclk_hdmi_cec", "aclk_peris_66",
1918                         ENABLE_PCLK_PERIS, 14, CLK_IGNORE_UNUSED, 0),
1919
1920         /* ENABLE_PCLK_PERIS_SECURE_TZPC */
1921         GATE(CLK_PCLK_TZPC12, "pclk_tzpc12", "aclk_peris_66",
1922                         ENABLE_PCLK_PERIS_SECURE_TZPC, 12, CLK_IGNORE_UNUSED, 0),
1923         GATE(CLK_PCLK_TZPC11, "pclk_tzpc11", "aclk_peris_66",
1924                         ENABLE_PCLK_PERIS_SECURE_TZPC, 11, CLK_IGNORE_UNUSED, 0),
1925         GATE(CLK_PCLK_TZPC10, "pclk_tzpc10", "aclk_peris_66",
1926                         ENABLE_PCLK_PERIS_SECURE_TZPC, 10, CLK_IGNORE_UNUSED, 0),
1927         GATE(CLK_PCLK_TZPC9, "pclk_tzpc9", "aclk_peris_66",
1928                         ENABLE_PCLK_PERIS_SECURE_TZPC, 9, CLK_IGNORE_UNUSED, 0),
1929         GATE(CLK_PCLK_TZPC8, "pclk_tzpc8", "aclk_peris_66",
1930                         ENABLE_PCLK_PERIS_SECURE_TZPC, 8, CLK_IGNORE_UNUSED, 0),
1931         GATE(CLK_PCLK_TZPC7, "pclk_tzpc7", "aclk_peris_66",
1932                         ENABLE_PCLK_PERIS_SECURE_TZPC, 7, CLK_IGNORE_UNUSED, 0),
1933         GATE(CLK_PCLK_TZPC6, "pclk_tzpc6", "aclk_peris_66",
1934                         ENABLE_PCLK_PERIS_SECURE_TZPC, 6, CLK_IGNORE_UNUSED, 0),
1935         GATE(CLK_PCLK_TZPC5, "pclk_tzpc5", "aclk_peris_66",
1936                         ENABLE_PCLK_PERIS_SECURE_TZPC, 5, CLK_IGNORE_UNUSED, 0),
1937         GATE(CLK_PCLK_TZPC4, "pclk_tzpc4", "aclk_peris_66",
1938                         ENABLE_PCLK_PERIS_SECURE_TZPC, 4, CLK_IGNORE_UNUSED, 0),
1939         GATE(CLK_PCLK_TZPC3, "pclk_tzpc3", "aclk_peris_66",
1940                         ENABLE_PCLK_PERIS_SECURE_TZPC, 3, CLK_IGNORE_UNUSED, 0),
1941         GATE(CLK_PCLK_TZPC2, "pclk_tzpc2", "aclk_peris_66",
1942                         ENABLE_PCLK_PERIS_SECURE_TZPC, 2, CLK_IGNORE_UNUSED, 0),
1943         GATE(CLK_PCLK_TZPC1, "pclk_tzpc1", "aclk_peris_66",
1944                         ENABLE_PCLK_PERIS_SECURE_TZPC, 1, CLK_IGNORE_UNUSED, 0),
1945         GATE(CLK_PCLK_TZPC0, "pclk_tzpc0", "aclk_peris_66",
1946                         ENABLE_PCLK_PERIS_SECURE_TZPC, 0, CLK_IGNORE_UNUSED, 0),
1947
1948         /* ENABLE_PCLK_PERIS_SECURE_SECKEY_APBIF */
1949         GATE(CLK_PCLK_SECKEY_APBIF, "pclk_seckey_apbif", "aclk_peris_66",
1950                         ENABLE_PCLK_PERIS_SECURE_SECKEY_APBIF, 0, CLK_IGNORE_UNUSED, 0),
1951
1952         /* ENABLE_PCLK_PERIS_SECURE_CHIPID_APBIF */
1953         GATE(CLK_PCLK_CHIPID_APBIF, "pclk_chipid_apbif", "aclk_peris_66",
1954                         ENABLE_PCLK_PERIS_SECURE_CHIPID_APBIF, 0, CLK_IGNORE_UNUSED, 0),
1955
1956         /* ENABLE_PCLK_PERIS_SECURE_TOPRTC */
1957         GATE(CLK_PCLK_TOPRTC, "pclk_toprtc", "aclk_peris_66",
1958                         ENABLE_PCLK_PERIS_SECURE_TOPRTC, 0, 0, 0),
1959
1960         /* ENABLE_PCLK_PERIS_SECURE_CUSTOM_EFUSE_APBIF */
1961         GATE(CLK_PCLK_CUSTOM_EFUSE_APBIF, "pclk_custom_efuse_apbif",
1962                         "aclk_peris_66",
1963                         ENABLE_PCLK_PERIS_SECURE_CUSTOM_EFUSE_APBIF, 0, 0, 0),
1964
1965         /* ENABLE_PCLK_PERIS_SECURE_ANTIRBK_CNT_APBIF */
1966         GATE(CLK_PCLK_ANTIRBK_CNT_APBIF, "pclk_antirbk_cnt_apbif",
1967                         "aclk_peris_66",
1968                         ENABLE_PCLK_PERIS_SECURE_ANTIRBK_CNT_APBIF, 0, 0, 0),
1969
1970         /* ENABLE_PCLK_PERIS_SECURE_OTP_CON_APBIF */
1971         GATE(CLK_PCLK_OTP_CON_APBIF, "pclk_otp_con_apbif",
1972                         "aclk_peris_66",
1973                         ENABLE_PCLK_PERIS_SECURE_OTP_CON_APBIF, 0, 0, 0),
1974
1975         /* ENABLE_SCLK_PERIS */
1976         GATE(CLK_SCLK_ASV_TB, "sclk_asv_tb", "oscclk_efuse_common",
1977                         ENABLE_SCLK_PERIS, 10, 0, 0),
1978         GATE(CLK_SCLK_TMU1, "sclk_tmu1", "oscclk_efuse_common",
1979                         ENABLE_SCLK_PERIS, 4, 0, 0),
1980         GATE(CLK_SCLK_TMU0, "sclk_tmu0", "oscclk_efuse_common",
1981                         ENABLE_SCLK_PERIS, 3, 0, 0),
1982
1983         /* ENABLE_SCLK_PERIS_SECURE_SECKEY */
1984         GATE(CLK_SCLK_SECKEY, "sclk_seckey", "oscclk_efuse_common",
1985                         ENABLE_SCLK_PERIS_SECURE_SECKEY, 0, CLK_IGNORE_UNUSED, 0),
1986
1987         /* ENABLE_SCLK_PERIS_SECURE_CHIPID */
1988         GATE(CLK_SCLK_CHIPID, "sclk_chipid", "oscclk_efuse_common",
1989                         ENABLE_SCLK_PERIS_SECURE_CHIPID, 0, CLK_IGNORE_UNUSED, 0),
1990
1991         /* ENABLE_SCLK_PERIS_SECURE_TOPRTC */
1992         GATE(CLK_SCLK_TOPRTC, "sclk_toprtc", "oscclk_efuse_common",
1993                         ENABLE_SCLK_PERIS_SECURE_TOPRTC, 0, 0, 0),
1994
1995         /* ENABLE_SCLK_PERIS_SECURE_CUSTOM_EFUSE */
1996         GATE(CLK_SCLK_CUSTOM_EFUSE, "sclk_custom_efuse", "oscclk_efuse_common",
1997                         ENABLE_SCLK_PERIS_SECURE_CUSTOM_EFUSE, 0, 0, 0),
1998
1999         /* ENABLE_SCLK_PERIS_SECURE_ANTIRBK_CNT */
2000         GATE(CLK_SCLK_ANTIRBK_CNT, "sclk_antirbk_cnt", "oscclk_efuse_common",
2001                         ENABLE_SCLK_PERIS_SECURE_ANTIRBK_CNT, 0, 0, 0),
2002
2003         /* ENABLE_SCLK_PERIS_SECURE_OTP_CON */
2004         GATE(CLK_SCLK_OTP_CON, "sclk_otp_con", "oscclk_efuse_common",
2005                         ENABLE_SCLK_PERIS_SECURE_OTP_CON, 0, 0, 0),
2006 };
2007
2008 static struct samsung_cmu_info peris_cmu_info __initdata = {
2009         .gate_clks              = peris_gate_clks,
2010         .nr_gate_clks           = ARRAY_SIZE(peris_gate_clks),
2011         .nr_clk_ids             = PERIS_NR_CLK,
2012         .clk_regs               = peris_clk_regs,
2013         .nr_clk_regs            = ARRAY_SIZE(peris_clk_regs),
2014 };
2015
2016 static void __init exynos5433_cmu_peris_init(struct device_node *np)
2017 {
2018         samsung_cmu_register_one(np, &peris_cmu_info);
2019 }
2020
2021 CLK_OF_DECLARE(exynos5433_cmu_peris, "samsung,exynos5433-cmu-peris",
2022                 exynos5433_cmu_peris_init);
2023
2024 /*
2025  * Register offset definitions for CMU_FSYS
2026  */
2027 #define MUX_SEL_FSYS0                   0x0200
2028 #define MUX_SEL_FSYS1                   0x0204
2029 #define MUX_SEL_FSYS2                   0x0208
2030 #define MUX_SEL_FSYS3                   0x020c
2031 #define MUX_SEL_FSYS4                   0x0210
2032 #define MUX_ENABLE_FSYS0                0x0300
2033 #define MUX_ENABLE_FSYS1                0x0304
2034 #define MUX_ENABLE_FSYS2                0x0308
2035 #define MUX_ENABLE_FSYS3                0x030c
2036 #define MUX_ENABLE_FSYS4                0x0310
2037 #define MUX_STAT_FSYS0                  0x0400
2038 #define MUX_STAT_FSYS1                  0x0404
2039 #define MUX_STAT_FSYS2                  0x0408
2040 #define MUX_STAT_FSYS3                  0x040c
2041 #define MUX_STAT_FSYS4                  0x0410
2042 #define MUX_IGNORE_FSYS2                0x0508
2043 #define MUX_IGNORE_FSYS3                0x050c
2044 #define ENABLE_ACLK_FSYS0               0x0800
2045 #define ENABLE_ACLK_FSYS1               0x0804
2046 #define ENABLE_PCLK_FSYS                0x0900
2047 #define ENABLE_SCLK_FSYS                0x0a00
2048 #define ENABLE_IP_FSYS0                 0x0b00
2049 #define ENABLE_IP_FSYS1                 0x0b04
2050
2051 /* list of all parent clock list */
2052 PNAME(mout_sclk_ufs_mphy_user_p)        = { "oscclk", "sclk_ufs_mphy", };
2053 PNAME(mout_aclk_fsys_200_user_p)        = { "oscclk", "div_aclk_fsys_200", };
2054 PNAME(mout_sclk_pcie_100_user_p)        = { "oscclk", "sclk_pcie_100_fsys",};
2055 PNAME(mout_sclk_ufsunipro_user_p)       = { "oscclk", "sclk_ufsunipro_fsys",};
2056 PNAME(mout_sclk_mmc2_user_p)            = { "oscclk", "sclk_mmc2_fsys", };
2057 PNAME(mout_sclk_mmc1_user_p)            = { "oscclk", "sclk_mmc1_fsys", };
2058 PNAME(mout_sclk_mmc0_user_p)            = { "oscclk", "sclk_mmc0_fsys", };
2059 PNAME(mout_sclk_usbhost30_user_p)       = { "oscclk", "sclk_usbhost30_fsys",};
2060 PNAME(mout_sclk_usbdrd30_user_p)        = { "oscclk", "sclk_usbdrd30_fsys", };
2061
2062 PNAME(mout_phyclk_usbhost30_uhost30_pipe_pclk_user_p)
2063                 = { "oscclk", "phyclk_usbhost30_uhost30_pipe_pclk_phy", };
2064 PNAME(mout_phyclk_usbhost30_uhost30_phyclock_user_p)
2065                 = { "oscclk", "phyclk_usbhost30_uhost30_phyclock_phy", };
2066 PNAME(mout_phyclk_usbhost20_phy_hsic1_p)
2067                 = { "oscclk", "phyclk_usbhost20_phy_hsic1_phy", };
2068 PNAME(mout_phyclk_usbhost20_phy_clk48mohci_user_p)
2069                 = { "oscclk", "phyclk_usbhost20_phy_clk48mohci_phy", };
2070 PNAME(mout_phyclk_usbhost20_phy_phyclock_user_p)
2071                 = { "oscclk", "phyclk_usbhost20_phy_phyclock_phy", };
2072 PNAME(mout_phyclk_usbhost20_phy_freeclk_user_p)
2073                 = { "oscclk", "phyclk_usbhost20_phy_freeclk_phy", };
2074 PNAME(mout_phyclk_usbdrd30_udrd30_pipe_pclk_p)
2075                 = { "oscclk", "phyclk_usbdrd30_udrd30_pipe_pclk_phy", };
2076 PNAME(mout_phyclk_usbdrd30_udrd30_phyclock_user_p)
2077                 = { "oscclk", "phyclk_usbdrd30_udrd30_phyclock_phy", };
2078 PNAME(mout_phyclk_ufs_rx1_symbol_user_p)
2079                 = { "oscclk", "phyclk_ufs_rx1_symbol_phy", };
2080 PNAME(mout_phyclk_ufs_rx0_symbol_user_p)
2081                 = { "oscclk", "phyclk_ufs_rx0_symbol_phy", };
2082 PNAME(mout_phyclk_ufs_tx1_symbol_user_p)
2083                 = { "oscclk", "phyclk_ufs_tx1_symbol_phy", };
2084 PNAME(mout_phyclk_ufs_tx0_symbol_user_p)
2085                 = { "oscclk", "phyclk_ufs_tx0_symbol_phy", };
2086 PNAME(mout_phyclk_lli_mphy_to_ufs_user_p)
2087                 = { "oscclk", "phyclk_lli_mphy_to_ufs_phy", };
2088 PNAME(mout_sclk_mphy_p)
2089                 = { "mout_sclk_ufs_mphy_user",
2090                             "mout_phyclk_lli_mphy_to_ufs_user", };
2091
2092 static unsigned long fsys_clk_regs[] __initdata = {
2093         MUX_SEL_FSYS0,
2094         MUX_SEL_FSYS1,
2095         MUX_SEL_FSYS2,
2096         MUX_SEL_FSYS3,
2097         MUX_SEL_FSYS4,
2098         MUX_ENABLE_FSYS0,
2099         MUX_ENABLE_FSYS1,
2100         MUX_ENABLE_FSYS2,
2101         MUX_ENABLE_FSYS3,
2102         MUX_ENABLE_FSYS4,
2103         MUX_IGNORE_FSYS2,
2104         MUX_IGNORE_FSYS3,
2105         ENABLE_ACLK_FSYS0,
2106         ENABLE_ACLK_FSYS1,
2107         ENABLE_PCLK_FSYS,
2108         ENABLE_SCLK_FSYS,
2109         ENABLE_IP_FSYS0,
2110         ENABLE_IP_FSYS1,
2111 };
2112
2113 static struct samsung_fixed_rate_clock fsys_fixed_clks[] __initdata = {
2114         /* PHY clocks from USBDRD30_PHY */
2115         FRATE(CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_PHY,
2116                         "phyclk_usbdrd30_udrd30_phyclock_phy", NULL,
2117                         CLK_IS_ROOT, 60000000),
2118         FRATE(CLK_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_PHY,
2119                         "phyclk_usbdrd30_udrd30_pipe_pclk_phy", NULL,
2120                         CLK_IS_ROOT, 125000000),
2121         /* PHY clocks from USBHOST30_PHY */
2122         FRATE(CLK_PHYCLK_USBHOST30_UHOST30_PHYCLOCK_PHY,
2123                         "phyclk_usbhost30_uhost30_phyclock_phy", NULL,
2124                         CLK_IS_ROOT, 60000000),
2125         FRATE(CLK_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK_PHY,
2126                         "phyclk_usbhost30_uhost30_pipe_pclk_phy", NULL,
2127                         CLK_IS_ROOT, 125000000),
2128         /* PHY clocks from USBHOST20_PHY */
2129         FRATE(CLK_PHYCLK_USBHOST20_PHY_FREECLK_PHY,
2130                         "phyclk_usbhost20_phy_freeclk_phy", NULL, CLK_IS_ROOT,
2131                         60000000),
2132         FRATE(CLK_PHYCLK_USBHOST20_PHY_PHYCLOCK_PHY,
2133                         "phyclk_usbhost20_phy_phyclock_phy", NULL, CLK_IS_ROOT,
2134                         60000000),
2135         FRATE(CLK_PHYCLK_USBHOST20_PHY_CLK48MOHCI_PHY,
2136                         "phyclk_usbhost20_phy_clk48mohci_phy", NULL,
2137                         CLK_IS_ROOT, 48000000),
2138         FRATE(CLK_PHYCLK_USBHOST20_PHY_HSIC1_PHY,
2139                         "phyclk_usbhost20_phy_hsic1_phy", NULL, CLK_IS_ROOT,
2140                         60000000),
2141         /* PHY clocks from UFS_PHY */
2142         FRATE(CLK_PHYCLK_UFS_TX0_SYMBOL_PHY, "phyclk_ufs_tx0_symbol_phy",
2143                         NULL, CLK_IS_ROOT, 300000000),
2144         FRATE(CLK_PHYCLK_UFS_RX0_SYMBOL_PHY, "phyclk_ufs_rx0_symbol_phy",
2145                         NULL, CLK_IS_ROOT, 300000000),
2146         FRATE(CLK_PHYCLK_UFS_TX1_SYMBOL_PHY, "phyclk_ufs_tx1_symbol_phy",
2147                         NULL, CLK_IS_ROOT, 300000000),
2148         FRATE(CLK_PHYCLK_UFS_RX1_SYMBOL_PHY, "phyclk_ufs_rx1_symbol_phy",
2149                         NULL, CLK_IS_ROOT, 300000000),
2150         /* PHY clocks from LLI_PHY */
2151         FRATE(CLK_PHYCLK_LLI_MPHY_TO_UFS_PHY, "phyclk_lli_mphy_to_ufs_phy",
2152                         NULL, CLK_IS_ROOT, 26000000),
2153 };
2154
2155 static struct samsung_mux_clock fsys_mux_clks[] __initdata = {
2156         /* MUX_SEL_FSYS0 */
2157         MUX(CLK_MOUT_SCLK_UFS_MPHY_USER, "mout_sclk_ufs_mphy_user",
2158                         mout_sclk_ufs_mphy_user_p, MUX_SEL_FSYS0, 4, 1),
2159         MUX(CLK_MOUT_ACLK_FSYS_200_USER, "mout_aclk_fsys_200_user",
2160                         mout_aclk_fsys_200_user_p, MUX_SEL_FSYS0, 0, 1),
2161
2162         /* MUX_SEL_FSYS1 */
2163         MUX(CLK_MOUT_SCLK_PCIE_100_USER, "mout_sclk_pcie_100_user",
2164                         mout_sclk_pcie_100_user_p, MUX_SEL_FSYS1, 28, 1),
2165         MUX(CLK_MOUT_SCLK_UFSUNIPRO_USER, "mout_sclk_ufsunipro_user",
2166                         mout_sclk_ufsunipro_user_p, MUX_SEL_FSYS1, 24, 1),
2167         MUX(CLK_MOUT_SCLK_MMC2_USER, "mout_sclk_mmc2_user",
2168                         mout_sclk_mmc2_user_p, MUX_SEL_FSYS1, 20, 1),
2169         MUX(CLK_MOUT_SCLK_MMC1_USER, "mout_sclk_mmc1_user",
2170                         mout_sclk_mmc1_user_p, MUX_SEL_FSYS1, 16, 1),
2171         MUX(CLK_MOUT_SCLK_MMC0_USER, "mout_sclk_mmc0_user",
2172                         mout_sclk_mmc0_user_p, MUX_SEL_FSYS1, 12, 1),
2173         MUX(CLK_MOUT_SCLK_USBHOST30_USER, "mout_sclk_usbhost30_user",
2174                         mout_sclk_usbhost30_user_p, MUX_SEL_FSYS1, 4, 1),
2175         MUX(CLK_MOUT_SCLK_USBDRD30_USER, "mout_sclk_usbdrd30_user",
2176                         mout_sclk_usbdrd30_user_p, MUX_SEL_FSYS1, 0, 1),
2177
2178         /* MUX_SEL_FSYS2 */
2179         MUX(CLK_MOUT_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK_USER,
2180                         "mout_phyclk_usbhost30_uhost30_pipe_pclk_user",
2181                         mout_phyclk_usbhost30_uhost30_pipe_pclk_user_p,
2182                         MUX_SEL_FSYS2, 28, 1),
2183         MUX(CLK_MOUT_PHYCLK_USBHOST30_UHOST30_PHYCLOCK_USER,
2184                         "mout_phyclk_usbhost30_uhost30_phyclock_user",
2185                         mout_phyclk_usbhost30_uhost30_phyclock_user_p,
2186                         MUX_SEL_FSYS2, 24, 1),
2187         MUX(CLK_MOUT_PHYCLK_USBHOST20_PHY_HSIC1_USER,
2188                         "mout_phyclk_usbhost20_phy_hsic1",
2189                         mout_phyclk_usbhost20_phy_hsic1_p,
2190                         MUX_SEL_FSYS2, 20, 1),
2191         MUX(CLK_MOUT_PHYCLK_USBHOST20_PHY_CLK48MOHCI_USER,
2192                         "mout_phyclk_usbhost20_phy_clk48mohci_user",
2193                         mout_phyclk_usbhost20_phy_clk48mohci_user_p,
2194                         MUX_SEL_FSYS2, 16, 1),
2195         MUX(CLK_MOUT_PHYCLK_USBHOST20_PHY_PHYCLOCK_USER,
2196                         "mout_phyclk_usbhost20_phy_phyclock_user",
2197                         mout_phyclk_usbhost20_phy_phyclock_user_p,
2198                         MUX_SEL_FSYS2, 12, 1),
2199         MUX(CLK_MOUT_PHYCLK_USBHOST20_PHY_PHY_FREECLK_USER,
2200                         "mout_phyclk_usbhost20_phy_freeclk_user",
2201                         mout_phyclk_usbhost20_phy_freeclk_user_p,
2202                         MUX_SEL_FSYS2, 8, 1),
2203         MUX(CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_USER,
2204                         "mout_phyclk_usbdrd30_udrd30_pipe_pclk_user",
2205                         mout_phyclk_usbdrd30_udrd30_pipe_pclk_p,
2206                         MUX_SEL_FSYS2, 4, 1),
2207         MUX(CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_USER,
2208                         "mout_phyclk_usbdrd30_udrd30_phyclock_user",
2209                         mout_phyclk_usbdrd30_udrd30_phyclock_user_p,
2210                         MUX_SEL_FSYS2, 0, 1),
2211
2212         /* MUX_SEL_FSYS3 */
2213         MUX(CLK_MOUT_PHYCLK_UFS_RX1_SYMBOL_USER,
2214                         "mout_phyclk_ufs_rx1_symbol_user",
2215                         mout_phyclk_ufs_rx1_symbol_user_p,
2216                         MUX_SEL_FSYS3, 16, 1),
2217         MUX(CLK_MOUT_PHYCLK_UFS_RX0_SYMBOL_USER,
2218                         "mout_phyclk_ufs_rx0_symbol_user",
2219                         mout_phyclk_ufs_rx0_symbol_user_p,
2220                         MUX_SEL_FSYS3, 12, 1),
2221         MUX(CLK_MOUT_PHYCLK_UFS_TX1_SYMBOL_USER,
2222                         "mout_phyclk_ufs_tx1_symbol_user",
2223                         mout_phyclk_ufs_tx1_symbol_user_p,
2224                         MUX_SEL_FSYS3, 8, 1),
2225         MUX(CLK_MOUT_PHYCLK_UFS_TX0_SYMBOL_USER,
2226                         "mout_phyclk_ufs_tx0_symbol_user",
2227                         mout_phyclk_ufs_tx0_symbol_user_p,
2228                         MUX_SEL_FSYS3, 4, 1),
2229         MUX(CLK_MOUT_PHYCLK_LLI_MPHY_TO_UFS_USER,
2230                         "mout_phyclk_lli_mphy_to_ufs_user",
2231                         mout_phyclk_lli_mphy_to_ufs_user_p,
2232                         MUX_SEL_FSYS3, 0, 1),
2233
2234         /* MUX_SEL_FSYS4 */
2235         MUX(CLK_MOUT_SCLK_MPHY, "mout_sclk_mphy", mout_sclk_mphy_p,
2236                         MUX_SEL_FSYS4, 0, 1),
2237 };
2238
2239 static struct samsung_gate_clock fsys_gate_clks[] __initdata = {
2240         /* ENABLE_ACLK_FSYS0 */
2241         GATE(CLK_ACLK_PCIE, "aclk_pcie", "mout_aclk_fsys_200_user",
2242                         ENABLE_ACLK_FSYS0, 13, CLK_IGNORE_UNUSED, 0),
2243         GATE(CLK_ACLK_PDMA1, "aclk_pdma1", "mout_aclk_fsys_200_user",
2244                         ENABLE_ACLK_FSYS0, 11, CLK_IGNORE_UNUSED, 0),
2245         GATE(CLK_ACLK_TSI, "aclk_tsi", "mout_aclk_fsys_200_user",
2246                         ENABLE_ACLK_FSYS0, 10, CLK_IGNORE_UNUSED, 0),
2247         GATE(CLK_ACLK_MMC2, "aclk_mmc2", "mout_aclk_fsys_200_user",
2248                         ENABLE_ACLK_FSYS0, 8, CLK_IGNORE_UNUSED, 0),
2249         GATE(CLK_ACLK_MMC1, "aclk_mmc1", "mout_aclk_fsys_200_user",
2250                         ENABLE_ACLK_FSYS0, 7, CLK_IGNORE_UNUSED, 0),
2251         GATE(CLK_ACLK_MMC0, "aclk_mmc0", "mout_aclk_fsys_200_user",
2252                         ENABLE_ACLK_FSYS0, 6, CLK_IGNORE_UNUSED, 0),
2253         GATE(CLK_ACLK_UFS, "aclk_ufs", "mout_aclk_fsys_200_user",
2254                         ENABLE_ACLK_FSYS0, 5, CLK_IGNORE_UNUSED, 0),
2255         GATE(CLK_ACLK_USBHOST20, "aclk_usbhost20", "mout_aclk_fsys_200_user",
2256                         ENABLE_ACLK_FSYS0, 3, CLK_IGNORE_UNUSED, 0),
2257         GATE(CLK_ACLK_USBHOST30, "aclk_usbhost30", "mout_aclk_fsys_200_user",
2258                         ENABLE_ACLK_FSYS0, 2, CLK_IGNORE_UNUSED, 0),
2259         GATE(CLK_ACLK_USBDRD30, "aclk_usbdrd30", "mout_aclk_fsys_200_user",
2260                         ENABLE_ACLK_FSYS0, 1, CLK_IGNORE_UNUSED, 0),
2261         GATE(CLK_ACLK_PDMA0, "aclk_pdma0", "mout_aclk_fsys_200_user",
2262                         ENABLE_ACLK_FSYS0, 0, CLK_IGNORE_UNUSED, 0),
2263
2264         /* ENABLE_ACLK_FSYS1 */
2265         GATE(CLK_ACLK_XIU_FSYSPX, "aclk_xiu_fsyspx", "mout_aclk_fsys_200_user",
2266                         ENABLE_ACLK_FSYS1, 27, CLK_IGNORE_UNUSED, 0),
2267         GATE(CLK_ACLK_AHB_USBLINKH1, "aclk_ahb_usblinkh1",
2268                         "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1,
2269                         26, CLK_IGNORE_UNUSED, 0),
2270         GATE(CLK_ACLK_SMMU_PDMA1, "aclk_smmu_pdma1", "mout_aclk_fsys_200_user",
2271                         ENABLE_ACLK_FSYS1, 25, CLK_IGNORE_UNUSED, 0),
2272         GATE(CLK_ACLK_BTS_PCIE, "aclk_bts_pcie", "mout_aclk_fsys_200_user",
2273                         ENABLE_ACLK_FSYS1, 24, CLK_IGNORE_UNUSED, 0),
2274         GATE(CLK_ACLK_AXIUS_PDMA1, "aclk_axius_pdma1",
2275                         "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1,
2276                         22, CLK_IGNORE_UNUSED, 0),
2277         GATE(CLK_ACLK_SMMU_PDMA0, "aclk_smmu_pdma0", "mout_aclk_fsys_200_user",
2278                         ENABLE_ACLK_FSYS1, 17, CLK_IGNORE_UNUSED, 0),
2279         GATE(CLK_ACLK_BTS_UFS, "aclk_bts_ufs", "mout_aclk_fsys_200_user",
2280                         ENABLE_ACLK_FSYS1, 14, CLK_IGNORE_UNUSED, 0),
2281         GATE(CLK_ACLK_BTS_USBHOST30, "aclk_bts_usbhost30",
2282                         "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1,
2283                         13, 0, 0),
2284         GATE(CLK_ACLK_BTS_USBDRD30, "aclk_bts_usbdrd30",
2285                         "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1,
2286                         12, 0, 0),
2287         GATE(CLK_ACLK_AXIUS_PDMA0, "aclk_axius_pdma0",
2288                         "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1,
2289                         11, CLK_IGNORE_UNUSED, 0),
2290         GATE(CLK_ACLK_AXIUS_USBHS, "aclk_axius_usbhs",
2291                         "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1,
2292                         10, CLK_IGNORE_UNUSED, 0),
2293         GATE(CLK_ACLK_AXIUS_FSYSSX, "aclk_axius_fsyssx",
2294                         "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1,
2295                         9, CLK_IGNORE_UNUSED, 0),
2296         GATE(CLK_ACLK_AHB2APB_FSYSP, "aclk_ahb2apb_fsysp",
2297                         "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1,
2298                         8, CLK_IGNORE_UNUSED, 0),
2299         GATE(CLK_ACLK_AHB2AXI_USBHS, "aclk_ahb2axi_usbhs",
2300                         "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1,
2301                         7, CLK_IGNORE_UNUSED, 0),
2302         GATE(CLK_ACLK_AHB_USBLINKH0, "aclk_ahb_usblinkh0",
2303                         "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1,
2304                         6, CLK_IGNORE_UNUSED, 0),
2305         GATE(CLK_ACLK_AHB_USBHS, "aclk_ahb_usbhs", "mout_aclk_fsys_200_user",
2306                         ENABLE_ACLK_FSYS1, 5, CLK_IGNORE_UNUSED, 0),
2307         GATE(CLK_ACLK_AHB_FSYSH, "aclk_ahb_fsysh", "mout_aclk_fsys_200_user",
2308                         ENABLE_ACLK_FSYS1, 4, CLK_IGNORE_UNUSED, 0),
2309         GATE(CLK_ACLK_XIU_FSYSX, "aclk_xiu_fsysx", "mout_aclk_fsys_200_user",
2310                         ENABLE_ACLK_FSYS1, 3, CLK_IGNORE_UNUSED, 0),
2311         GATE(CLK_ACLK_XIU_FSYSSX, "aclk_xiu_fsyssx", "mout_aclk_fsys_200_user",
2312                         ENABLE_ACLK_FSYS1, 2, CLK_IGNORE_UNUSED, 0),
2313         GATE(CLK_ACLK_FSYSNP_200, "aclk_fsysnp_200", "mout_aclk_fsys_200_user",
2314                         ENABLE_ACLK_FSYS1, 1, CLK_IGNORE_UNUSED, 0),
2315         GATE(CLK_ACLK_FSYSND_200, "aclk_fsysnd_200", "mout_aclk_fsys_200_user",
2316                         ENABLE_ACLK_FSYS1, 0, CLK_IGNORE_UNUSED, 0),
2317
2318         /* ENABLE_PCLK_FSYS */
2319         GATE(CLK_PCLK_PCIE_CTRL, "pclk_pcie_ctrl", "mout_aclk_fsys_200_user",
2320                         ENABLE_PCLK_FSYS, 17, CLK_IGNORE_UNUSED, 0),
2321         GATE(CLK_PCLK_SMMU_PDMA1, "pclk_smmu_pdma1", "mout_aclk_fsys_200_user",
2322                         ENABLE_PCLK_FSYS, 16, CLK_IGNORE_UNUSED, 0),
2323         GATE(CLK_PCLK_PCIE_PHY, "pclk_pcie_phy", "mout_aclk_fsys_200_user",
2324                         ENABLE_PCLK_FSYS, 14, CLK_IGNORE_UNUSED, 0),
2325         GATE(CLK_PCLK_BTS_PCIE, "pclk_bts_pcie", "mout_aclk_fsys_200_user",
2326                         ENABLE_PCLK_FSYS, 13, CLK_IGNORE_UNUSED, 0),
2327         GATE(CLK_PCLK_SMMU_PDMA0, "pclk_smmu_pdma0", "mout_aclk_fsys_200_user",
2328                         ENABLE_PCLK_FSYS, 8, CLK_IGNORE_UNUSED, 0),
2329         GATE(CLK_PCLK_BTS_UFS, "pclk_bts_ufs", "mout_aclk_fsys_200_user",
2330                         ENABLE_PCLK_FSYS, 5, 0, 0),
2331         GATE(CLK_PCLK_BTS_USBHOST30, "pclk_bts_usbhost30",
2332                         "mout_aclk_fsys_200_user", ENABLE_PCLK_FSYS, 4, 0, 0),
2333         GATE(CLK_PCLK_BTS_USBDRD30, "pclk_bts_usbdrd30",
2334                         "mout_aclk_fsys_200_user", ENABLE_PCLK_FSYS, 3, 0, 0),
2335         GATE(CLK_PCLK_GPIO_FSYS, "pclk_gpio_fsys", "mout_aclk_fsys_200_user",
2336                         ENABLE_PCLK_FSYS, 2, CLK_IGNORE_UNUSED, 0),
2337         GATE(CLK_PCLK_PMU_FSYS, "pclk_pmu_fsys", "mout_aclk_fsys_200_user",
2338                         ENABLE_PCLK_FSYS, 1, CLK_IGNORE_UNUSED, 0),
2339         GATE(CLK_PCLK_SYSREG_FSYS, "pclk_sysreg_fsys",
2340                         "mout_aclk_fsys_200_user", ENABLE_PCLK_FSYS,
2341                         0, CLK_IGNORE_UNUSED, 0),
2342
2343         /* ENABLE_SCLK_FSYS */
2344         GATE(CLK_SCLK_PCIE_100, "sclk_pcie_100", "mout_sclk_pcie_100_user",
2345                         ENABLE_SCLK_FSYS, 21, 0, 0),
2346         GATE(CLK_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK,
2347                         "phyclk_usbhost30_uhost30_pipe_pclk",
2348                         "mout_phyclk_usbhost30_uhost30_pipe_pclk_user",
2349                         ENABLE_SCLK_FSYS, 18, 0, 0),
2350         GATE(CLK_PHYCLK_USBHOST30_UHOST30_PHYCLOCK,
2351                         "phyclk_usbhost30_uhost30_phyclock",
2352                         "mout_phyclk_usbhost30_uhost30_phyclock_user",
2353                         ENABLE_SCLK_FSYS, 17, 0, 0),
2354         GATE(CLK_PHYCLK_UFS_RX1_SYMBOL, "phyclk_ufs_rx1_symbol",
2355                         "mout_phyclk_ufs_rx1_symbol_user", ENABLE_SCLK_FSYS,
2356                         16, 0, 0),
2357         GATE(CLK_PHYCLK_UFS_RX0_SYMBOL, "phyclk_ufs_rx0_symbol",
2358                         "mout_phyclk_ufs_rx0_symbol_user", ENABLE_SCLK_FSYS,
2359                         15, 0, 0),
2360         GATE(CLK_PHYCLK_UFS_TX1_SYMBOL, "phyclk_ufs_tx1_symbol",
2361                         "mout_phyclk_ufs_tx1_symbol_user", ENABLE_SCLK_FSYS,
2362                         14, 0, 0),
2363         GATE(CLK_PHYCLK_UFS_TX0_SYMBOL, "phyclk_ufs_tx0_symbol",
2364                         "mout_phyclk_ufs_tx0_symbol_user", ENABLE_SCLK_FSYS,
2365                         13, 0, 0),
2366         GATE(CLK_PHYCLK_USBHOST20_PHY_HSIC1, "phyclk_usbhost20_phy_hsic1",
2367                         "mout_phyclk_usbhost20_phy_hsic1", ENABLE_SCLK_FSYS,
2368                         12, 0, 0),
2369         GATE(CLK_PHYCLK_USBHOST20_PHY_CLK48MOHCI,
2370                         "phyclk_usbhost20_phy_clk48mohci",
2371                         "mout_phyclk_usbhost20_phy_clk48mohci_user",
2372                         ENABLE_SCLK_FSYS, 11, 0, 0),
2373         GATE(CLK_PHYCLK_USBHOST20_PHY_PHYCLOCK,
2374                         "phyclk_usbhost20_phy_phyclock",
2375                         "mout_phyclk_usbhost20_phy_phyclock_user",
2376                         ENABLE_SCLK_FSYS, 10, 0, 0),
2377         GATE(CLK_PHYCLK_USBHOST20_PHY_FREECLK,
2378                         "phyclk_usbhost20_phy_freeclk",
2379                         "mout_phyclk_usbhost20_phy_freeclk_user",
2380                         ENABLE_SCLK_FSYS, 9, 0, 0),
2381         GATE(CLK_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK,
2382                         "phyclk_usbdrd30_udrd30_pipe_pclk",
2383                         "mout_phyclk_usbdrd30_udrd30_pipe_pclk_user",
2384                         ENABLE_SCLK_FSYS, 8, 0, 0),
2385         GATE(CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK,
2386                         "phyclk_usbdrd30_udrd30_phyclock",
2387                         "mout_phyclk_usbdrd30_udrd30_phyclock_user",
2388                         ENABLE_SCLK_FSYS, 7, 0, 0),
2389         GATE(CLK_SCLK_MPHY, "sclk_mphy", "mout_sclk_mphy",
2390                         ENABLE_SCLK_FSYS, 6, 0, 0),
2391         GATE(CLK_SCLK_UFSUNIPRO, "sclk_ufsunipro", "mout_sclk_ufsunipro_user",
2392                         ENABLE_SCLK_FSYS, 5, 0, 0),
2393         GATE(CLK_SCLK_MMC2, "sclk_mmc2", "mout_sclk_mmc2_user",
2394                         ENABLE_SCLK_FSYS, 4, CLK_SET_RATE_PARENT, 0),
2395         GATE(CLK_SCLK_MMC1, "sclk_mmc1", "mout_sclk_mmc1_user",
2396                         ENABLE_SCLK_FSYS, 3, CLK_SET_RATE_PARENT, 0),
2397         GATE(CLK_SCLK_MMC0, "sclk_mmc0", "mout_sclk_mmc0_user",
2398                         ENABLE_SCLK_FSYS, 2, CLK_SET_RATE_PARENT, 0),
2399         GATE(CLK_SCLK_USBHOST30, "sclk_usbhost30", "mout_sclk_usbhost30_user",
2400                         ENABLE_SCLK_FSYS, 1, 0, 0),
2401         GATE(CLK_SCLK_USBDRD30, "sclk_usbdrd30", "mout_sclk_usbdrd30_user",
2402                         ENABLE_SCLK_FSYS, 0, 0, 0),
2403
2404         /* ENABLE_IP_FSYS0 */
2405         GATE(CLK_PCIE_PHY, "pcie_phy", "NULL", ENABLE_IP_FSYS0, 18, 0, 0),
2406         GATE(CLK_PCIE, "pcie", "sclk_pcie_100", ENABLE_IP_FSYS0, 17, 0, 0),
2407         GATE(CLK_PDMA1, "pdma1", "aclk_pdma1", ENABLE_IP_FSYS0, 15, 0, 0),
2408         GATE(CLK_PDMA0, "pdma0", "aclk_pdma0", ENABLE_IP_FSYS0, 0, 0, 0),
2409 };
2410
2411 static struct samsung_cmu_info fsys_cmu_info __initdata = {
2412         .mux_clks               = fsys_mux_clks,
2413         .nr_mux_clks            = ARRAY_SIZE(fsys_mux_clks),
2414         .gate_clks              = fsys_gate_clks,
2415         .nr_gate_clks           = ARRAY_SIZE(fsys_gate_clks),
2416         .fixed_clks             = fsys_fixed_clks,
2417         .nr_fixed_clks          = ARRAY_SIZE(fsys_fixed_clks),
2418         .nr_clk_ids             = FSYS_NR_CLK,
2419         .clk_regs               = fsys_clk_regs,
2420         .nr_clk_regs            = ARRAY_SIZE(fsys_clk_regs),
2421 };
2422
2423 static void __init exynos5433_cmu_fsys_init(struct device_node *np)
2424 {
2425         samsung_cmu_register_one(np, &fsys_cmu_info);
2426 }
2427
2428 CLK_OF_DECLARE(exynos5433_cmu_fsys, "samsung,exynos5433-cmu-fsys",
2429                 exynos5433_cmu_fsys_init);
2430
2431 /*
2432  * Register offset definitions for CMU_G2D
2433  */
2434 #define MUX_SEL_G2D0                            0x0200
2435 #define MUX_SEL_ENABLE_G2D0                     0x0300
2436 #define MUX_SEL_STAT_G2D0                       0x0400
2437 #define DIV_G2D                                 0x0600
2438 #define DIV_STAT_G2D                            0x0700
2439 #define DIV_ENABLE_ACLK_G2D                     0x0800
2440 #define DIV_ENABLE_ACLK_G2D_SECURE_SMMU_G2D     0x0804
2441 #define DIV_ENABLE_PCLK_G2D                     0x0900
2442 #define DIV_ENABLE_PCLK_G2D_SECURE_SMMU_G2D     0x0904
2443 #define DIV_ENABLE_IP_G2D0                      0x0b00
2444 #define DIV_ENABLE_IP_G2D1                      0x0b04
2445 #define DIV_ENABLE_IP_G2D_SECURE_SMMU_G2D       0x0b08
2446
2447 static unsigned long g2d_clk_regs[] __initdata = {
2448         MUX_SEL_G2D0,
2449         MUX_SEL_ENABLE_G2D0,
2450         DIV_G2D,
2451         DIV_ENABLE_ACLK_G2D,
2452         DIV_ENABLE_ACLK_G2D_SECURE_SMMU_G2D,
2453         DIV_ENABLE_PCLK_G2D,
2454         DIV_ENABLE_PCLK_G2D_SECURE_SMMU_G2D,
2455         DIV_ENABLE_IP_G2D0,
2456         DIV_ENABLE_IP_G2D1,
2457         DIV_ENABLE_IP_G2D_SECURE_SMMU_G2D,
2458 };
2459
2460 /* list of all parent clock list */
2461 PNAME(mout_aclk_g2d_266_user_p)         = { "oscclk", "aclk_g2d_266", };
2462 PNAME(mout_aclk_g2d_400_user_p)         = { "oscclk", "aclk_g2d_400", };
2463
2464 static struct samsung_mux_clock g2d_mux_clks[] __initdata = {
2465         /* MUX_SEL_G2D0 */
2466         MUX(CLK_MUX_ACLK_G2D_266_USER, "mout_aclk_g2d_266_user",
2467                         mout_aclk_g2d_266_user_p, MUX_SEL_G2D0, 4, 1),
2468         MUX(CLK_MUX_ACLK_G2D_400_USER, "mout_aclk_g2d_400_user",
2469                         mout_aclk_g2d_400_user_p, MUX_SEL_G2D0, 0, 1),
2470 };
2471
2472 static struct samsung_div_clock g2d_div_clks[] __initdata = {
2473         /* DIV_G2D */
2474         DIV(CLK_DIV_PCLK_G2D, "div_pclk_g2d", "mout_aclk_g2d_266_user",
2475                         DIV_G2D, 0, 2),
2476 };
2477
2478 static struct samsung_gate_clock g2d_gate_clks[] __initdata = {
2479         /* DIV_ENABLE_ACLK_G2D */
2480         GATE(CLK_ACLK_SMMU_MDMA1, "aclk_smmu_mdma1", "mout_aclk_g2d_266_user",
2481                         DIV_ENABLE_ACLK_G2D, 12, 0, 0),
2482         GATE(CLK_ACLK_BTS_MDMA1, "aclk_bts_mdam1", "mout_aclk_g2d_266_user",
2483                         DIV_ENABLE_ACLK_G2D, 11, 0, 0),
2484         GATE(CLK_ACLK_BTS_G2D, "aclk_bts_g2d", "mout_aclk_g2d_400_user",
2485                         DIV_ENABLE_ACLK_G2D, 10, 0, 0),
2486         GATE(CLK_ACLK_ALB_G2D, "aclk_alb_g2d", "mout_aclk_g2d_400_user",
2487                         DIV_ENABLE_ACLK_G2D, 9, 0, 0),
2488         GATE(CLK_ACLK_AXIUS_G2DX, "aclk_axius_g2dx", "mout_aclk_g2d_400_user",
2489                         DIV_ENABLE_ACLK_G2D, 8, 0, 0),
2490         GATE(CLK_ACLK_ASYNCAXI_SYSX, "aclk_asyncaxi_sysx",
2491                         "mout_aclk_g2d_400_user", DIV_ENABLE_ACLK_G2D,
2492                         7, 0, 0),
2493         GATE(CLK_ACLK_AHB2APB_G2D1P, "aclk_ahb2apb_g2d1p", "div_pclk_g2d",
2494                         DIV_ENABLE_ACLK_G2D, 6, CLK_IGNORE_UNUSED, 0),
2495         GATE(CLK_ACLK_AHB2APB_G2D0P, "aclk_ahb2apb_g2d0p", "div_pclk_g2d",
2496                         DIV_ENABLE_ACLK_G2D, 5, CLK_IGNORE_UNUSED, 0),
2497         GATE(CLK_ACLK_XIU_G2DX, "aclk_xiu_g2dx", "mout_aclk_g2d_400_user",
2498                         DIV_ENABLE_ACLK_G2D, 4, CLK_IGNORE_UNUSED, 0),
2499         GATE(CLK_ACLK_G2DNP_133, "aclk_g2dnp_133", "div_pclk_g2d",
2500                         DIV_ENABLE_ACLK_G2D, 3, CLK_IGNORE_UNUSED, 0),
2501         GATE(CLK_ACLK_G2DND_400, "aclk_g2dnd_400", "mout_aclk_g2d_400_user",
2502                         DIV_ENABLE_ACLK_G2D, 2, CLK_IGNORE_UNUSED, 0),
2503         GATE(CLK_ACLK_MDMA1, "aclk_mdma1", "mout_aclk_g2d_266_user",
2504                         DIV_ENABLE_ACLK_G2D, 1, 0, 0),
2505         GATE(CLK_ACLK_G2D, "aclk_g2d", "mout_aclk_g2d_400_user",
2506                         DIV_ENABLE_ACLK_G2D, 0, 0, 0),
2507
2508         /* DIV_ENABLE_ACLK_G2D_SECURE_SMMU_G2D */
2509         GATE(CLK_ACLK_SMMU_G2D, "aclk_smmu_g2d", "mout_aclk_g2d_400_user",
2510                 DIV_ENABLE_ACLK_G2D_SECURE_SMMU_G2D, 0, 0, 0),
2511
2512         /* DIV_ENABLE_PCLK_G2D */
2513         GATE(CLK_PCLK_SMMU_MDMA1, "pclk_smmu_mdma1", "div_pclk_g2d",
2514                         DIV_ENABLE_PCLK_G2D, 7, 0, 0),
2515         GATE(CLK_PCLK_BTS_MDMA1, "pclk_bts_mdam1", "div_pclk_g2d",
2516                         DIV_ENABLE_PCLK_G2D, 6, 0, 0),
2517         GATE(CLK_PCLK_BTS_G2D, "pclk_bts_g2d", "div_pclk_g2d",
2518                         DIV_ENABLE_PCLK_G2D, 5, 0, 0),
2519         GATE(CLK_PCLK_ALB_G2D, "pclk_alb_g2d", "div_pclk_g2d",
2520                         DIV_ENABLE_PCLK_G2D, 4, 0, 0),
2521         GATE(CLK_PCLK_ASYNCAXI_SYSX, "pclk_asyncaxi_sysx", "div_pclk_g2d",
2522                         DIV_ENABLE_PCLK_G2D, 3, 0, 0),
2523         GATE(CLK_PCLK_PMU_G2D, "pclk_pmu_g2d", "div_pclk_g2d",
2524                         DIV_ENABLE_PCLK_G2D, 2, CLK_IGNORE_UNUSED, 0),
2525         GATE(CLK_PCLK_SYSREG_G2D, "pclk_sysreg_g2d", "div_pclk_g2d",
2526                         DIV_ENABLE_PCLK_G2D, 1, CLK_IGNORE_UNUSED, 0),
2527         GATE(CLK_PCLK_G2D, "pclk_g2d", "div_pclk_g2d", DIV_ENABLE_PCLK_G2D,
2528                         0, 0, 0),
2529
2530         /* DIV_ENABLE_PCLK_G2D_SECURE_SMMU_G2D */
2531         GATE(CLK_PCLK_SMMU_G2D, "pclk_smmu_g2d", "div_pclk_g2d",
2532                 DIV_ENABLE_PCLK_G2D_SECURE_SMMU_G2D, 0, 0, 0),
2533 };
2534
2535 static struct samsung_cmu_info g2d_cmu_info __initdata = {
2536         .mux_clks               = g2d_mux_clks,
2537         .nr_mux_clks            = ARRAY_SIZE(g2d_mux_clks),
2538         .div_clks               = g2d_div_clks,
2539         .nr_div_clks            = ARRAY_SIZE(g2d_div_clks),
2540         .gate_clks              = g2d_gate_clks,
2541         .nr_gate_clks           = ARRAY_SIZE(g2d_gate_clks),
2542         .nr_clk_ids             = G2D_NR_CLK,
2543         .clk_regs               = g2d_clk_regs,
2544         .nr_clk_regs            = ARRAY_SIZE(g2d_clk_regs),
2545 };
2546
2547 static void __init exynos5433_cmu_g2d_init(struct device_node *np)
2548 {
2549         samsung_cmu_register_one(np, &g2d_cmu_info);
2550 }
2551
2552 CLK_OF_DECLARE(exynos5433_cmu_g2d, "samsung,exynos5433-cmu-g2d",
2553                 exynos5433_cmu_g2d_init);
2554
2555 /*
2556  * Register offset definitions for CMU_DISP
2557  */
2558 #define DISP_PLL_LOCK                   0x0000
2559 #define DISP_PLL_CON0                   0x0100
2560 #define DISP_PLL_CON1                   0x0104
2561 #define DISP_PLL_FREQ_DET               0x0108
2562 #define MUX_SEL_DISP0                   0x0200
2563 #define MUX_SEL_DISP1                   0x0204
2564 #define MUX_SEL_DISP2                   0x0208
2565 #define MUX_SEL_DISP3                   0x020c
2566 #define MUX_SEL_DISP4                   0x0210
2567 #define MUX_ENABLE_DISP0                0x0300
2568 #define MUX_ENABLE_DISP1                0x0304
2569 #define MUX_ENABLE_DISP2                0x0308
2570 #define MUX_ENABLE_DISP3                0x030c
2571 #define MUX_ENABLE_DISP4                0x0310
2572 #define MUX_STAT_DISP0                  0x0400
2573 #define MUX_STAT_DISP1                  0x0404
2574 #define MUX_STAT_DISP2                  0x0408
2575 #define MUX_STAT_DISP3                  0x040c
2576 #define MUX_STAT_DISP4                  0x0410
2577 #define MUX_IGNORE_DISP2                0x0508
2578 #define DIV_DISP                        0x0600
2579 #define DIV_DISP_PLL_FREQ_DET           0x0604
2580 #define DIV_STAT_DISP                   0x0700
2581 #define DIV_STAT_DISP_PLL_FREQ_DET      0x0704
2582 #define ENABLE_ACLK_DISP0               0x0800
2583 #define ENABLE_ACLK_DISP1               0x0804
2584 #define ENABLE_PCLK_DISP                0x0900
2585 #define ENABLE_SCLK_DISP                0x0a00
2586 #define ENABLE_IP_DISP0                 0x0b00
2587 #define ENABLE_IP_DISP1                 0x0b04
2588 #define CLKOUT_CMU_DISP                 0x0c00
2589 #define CLKOUT_CMU_DISP_DIV_STAT        0x0c04
2590
2591 static unsigned long disp_clk_regs[] __initdata = {
2592         DISP_PLL_LOCK,
2593         DISP_PLL_CON0,
2594         DISP_PLL_CON1,
2595         DISP_PLL_FREQ_DET,
2596         MUX_SEL_DISP0,
2597         MUX_SEL_DISP1,
2598         MUX_SEL_DISP2,
2599         MUX_SEL_DISP3,
2600         MUX_SEL_DISP4,
2601         MUX_ENABLE_DISP0,
2602         MUX_ENABLE_DISP1,
2603         MUX_ENABLE_DISP2,
2604         MUX_ENABLE_DISP3,
2605         MUX_ENABLE_DISP4,
2606         MUX_IGNORE_DISP2,
2607         DIV_DISP,
2608         DIV_DISP_PLL_FREQ_DET,
2609         ENABLE_ACLK_DISP0,
2610         ENABLE_ACLK_DISP1,
2611         ENABLE_PCLK_DISP,
2612         ENABLE_SCLK_DISP,
2613         ENABLE_IP_DISP0,
2614         ENABLE_IP_DISP1,
2615         CLKOUT_CMU_DISP,
2616         CLKOUT_CMU_DISP_DIV_STAT,
2617 };
2618
2619 /* list of all parent clock list */
2620 PNAME(mout_disp_pll_p)                  = { "oscclk", "fout_disp_pll", };
2621 PNAME(mout_sclk_dsim1_user_p)           = { "oscclk", "sclk_dsim1_disp", };
2622 PNAME(mout_sclk_dsim0_user_p)           = { "oscclk", "sclk_dsim0_disp", };
2623 PNAME(mout_sclk_dsd_user_p)             = { "oscclk", "sclk_dsd_disp", };
2624 PNAME(mout_sclk_decon_tv_eclk_user_p)   = { "oscclk",
2625                                             "sclk_decon_tv_eclk_disp", };
2626 PNAME(mout_sclk_decon_vclk_user_p)      = { "oscclk",
2627                                             "sclk_decon_vclk_disp", };
2628 PNAME(mout_sclk_decon_eclk_user_p)      = { "oscclk",
2629                                             "sclk_decon_eclk_disp", };
2630 PNAME(mout_sclk_decon_tv_vlkc_user_p)   = { "oscclk",
2631                                             "sclk_decon_tv_vclk_disp", };
2632 PNAME(mout_aclk_disp_333_user_p)        = { "oscclk", "aclk_disp_333", };
2633
2634 PNAME(mout_phyclk_mipidphy1_bitclkdiv8_user_p)  = { "oscclk",
2635                                         "phyclk_mipidphy1_bitclkdiv8_phy", };
2636 PNAME(mout_phyclk_mipidphy1_rxclkesc0_user_p)   = { "oscclk",
2637                                         "phyclk_mipidphy1_rxclkesc0_phy", };
2638 PNAME(mout_phyclk_mipidphy0_bitclkdiv8_user_p)  = { "oscclk",
2639                                         "phyclk_mipidphy0_bitclkdiv8_phy", };
2640 PNAME(mout_phyclk_mipidphy0_rxclkesc0_user_p)   = { "oscclk",
2641                                         "phyclk_mipidphy0_rxclkesc0_phy", };
2642 PNAME(mout_phyclk_hdmiphy_tmds_clko_user_p)     = { "oscclk",
2643                                         "phyclk_hdmiphy_tmds_clko_phy", };
2644 PNAME(mout_phyclk_hdmiphy_pixel_clko_user_p)    = { "oscclk",
2645                                         "phyclk_hdmiphy_pixel_clko_phy", };
2646
2647 PNAME(mout_sclk_dsim0_p)                = { "mout_disp_pll",
2648                                             "mout_sclk_dsim0_user", };
2649 PNAME(mout_sclk_decon_tv_eclk_p)        = { "mout_disp_pll",
2650                                             "mout_sclk_decon_tv_eclk_user", };
2651 PNAME(mout_sclk_decon_vclk_p)           = { "mout_disp_pll",
2652                                             "mout_sclk_decon_vclk_user", };
2653 PNAME(mout_sclk_decon_eclk_p)           = { "mout_disp_pll",
2654                                             "mout_sclk_decon_eclk_user", };
2655
2656 PNAME(mout_sclk_dsim1_b_disp_p)         = { "mout_sclk_dsim1_a_disp",
2657                                             "mout_sclk_dsim1_user", };
2658 PNAME(mout_sclk_decon_tv_vclk_c_disp_p) = {
2659                                 "mout_phyclk_hdmiphy_pixel_clko_user",
2660                                 "mout_sclk_decon_tv_vclk_b_disp", };
2661 PNAME(mout_sclk_decon_tv_vclk_b_disp_p) = { "mout_sclk_decon_tv_vclk_a_disp",
2662                                             "mout_sclk_decon_tv_vclk_user", };
2663
2664 static struct samsung_pll_clock disp_pll_clks[] __initdata = {
2665         PLL(pll_35xx, CLK_FOUT_DISP_PLL, "fout_disp_pll", "oscclk",
2666                 DISP_PLL_LOCK, DISP_PLL_CON0, exynos5443_pll_rates),
2667 };
2668
2669 static struct samsung_fixed_factor_clock disp_fixed_factor_clks[] __initdata = {
2670         /*
2671          * sclk_rgb_{vclk|tv_vclk} is half clock of sclk_decon_{vclk|tv_vclk}.
2672          * The divider has fixed value (2) between sclk_rgb_{vclk|tv_vclk}
2673          * and sclk_decon_{vclk|tv_vclk}.
2674          */
2675         FFACTOR(CLK_SCLK_RGB_VCLK, "sclk_rgb_vclk", "sclk_decon_vclk",
2676                         1, 2, 0),
2677         FFACTOR(CLK_SCLK_RGB_TV_VCLK, "sclk_rgb_tv_vclk", "sclk_decon_tv_vclk",
2678                         1, 2, 0),
2679 };
2680
2681 static struct samsung_fixed_rate_clock disp_fixed_clks[] __initdata = {
2682         /* PHY clocks from MIPI_DPHY1 */
2683         FRATE(0, "phyclk_mipidphy1_bitclkdiv8_phy", NULL, CLK_IS_ROOT,
2684                         188000000),
2685         FRATE(0, "phyclk_mipidphy1_rxclkesc0_phy", NULL, CLK_IS_ROOT,
2686                         100000000),
2687         /* PHY clocks from MIPI_DPHY0 */
2688         FRATE(0, "phyclk_mipidphy0_bitclkdiv8_phy", NULL, CLK_IS_ROOT,
2689                         188000000),
2690         FRATE(0, "phyclk_mipidphy0_rxclkesc0_phy", NULL, CLK_IS_ROOT,
2691                         100000000),
2692         /* PHY clocks from HDMI_PHY */
2693         FRATE(CLK_PHYCLK_HDMIPHY_TMDS_CLKO_PHY, "phyclk_hdmiphy_tmds_clko_phy",
2694                         NULL, CLK_IS_ROOT, 300000000),
2695         FRATE(CLK_PHYCLK_HDMIPHY_PIXEL_CLKO_PHY, "phyclk_hdmiphy_pixel_clko_phy",
2696                         NULL, CLK_IS_ROOT, 166000000),
2697 };
2698
2699 static struct samsung_mux_clock disp_mux_clks[] __initdata = {
2700         /* MUX_SEL_DISP0 */
2701         MUX(CLK_MOUT_DISP_PLL, "mout_disp_pll", mout_disp_pll_p, MUX_SEL_DISP0,
2702                         0, 1),
2703
2704         /* MUX_SEL_DISP1 */
2705         MUX(CLK_MOUT_SCLK_DSIM1_USER, "mout_sclk_dsim1_user",
2706                         mout_sclk_dsim1_user_p, MUX_SEL_DISP1, 28, 1),
2707         MUX(CLK_MOUT_SCLK_DSIM0_USER, "mout_sclk_dsim0_user",
2708                         mout_sclk_dsim0_user_p, MUX_SEL_DISP1, 24, 1),
2709         MUX(CLK_MOUT_SCLK_DSD_USER, "mout_sclk_dsd_user", mout_sclk_dsd_user_p,
2710                         MUX_SEL_DISP1, 20, 1),
2711         MUX(CLK_MOUT_SCLK_DECON_TV_ECLK_USER, "mout_sclk_decon_tv_eclk_user",
2712                         mout_sclk_decon_tv_eclk_user_p, MUX_SEL_DISP1, 16, 1),
2713         MUX(CLK_MOUT_SCLK_DECON_VCLK_USER, "mout_sclk_decon_vclk_user",
2714                         mout_sclk_decon_vclk_user_p, MUX_SEL_DISP1, 12, 1),
2715         MUX(CLK_MOUT_SCLK_DECON_ECLK_USER, "mout_sclk_decon_eclk_user",
2716                         mout_sclk_decon_eclk_user_p, MUX_SEL_DISP1, 8, 1),
2717         MUX(CLK_MOUT_SCLK_DECON_TV_VCLK_USER, "mout_sclk_decon_tv_vclk_user",
2718                         mout_sclk_decon_tv_vlkc_user_p, MUX_SEL_DISP1, 4, 1),
2719         MUX(CLK_MOUT_ACLK_DISP_333_USER, "mout_aclk_disp_333_user",
2720                         mout_aclk_disp_333_user_p, MUX_SEL_DISP1, 0, 1),
2721
2722         /* MUX_SEL_DISP2 */
2723         MUX(CLK_MOUT_PHYCLK_MIPIDPHY1_BITCLKDIV8_USER,
2724                         "mout_phyclk_mipidphy1_bitclkdiv8_user",
2725                         mout_phyclk_mipidphy1_bitclkdiv8_user_p, MUX_SEL_DISP2,
2726                         20, 1),
2727         MUX(CLK_MOUT_PHYCLK_MIPIDPHY1_RXCLKESC0_USER,
2728                         "mout_phyclk_mipidphy1_rxclkesc0_user",
2729                         mout_phyclk_mipidphy1_rxclkesc0_user_p, MUX_SEL_DISP2,
2730                         16, 1),
2731         MUX(CLK_MOUT_PHYCLK_MIPIDPHY0_BITCLKDIV8_USER,
2732                         "mout_phyclk_mipidphy0_bitclkdiv8_user",
2733                         mout_phyclk_mipidphy0_bitclkdiv8_user_p, MUX_SEL_DISP2,
2734                         12, 1),
2735         MUX(CLK_MOUT_PHYCLK_MIPIDPHY0_RXCLKESC0_USER,
2736                         "mout_phyclk_mipidphy0_rxclkesc0_user",
2737                         mout_phyclk_mipidphy0_rxclkesc0_user_p, MUX_SEL_DISP2,
2738                         8, 1),
2739         MUX(CLK_MOUT_PHYCLK_HDMIPHY_TMDS_CLKO_USER,
2740                         "mout_phyclk_hdmiphy_tmds_clko_user",
2741                         mout_phyclk_hdmiphy_tmds_clko_user_p, MUX_SEL_DISP2,
2742                         4, 1),
2743         MUX(CLK_MOUT_PHYCLK_HDMIPHY_PIXEL_CLKO_USER,
2744                         "mout_phyclk_hdmiphy_pixel_clko_user",
2745                         mout_phyclk_hdmiphy_pixel_clko_user_p, MUX_SEL_DISP2,
2746                         0, 1),
2747
2748         /* MUX_SEL_DISP3 */
2749         MUX(CLK_MOUT_SCLK_DSIM0, "mout_sclk_dsim0", mout_sclk_dsim0_p,
2750                         MUX_SEL_DISP3, 12, 1),
2751         MUX(CLK_MOUT_SCLK_DECON_TV_ECLK, "mout_sclk_decon_tv_eclk",
2752                         mout_sclk_decon_tv_eclk_p, MUX_SEL_DISP3, 8, 1),
2753         MUX(CLK_MOUT_SCLK_DECON_VCLK, "mout_sclk_decon_vclk",
2754                         mout_sclk_decon_vclk_p, MUX_SEL_DISP3, 4, 1),
2755         MUX(CLK_MOUT_SCLK_DECON_ECLK, "mout_sclk_decon_eclk",
2756                         mout_sclk_decon_eclk_p, MUX_SEL_DISP3, 0, 1),
2757
2758         /* MUX_SEL_DISP4 */
2759         MUX(CLK_MOUT_SCLK_DSIM1_B_DISP, "mout_sclk_dsim1_b_disp",
2760                         mout_sclk_dsim1_b_disp_p, MUX_SEL_DISP4, 16, 1),
2761         MUX(CLK_MOUT_SCLK_DSIM1_A_DISP, "mout_sclk_dsim1_a_disp",
2762                         mout_sclk_dsim0_p, MUX_SEL_DISP4, 12, 1),
2763         MUX(CLK_MOUT_SCLK_DECON_TV_VCLK_C_DISP,
2764                         "mout_sclk_decon_tv_vclk_c_disp",
2765                         mout_sclk_decon_tv_vclk_c_disp_p, MUX_SEL_DISP4, 8, 1),
2766         MUX(CLK_MOUT_SCLK_DECON_TV_VCLK_B_DISP,
2767                         "mout_sclk_decon_tv_vclk_b_disp",
2768                         mout_sclk_decon_tv_vclk_b_disp_p, MUX_SEL_DISP4, 4, 1),
2769         MUX(CLK_MOUT_SCLK_DECON_TV_VCLK_A_DISP,
2770                         "mout_sclk_decon_tv_vclk_a_disp",
2771                         mout_sclk_decon_vclk_p, MUX_SEL_DISP4, 0, 1),
2772 };
2773
2774 static struct samsung_div_clock disp_div_clks[] __initdata = {
2775         /* DIV_DISP */
2776         DIV(CLK_DIV_SCLK_DSIM1_DISP, "div_sclk_dsim1_disp",
2777                         "mout_sclk_dsim1_b_disp", DIV_DISP, 24, 3),
2778         DIV(CLK_DIV_SCLK_DECON_TV_VCLK_DISP, "div_sclk_decon_tv_vclk_disp",
2779                         "mout_sclk_decon_tv_vclk_c_disp", DIV_DISP, 20, 3),
2780         DIV(CLK_DIV_SCLK_DSIM0_DISP, "div_sclk_dsim0_disp", "mout_sclk_dsim0",
2781                         DIV_DISP, 16, 3),
2782         DIV(CLK_DIV_SCLK_DECON_TV_ECLK_DISP, "div_sclk_decon_tv_eclk_disp",
2783                         "mout_sclk_decon_tv_eclk", DIV_DISP, 12, 3),
2784         DIV(CLK_DIV_SCLK_DECON_VCLK_DISP, "div_sclk_decon_vclk_disp",
2785                         "mout_sclk_decon_vclk", DIV_DISP, 8, 3),
2786         DIV(CLK_DIV_SCLK_DECON_ECLK_DISP, "div_sclk_decon_eclk_disp",
2787                         "mout_sclk_decon_eclk", DIV_DISP, 4, 3),
2788         DIV(CLK_DIV_PCLK_DISP, "div_pclk_disp", "mout_aclk_disp_333_user",
2789                         DIV_DISP, 0, 2),
2790 };
2791
2792 static struct samsung_gate_clock disp_gate_clks[] __initdata = {
2793         /* ENABLE_ACLK_DISP0 */
2794         GATE(CLK_ACLK_DECON_TV, "aclk_decon_tv", "mout_aclk_disp_333_user",
2795                         ENABLE_ACLK_DISP0, 2, 0, 0),
2796         GATE(CLK_ACLK_DECON, "aclk_decon", "mout_aclk_disp_333_user",
2797                         ENABLE_ACLK_DISP0, 0, 0, 0),
2798
2799         /* ENABLE_ACLK_DISP1 */
2800         GATE(CLK_ACLK_SMMU_TV1X, "aclk_smmu_tv1x", "mout_aclk_disp_333_user",
2801                         ENABLE_ACLK_DISP1, 25, 0, 0),
2802         GATE(CLK_ACLK_SMMU_TV0X, "aclk_smmu_tv0x", "mout_aclk_disp_333_user",
2803                         ENABLE_ACLK_DISP1, 24, 0, 0),
2804         GATE(CLK_ACLK_SMMU_DECON1X, "aclk_smmu_decon1x",
2805                         "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 23, 0, 0),
2806         GATE(CLK_ACLK_SMMU_DECON0X, "aclk_smmu_decon0x",
2807                         "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 22, 0, 0),
2808         GATE(CLK_ACLK_BTS_DECON_TV_M3, "aclk_bts_decon_tv_m3",
2809                         "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 21, 0, 0),
2810         GATE(CLK_ACLK_BTS_DECON_TV_M2, "aclk_bts_decon_tv_m2",
2811                         "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 20, 0, 0),
2812         GATE(CLK_ACLK_BTS_DECON_TV_M1, "aclk_bts_decon_tv_m1",
2813                         "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 19, 0, 0),
2814         GATE(CLK_ACLK_BTS_DECON_TV_M0, "aclk-bts_decon_tv_m0",
2815                         "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 18, 0, 0),
2816         GATE(CLK_ACLK_BTS_DECON_NM4, "aclk_bts_decon_nm4",
2817                         "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 17, 0, 0),
2818         GATE(CLK_ACLK_BTS_DECON_NM3, "aclk_bts_decon_nm3",
2819                         "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 16, 0, 0),
2820         GATE(CLK_ACLK_BTS_DECON_NM2, "aclk_bts_decon_nm2",
2821                         "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 15, 0, 0),
2822         GATE(CLK_ACLK_BTS_DECON_NM1, "aclk_bts_decon_nm1",
2823                         "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 14, 0, 0),
2824         GATE(CLK_ACLK_BTS_DECON_NM0, "aclk_bts_decon_nm0",
2825                         "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 13, 0, 0),
2826         GATE(CLK_ACLK_AHB2APB_DISPSFR2P, "aclk_ahb2apb_dispsfr2p",
2827                         "div_pclk_disp", ENABLE_ACLK_DISP1,
2828                         12, CLK_IGNORE_UNUSED, 0),
2829         GATE(CLK_ACLK_AHB2APB_DISPSFR1P, "aclk_ahb2apb_dispsfr1p",
2830                         "div_pclk_disp", ENABLE_ACLK_DISP1,
2831                         11, CLK_IGNORE_UNUSED, 0),
2832         GATE(CLK_ACLK_AHB2APB_DISPSFR0P, "aclk_ahb2apb_dispsfr0p",
2833                         "div_pclk_disp", ENABLE_ACLK_DISP1,
2834                         10, CLK_IGNORE_UNUSED, 0),
2835         GATE(CLK_ACLK_AHB_DISPH, "aclk_ahb_disph", "div_pclk_disp",
2836                         ENABLE_ACLK_DISP1, 8, CLK_IGNORE_UNUSED, 0),
2837         GATE(CLK_ACLK_XIU_TV1X, "aclk_xiu_tv1x", "mout_aclk_disp_333_user",
2838                         ENABLE_ACLK_DISP1, 7, 0, 0),
2839         GATE(CLK_ACLK_XIU_TV0X, "aclk_xiu_tv0x", "mout_aclk_disp_333_user",
2840                         ENABLE_ACLK_DISP1, 6, 0, 0),
2841         GATE(CLK_ACLK_XIU_DECON1X, "aclk_xiu_decon1x",
2842                         "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 5, 0, 0),
2843         GATE(CLK_ACLK_XIU_DECON0X, "aclk_xiu_decon0x",
2844                         "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 4, 0, 0),
2845         GATE(CLK_ACLK_XIU_DISP1X, "aclk_xiu_disp1x", "mout_aclk_disp_333_user",
2846                         ENABLE_ACLK_DISP1, 3, CLK_IGNORE_UNUSED, 0),
2847         GATE(CLK_ACLK_XIU_DISPNP_100, "aclk_xiu_dispnp_100", "div_pclk_disp",
2848                         ENABLE_ACLK_DISP1, 2, CLK_IGNORE_UNUSED, 0),
2849         GATE(CLK_ACLK_DISP1ND_333, "aclk_disp1nd_333",
2850                         "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 1,
2851                         CLK_IGNORE_UNUSED, 0),
2852         GATE(CLK_ACLK_DISP0ND_333, "aclk_disp0nd_333",
2853                         "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1,
2854                         0, CLK_IGNORE_UNUSED, 0),
2855
2856         /* ENABLE_PCLK_DISP */
2857         GATE(CLK_PCLK_SMMU_TV1X, "pclk_smmu_tv1x", "div_pclk_disp",
2858                         ENABLE_PCLK_DISP, 23, 0, 0),
2859         GATE(CLK_PCLK_SMMU_TV0X, "pclk_smmu_tv0x", "div_pclk_disp",
2860                         ENABLE_PCLK_DISP, 22, 0, 0),
2861         GATE(CLK_PCLK_SMMU_DECON1X, "pclk_smmu_decon1x", "div_pclk_disp",
2862                         ENABLE_PCLK_DISP, 21, 0, 0),
2863         GATE(CLK_PCLK_SMMU_DECON0X, "pclk_smmu_decon0x", "div_pclk_disp",
2864                         ENABLE_PCLK_DISP, 20, 0, 0),
2865         GATE(CLK_PCLK_BTS_DECON_TV_M3, "pclk_bts_decon_tv_m3", "div_pclk_disp",
2866                         ENABLE_PCLK_DISP, 19, 0, 0),
2867         GATE(CLK_PCLK_BTS_DECON_TV_M2, "pclk_bts_decon_tv_m2", "div_pclk_disp",
2868                         ENABLE_PCLK_DISP, 18, 0, 0),
2869         GATE(CLK_PCLK_BTS_DECON_TV_M1, "pclk_bts_decon_tv_m1", "div_pclk_disp",
2870                         ENABLE_PCLK_DISP, 17, 0, 0),
2871         GATE(CLK_PCLK_BTS_DECON_TV_M0, "pclk_bts_decon_tv_m0", "div_pclk_disp",
2872                         ENABLE_PCLK_DISP, 16, 0, 0),
2873         GATE(CLK_PCLK_BTS_DECONM4, "pclk_bts_deconm4", "div_pclk_disp",
2874                         ENABLE_PCLK_DISP, 15, 0, 0),
2875         GATE(CLK_PCLK_BTS_DECONM3, "pclk_bts_deconm3", "div_pclk_disp",
2876                         ENABLE_PCLK_DISP, 14, 0, 0),
2877         GATE(CLK_PCLK_BTS_DECONM2, "pclk_bts_deconm2", "div_pclk_disp",
2878                         ENABLE_PCLK_DISP, 13, 0, 0),
2879         GATE(CLK_PCLK_BTS_DECONM1, "pclk_bts_deconm1", "div_pclk_disp",
2880                         ENABLE_PCLK_DISP, 12, 0, 0),
2881         GATE(CLK_PCLK_BTS_DECONM0, "pclk_bts_deconm0", "div_pclk_disp",
2882                         ENABLE_PCLK_DISP, 11, 0, 0),
2883         GATE(CLK_PCLK_MIC1, "pclk_mic1", "div_pclk_disp",
2884                         ENABLE_PCLK_DISP, 10, 0, 0),
2885         GATE(CLK_PCLK_PMU_DISP, "pclk_pmu_disp", "div_pclk_disp",
2886                         ENABLE_PCLK_DISP, 9, CLK_IGNORE_UNUSED, 0),
2887         GATE(CLK_PCLK_SYSREG_DISP, "pclk_sysreg_disp", "div_pclk_disp",
2888                         ENABLE_PCLK_DISP, 8, CLK_IGNORE_UNUSED, 0),
2889         GATE(CLK_PCLK_HDMIPHY, "pclk_hdmiphy", "div_pclk_disp",
2890                         ENABLE_PCLK_DISP, 7, 0, 0),
2891         GATE(CLK_PCLK_HDMI, "pclk_hdmi", "div_pclk_disp",
2892                         ENABLE_PCLK_DISP, 6, 0, 0),
2893         GATE(CLK_PCLK_MIC0, "pclk_mic0", "div_pclk_disp",
2894                         ENABLE_PCLK_DISP, 5, 0, 0),
2895         GATE(CLK_PCLK_DSIM1, "pclk_dsim1", "div_pclk_disp",
2896                         ENABLE_PCLK_DISP, 3, 0, 0),
2897         GATE(CLK_PCLK_DSIM0, "pclk_dsim0", "div_pclk_disp",
2898                         ENABLE_PCLK_DISP, 2, 0, 0),
2899         GATE(CLK_PCLK_DECON_TV, "pclk_decon_tv", "div_pclk_disp",
2900                         ENABLE_PCLK_DISP, 1, 0, 0),
2901         GATE(CLK_PCLK_DECON, "pclk_decon", "div_pclk_disp",
2902                         ENABLE_PCLK_DISP, 0, 0, 0),
2903
2904         /* ENABLE_SCLK_DISP */
2905         GATE(CLK_PHYCLK_MIPIDPHY1_BITCLKDIV8, "phyclk_mipidphy1_bitclkdiv8",
2906                         "mout_phyclk_mipidphy1_bitclkdiv8_user",
2907                         ENABLE_SCLK_DISP, 26, 0, 0),
2908         GATE(CLK_PHYCLK_MIPIDPHY1_RXCLKESC0, "phyclk_mipidphy1_rxclkesc0",
2909                         "mout_phyclk_mipidphy1_rxclkesc0_user",
2910                         ENABLE_SCLK_DISP, 25, 0, 0),
2911         GATE(CLK_SCLK_RGB_TV_VCLK_TO_DSIM1, "sclk_rgb_tv_vclk_to_dsim1",
2912                         "sclk_rgb_tv_vclk", ENABLE_SCLK_DISP, 24, 0, 0),
2913         GATE(CLK_SCLK_RGB_TV_VCLK_TO_MIC1, "sclk_rgb_tv_vclk_to_mic1",
2914                         "sclk_rgb_tv_vclk", ENABLE_SCLK_DISP, 23, 0, 0),
2915         GATE(CLK_SCLK_DSIM1, "sclk_dsim1", "div_sclk_dsim1_disp",
2916                         ENABLE_SCLK_DISP, 22, 0, 0),
2917         GATE(CLK_SCLK_DECON_TV_VCLK, "sclk_decon_tv_vclk",
2918                         "div_sclk_decon_tv_vclk_disp",
2919                         ENABLE_SCLK_DISP, 21, 0, 0),
2920         GATE(CLK_PHYCLK_MIPIDPHY0_BITCLKDIV8, "phyclk_mipidphy0_bitclkdiv8",
2921                         "mout_phyclk_mipidphy0_bitclkdiv8_user",
2922                         ENABLE_SCLK_DISP, 15, 0, 0),
2923         GATE(CLK_PHYCLK_MIPIDPHY0_RXCLKESC0, "phyclk_mipidphy0_rxclkesc0",
2924                         "mout_phyclk_mipidphy0_rxclkesc0_user",
2925                         ENABLE_SCLK_DISP, 14, 0, 0),
2926         GATE(CLK_PHYCLK_HDMIPHY_TMDS_CLKO, "phyclk_hdmiphy_tmds_clko",
2927                         "mout_phyclk_hdmiphy_tmds_clko_user",
2928                         ENABLE_SCLK_DISP, 13, 0, 0),
2929         GATE(CLK_PHYCLK_HDMI_PIXEL, "phyclk_hdmi_pixel",
2930                         "sclk_rgb_tv_vclk", ENABLE_SCLK_DISP, 12, 0, 0),
2931         GATE(CLK_SCLK_RGB_VCLK_TO_SMIES, "sclk_rgb_vclk_to_smies",
2932                         "sclk_rgb_vclk", ENABLE_SCLK_DISP, 11, 0, 0),
2933         GATE(CLK_SCLK_RGB_VCLK_TO_DSIM0, "sclk_rgb_vclk_to_dsim0",
2934                         "sclk_rgb_vclk", ENABLE_SCLK_DISP, 9, 0, 0),
2935         GATE(CLK_SCLK_RGB_VCLK_TO_MIC0, "sclk_rgb_vclk_to_mic0",
2936                         "sclk_rgb_vclk", ENABLE_SCLK_DISP, 8, 0, 0),
2937         GATE(CLK_SCLK_DSD, "sclk_dsd", "mout_sclk_dsd_user",
2938                         ENABLE_SCLK_DISP, 7, 0, 0),
2939         GATE(CLK_SCLK_HDMI_SPDIF, "sclk_hdmi_spdif", "sclk_hdmi_spdif_disp",
2940                         ENABLE_SCLK_DISP, 6, 0, 0),
2941         GATE(CLK_SCLK_DSIM0, "sclk_dsim0", "div_sclk_dsim0_disp",
2942                         ENABLE_SCLK_DISP, 5, 0, 0),
2943         GATE(CLK_SCLK_DECON_TV_ECLK, "sclk_decon_tv_eclk",
2944                         "div_sclk_decon_tv_eclk_disp",
2945                         ENABLE_SCLK_DISP, 4, 0, 0),
2946         GATE(CLK_SCLK_DECON_VCLK, "sclk_decon_vclk",
2947                         "div_sclk_decon_vclk_disp", ENABLE_SCLK_DISP, 3, 0, 0),
2948         GATE(CLK_SCLK_DECON_ECLK, "sclk_decon_eclk",
2949                         "div_sclk_decon_eclk_disp", ENABLE_SCLK_DISP, 2, 0, 0),
2950 };
2951
2952 static struct samsung_cmu_info disp_cmu_info __initdata = {
2953         .pll_clks               = disp_pll_clks,
2954         .nr_pll_clks            = ARRAY_SIZE(disp_pll_clks),
2955         .mux_clks               = disp_mux_clks,
2956         .nr_mux_clks            = ARRAY_SIZE(disp_mux_clks),
2957         .div_clks               = disp_div_clks,
2958         .nr_div_clks            = ARRAY_SIZE(disp_div_clks),
2959         .gate_clks              = disp_gate_clks,
2960         .nr_gate_clks           = ARRAY_SIZE(disp_gate_clks),
2961         .fixed_clks             = disp_fixed_clks,
2962         .nr_fixed_clks          = ARRAY_SIZE(disp_fixed_clks),
2963         .fixed_factor_clks      = disp_fixed_factor_clks,
2964         .nr_fixed_factor_clks   = ARRAY_SIZE(disp_fixed_factor_clks),
2965         .nr_clk_ids             = DISP_NR_CLK,
2966 };
2967
2968 static void __init exynos5433_cmu_disp_init(struct device_node *np)
2969 {
2970         samsung_cmu_register_one(np, &disp_cmu_info);
2971
2972         if (of_get_property(np, "power-domains", NULL))
2973                 exynos5433_cmu_pd_handler_init(np, disp_clk_regs,
2974                                 ARRAY_SIZE(disp_clk_regs));
2975 }
2976
2977 CLK_OF_DECLARE(exynos5433_cmu_disp, "samsung,exynos5433-cmu-disp",
2978                 exynos5433_cmu_disp_init);
2979
2980 /*
2981  * Register offset definitions for CMU_AUD
2982  */
2983 #define MUX_SEL_AUD0                    0x0200
2984 #define MUX_SEL_AUD1                    0x0204
2985 #define MUX_ENABLE_AUD0                 0x0300
2986 #define MUX_ENABLE_AUD1                 0x0304
2987 #define MUX_STAT_AUD0                   0x0400
2988 #define DIV_AUD0                        0x0600
2989 #define DIV_AUD1                        0x0604
2990 #define DIV_STAT_AUD0                   0x0700
2991 #define DIV_STAT_AUD1                   0x0704
2992 #define ENABLE_ACLK_AUD                 0x0800
2993 #define ENABLE_PCLK_AUD                 0x0900
2994 #define ENABLE_SCLK_AUD0                0x0a00
2995 #define ENABLE_SCLK_AUD1                0x0a04
2996 #define ENABLE_IP_AUD0                  0x0b00
2997 #define ENABLE_IP_AUD1                  0x0b04
2998
2999 static unsigned long aud_clk_regs[] __initdata = {
3000         MUX_SEL_AUD0,
3001         MUX_SEL_AUD1,
3002         MUX_ENABLE_AUD0,
3003         MUX_ENABLE_AUD1,
3004         DIV_AUD0,
3005         DIV_AUD1,
3006         ENABLE_ACLK_AUD,
3007         ENABLE_PCLK_AUD,
3008         ENABLE_SCLK_AUD0,
3009         ENABLE_SCLK_AUD1,
3010         ENABLE_IP_AUD0,
3011         ENABLE_IP_AUD1,
3012 };
3013
3014 /* list of all parent clock list */
3015 PNAME(mout_aud_pll_user_aud_p)  = { "oscclk", "fout_aud_pll", };
3016 PNAME(mout_sclk_aud_pcm_p)      = { "mout_aud_pll_user", "ioclk_audiocdclk0",};
3017
3018 static struct samsung_fixed_rate_clock aud_fixed_clks[] __initdata = {
3019         FRATE(0, "ioclk_jtag_tclk", NULL, CLK_IS_ROOT, 33000000),
3020         FRATE(0, "ioclk_slimbus_clk", NULL, CLK_IS_ROOT, 25000000),
3021         FRATE(0, "ioclk_i2s_bclk", NULL, CLK_IS_ROOT, 50000000),
3022 };
3023
3024 static struct samsung_mux_clock aud_mux_clks[] __initdata = {
3025         /* MUX_SEL_AUD0 */
3026         MUX(CLK_MOUT_AUD_PLL_USER, "mout_aud_pll_user",
3027                         mout_aud_pll_user_aud_p, MUX_SEL_AUD0, 0, 1),
3028
3029         /* MUX_SEL_AUD1 */
3030         MUX(CLK_MOUT_SCLK_AUD_PCM, "mout_sclk_aud_pcm", mout_sclk_aud_pcm_p,
3031                         MUX_SEL_AUD1, 8, 1),
3032         MUX(CLK_MOUT_SCLK_AUD_I2S, "mout_sclk_aud_i2s", mout_sclk_aud_pcm_p,
3033                         MUX_SEL_AUD1, 0, 1),
3034 };
3035
3036 static struct samsung_div_clock aud_div_clks[] __initdata = {
3037         /* DIV_AUD0 */
3038         DIV(CLK_DIV_ATCLK_AUD, "div_atclk_aud", "div_aud_ca5", DIV_AUD0,
3039                         12, 4),
3040         DIV(CLK_DIV_PCLK_DBG_AUD, "div_pclk_dbg_aud", "div_aud_ca5", DIV_AUD0,
3041                         8, 4),
3042         DIV(CLK_DIV_ACLK_AUD, "div_aclk_aud", "div_aud_ca5", DIV_AUD0,
3043                         4, 4),
3044         DIV(CLK_DIV_AUD_CA5, "div_aud_ca5", "mout_aud_pll_user", DIV_AUD0,
3045                         0, 4),
3046
3047         /* DIV_AUD1 */
3048         DIV(CLK_DIV_SCLK_AUD_SLIMBUS, "div_sclk_aud_slimbus",
3049                         "mout_aud_pll_user", DIV_AUD1, 16, 5),
3050         DIV(CLK_DIV_SCLK_AUD_UART, "div_sclk_aud_uart", "mout_aud_pll_user",
3051                         DIV_AUD1, 12, 4),
3052         DIV(CLK_DIV_SCLK_AUD_PCM, "div_sclk_aud_pcm", "mout_sclk_aud_pcm",
3053                         DIV_AUD1, 4, 8),
3054         DIV(CLK_DIV_SCLK_AUD_I2S, "div_sclk_aud_i2s",  "mout_sclk_aud_i2s",
3055                         DIV_AUD1, 0, 4),
3056 };
3057
3058 static struct samsung_gate_clock aud_gate_clks[] __initdata = {
3059         /* ENABLE_ACLK_AUD */
3060         GATE(CLK_ACLK_INTR_CTRL, "aclk_intr_ctrl", "div_aclk_aud",
3061                         ENABLE_ACLK_AUD, 12, 0, 0),
3062         GATE(CLK_ACLK_SMMU_LPASSX, "aclk_smmu_lpassx", "div_aclk_aud",
3063                         ENABLE_ACLK_AUD, 7, 0, 0),
3064         GATE(CLK_ACLK_XIU_LPASSX, "aclk_xiu_lpassx", "div_aclk_aud",
3065                         ENABLE_ACLK_AUD, 0, 4, 0),
3066         GATE(CLK_ACLK_AUDNP_133, "aclk_audnp_133", "div_aclk_aud",
3067                         ENABLE_ACLK_AUD, 0, 3, 0),
3068         GATE(CLK_ACLK_AUDND_133, "aclk_audnd_133", "div_aclk_aud",
3069                         ENABLE_ACLK_AUD, 0, 2, 0),
3070         GATE(CLK_ACLK_SRAMC, "aclk_sramc", "div_aclk_aud", ENABLE_ACLK_AUD,
3071                         0, 1, 0),
3072         GATE(CLK_ACLK_DMAC, "aclk_dmac",  "div_aclk_aud", ENABLE_ACLK_AUD,
3073                         0, CLK_IGNORE_UNUSED, 0),
3074
3075         /* ENABLE_PCLK_AUD */
3076         GATE(CLK_PCLK_WDT1, "pclk_wdt1", "div_aclk_aud", ENABLE_PCLK_AUD,
3077                         13, 0, 0),
3078         GATE(CLK_PCLK_WDT0, "pclk_wdt0", "div_aclk_aud", ENABLE_PCLK_AUD,
3079                         12, 0, 0),
3080         GATE(CLK_PCLK_SFR1, "pclk_sfr1", "div_aclk_aud", ENABLE_PCLK_AUD,
3081                         11, 0, 0),
3082         GATE(CLK_PCLK_SMMU_LPASSX, "pclk_smmu_lpassx", "div_aclk_aud",
3083                         ENABLE_PCLK_AUD, 10, 0, 0),
3084         GATE(CLK_PCLK_GPIO_AUD, "pclk_gpio_aud", "div_aclk_aud",
3085                         ENABLE_PCLK_AUD, 9, CLK_IGNORE_UNUSED, 0),
3086         GATE(CLK_PCLK_PMU_AUD, "pclk_pmu_aud", "div_aclk_aud",
3087                         ENABLE_PCLK_AUD, 8, CLK_IGNORE_UNUSED, 0),
3088         GATE(CLK_PCLK_SYSREG_AUD, "pclk_sysreg_aud", "div_aclk_aud",
3089                         ENABLE_PCLK_AUD, 7, CLK_IGNORE_UNUSED, 0),
3090         GATE(CLK_PCLK_AUD_SLIMBUS, "pclk_aud_slimbus", "div_aclk_aud",
3091                         ENABLE_PCLK_AUD, 6, 0, 0),
3092         GATE(CLK_PCLK_AUD_UART, "pclk_aud_uart", "div_aclk_aud",
3093                         ENABLE_PCLK_AUD, 5, 0, 0),
3094         GATE(CLK_PCLK_AUD_PCM, "pclk_aud_pcm", "div_aclk_aud",
3095                         ENABLE_PCLK_AUD, 4, 0, 0),
3096         GATE(CLK_PCLK_AUD_I2S, "pclk_aud_i2s", "div_aclk_aud",
3097                         ENABLE_PCLK_AUD, 3, 0, 0),
3098         GATE(CLK_PCLK_TIMER, "pclk_timer", "div_aclk_aud", ENABLE_PCLK_AUD,
3099                         2, 0, 0),
3100         GATE(CLK_PCLK_SFR0_CTRL, "pclk_sfr0_ctrl", "div_aclk_aud",
3101                         ENABLE_PCLK_AUD, 0, CLK_IGNORE_UNUSED, 0),
3102
3103         /* ENABLE_SCLK_AUD0 */
3104         GATE(CLK_ATCLK_AUD, "atclk_aud", "div_atclk_aud", ENABLE_SCLK_AUD0,
3105                         2, CLK_IGNORE_UNUSED, 0),
3106         GATE(CLK_PCLK_DBG_AUD, "pclk_dbg_aud", "div_pclk_dbg_aud",
3107                         ENABLE_SCLK_AUD0, 1, 0, 0),
3108         GATE(CLK_SCLK_AUD_CA5, "sclk_aud_ca5", "div_aud_ca5", ENABLE_SCLK_AUD0,
3109                         0, 0, 0),
3110
3111         /* ENABLE_SCLK_AUD1 */
3112         GATE(CLK_SCLK_JTAG_TCK, "sclk_jtag_tck", "ioclk_jtag_tclk",
3113                         ENABLE_SCLK_AUD1, 6, 0, 0),
3114         GATE(CLK_SCLK_SLIMBUS_CLKIN, "sclk_slimbus_clkin", "ioclk_slimbus_clk",
3115                         ENABLE_SCLK_AUD1, 5, 0, 0),
3116         GATE(CLK_SCLK_AUD_SLIMBUS, "sclk_aud_slimbus", "div_sclk_aud_slimbus",
3117                         ENABLE_SCLK_AUD1, 4, 0, 0),
3118         GATE(CLK_SCLK_AUD_UART, "sclk_aud_uart", "div_sclk_aud_uart",
3119                         ENABLE_SCLK_AUD1, 3, CLK_IGNORE_UNUSED, 0),
3120         GATE(CLK_SCLK_AUD_PCM, "sclk_aud_pcm", "div_sclk_aud_pcm",
3121                         ENABLE_SCLK_AUD1, 2, 0, 0),
3122         GATE(CLK_SCLK_I2S_BCLK, "sclk_i2s_bclk", "ioclk_i2s_bclk",
3123                         ENABLE_SCLK_AUD1, 1, CLK_IGNORE_UNUSED, 0),
3124         GATE(CLK_SCLK_AUD_I2S, "sclk_aud_i2s", "div_sclk_aud_i2s",
3125                         ENABLE_SCLK_AUD1, 0, CLK_IGNORE_UNUSED, 0),
3126 };
3127
3128 static struct samsung_cmu_info aud_cmu_info __initdata = {
3129         .mux_clks               = aud_mux_clks,
3130         .nr_mux_clks            = ARRAY_SIZE(aud_mux_clks),
3131         .div_clks               = aud_div_clks,
3132         .nr_div_clks            = ARRAY_SIZE(aud_div_clks),
3133         .gate_clks              = aud_gate_clks,
3134         .nr_gate_clks           = ARRAY_SIZE(aud_gate_clks),
3135         .fixed_clks             = aud_fixed_clks,
3136         .nr_fixed_clks          = ARRAY_SIZE(aud_fixed_clks),
3137         .nr_clk_ids             = AUD_NR_CLK,
3138         .clk_regs               = aud_clk_regs,
3139         .nr_clk_regs            = ARRAY_SIZE(aud_clk_regs),
3140 };
3141
3142 static void __init exynos5433_cmu_aud_init(struct device_node *np)
3143 {
3144         samsung_cmu_register_one(np, &aud_cmu_info);
3145 }
3146 CLK_OF_DECLARE(exynos5433_cmu_aud, "samsung,exynos5433-cmu-aud",
3147                 exynos5433_cmu_aud_init);
3148
3149
3150 /*
3151  * Register offset definitions for CMU_BUS{0|1|2}
3152  */
3153 #define DIV_BUS                         0x0600
3154 #define DIV_STAT_BUS                    0x0700
3155 #define ENABLE_ACLK_BUS                 0x0800
3156 #define ENABLE_PCLK_BUS                 0x0900
3157 #define ENABLE_IP_BUS0                  0x0b00
3158 #define ENABLE_IP_BUS1                  0x0b04
3159
3160 #define MUX_SEL_BUS2                    0x0200  /* Only for CMU_BUS2 */
3161 #define MUX_ENABLE_BUS2                 0x0300  /* Only for CMU_BUS2 */
3162 #define MUX_STAT_BUS2                   0x0400  /* Only for CMU_BUS2 */
3163
3164 /* list of all parent clock list */
3165 PNAME(mout_aclk_bus2_400_p)     = { "oscclk", "aclk_bus2_400", };
3166
3167 #define CMU_BUS_COMMON_CLK_REGS \
3168         DIV_BUS,                \
3169         ENABLE_ACLK_BUS,        \
3170         ENABLE_PCLK_BUS,        \
3171         ENABLE_IP_BUS0,         \
3172         ENABLE_IP_BUS1
3173
3174 static unsigned long bus01_clk_regs[] __initdata = {
3175         CMU_BUS_COMMON_CLK_REGS,
3176 };
3177
3178 static unsigned long bus2_clk_regs[] __initdata = {
3179         MUX_SEL_BUS2,
3180         MUX_ENABLE_BUS2,
3181         CMU_BUS_COMMON_CLK_REGS,
3182 };
3183
3184 static struct samsung_div_clock bus0_div_clks[] __initdata = {
3185         /* DIV_BUS0 */
3186         DIV(CLK_DIV_PCLK_BUS_133, "div_pclk_bus0_133", "aclk_bus0_400",
3187                         DIV_BUS, 0, 3),
3188 };
3189
3190 /* CMU_BUS0 clocks */
3191 static struct samsung_gate_clock bus0_gate_clks[] __initdata = {
3192         /* ENABLE_ACLK_BUS0 */
3193         GATE(CLK_ACLK_AHB2APB_BUSP, "aclk_ahb2apb_bus0p", "div_pclk_bus0_133",
3194                         ENABLE_ACLK_BUS, 4, CLK_IGNORE_UNUSED, 0),
3195         GATE(CLK_ACLK_BUSNP_133, "aclk_bus0np_133", "div_pclk_bus0_133",
3196                         ENABLE_ACLK_BUS, 2, CLK_IGNORE_UNUSED, 0),
3197         GATE(CLK_ACLK_BUSND_400, "aclk_bus0nd_400", "aclk_bus0_400",
3198                         ENABLE_ACLK_BUS, 0, CLK_IGNORE_UNUSED, 0),
3199
3200         /* ENABLE_PCLK_BUS0 */
3201         GATE(CLK_PCLK_BUSSRVND_133, "pclk_bus0srvnd_133", "div_pclk_bus0_133",
3202                         ENABLE_PCLK_BUS, 2, 0, 0),
3203         GATE(CLK_PCLK_PMU_BUS, "pclk_pmu_bus0", "div_pclk_bus0_133",
3204                         ENABLE_PCLK_BUS, 1, CLK_IGNORE_UNUSED, 0),
3205         GATE(CLK_PCLK_SYSREG_BUS, "pclk_sysreg_bus0", "div_pclk_bus0_133",
3206                         ENABLE_PCLK_BUS, 0, CLK_IGNORE_UNUSED, 0),
3207 };
3208
3209 /* CMU_BUS1 clocks */
3210 static struct samsung_div_clock bus1_div_clks[] __initdata = {
3211         /* DIV_BUS1 */
3212         DIV(CLK_DIV_PCLK_BUS_133, "div_pclk_bus1_133", "aclk_bus1_400",
3213                         DIV_BUS, 0, 3),
3214 };
3215
3216 static struct samsung_gate_clock bus1_gate_clks[] __initdata = {
3217         /* ENABLE_ACLK_BUS1 */
3218         GATE(CLK_ACLK_AHB2APB_BUSP, "aclk_ahb2apb_bus1p", "div_pclk_bus1_133",
3219                         ENABLE_ACLK_BUS, 4, CLK_IGNORE_UNUSED, 0),
3220         GATE(CLK_ACLK_BUSNP_133, "aclk_bus1np_133", "div_pclk_bus1_133",
3221                         ENABLE_ACLK_BUS, 2, CLK_IGNORE_UNUSED, 0),
3222         GATE(CLK_ACLK_BUSND_400, "aclk_bus1nd_400", "aclk_bus1_400",
3223                         ENABLE_ACLK_BUS, 0, CLK_IGNORE_UNUSED, 0),
3224
3225         /* ENABLE_PCLK_BUS1 */
3226         GATE(CLK_PCLK_BUSSRVND_133, "pclk_bus1srvnd_133", "div_pclk_bus1_133",
3227                         ENABLE_PCLK_BUS, 2, 0, 0),
3228         GATE(CLK_PCLK_PMU_BUS, "pclk_pmu_bus1", "div_pclk_bus1_133",
3229                         ENABLE_PCLK_BUS, 1, CLK_IGNORE_UNUSED, 0),
3230         GATE(CLK_PCLK_SYSREG_BUS, "pclk_sysreg_bus1", "div_pclk_bus1_133",
3231                         ENABLE_PCLK_BUS, 0, CLK_IGNORE_UNUSED, 0),
3232 };
3233
3234 /* CMU_BUS2 clocks */
3235 static struct samsung_mux_clock bus2_mux_clks[] __initdata = {
3236         /* MUX_SEL_BUS2 */
3237         MUX(CLK_MOUT_ACLK_BUS2_400_USER, "mout_aclk_bus2_400_user",
3238                         mout_aclk_bus2_400_p, MUX_SEL_BUS2, 0, 1),
3239 };
3240
3241 static struct samsung_div_clock bus2_div_clks[] __initdata = {
3242         /* DIV_BUS2 */
3243         DIV(CLK_DIV_PCLK_BUS_133, "div_pclk_bus2_133",
3244                         "mout_aclk_bus2_400_user", DIV_BUS, 0, 3),
3245 };
3246
3247 static struct samsung_gate_clock bus2_gate_clks[] __initdata = {
3248         /* ENABLE_ACLK_BUS2 */
3249         GATE(CLK_ACLK_AHB2APB_BUSP, "aclk_ahb2apb_bus2p", "div_pclk_bus2_133",
3250                         ENABLE_ACLK_BUS, 3, CLK_IGNORE_UNUSED, 0),
3251         GATE(CLK_ACLK_BUSNP_133, "aclk_bus2np_133", "div_pclk_bus2_133",
3252                         ENABLE_ACLK_BUS, 2, CLK_IGNORE_UNUSED, 0),
3253         GATE(CLK_ACLK_BUS2BEND_400, "aclk_bus2bend_400",
3254                         "mout_aclk_bus2_400_user", ENABLE_ACLK_BUS,
3255                         1, CLK_IGNORE_UNUSED, 0),
3256         GATE(CLK_ACLK_BUS2RTND_400, "aclk_bus2rtnd_400",
3257                         "mout_aclk_bus2_400_user", ENABLE_ACLK_BUS,
3258                         0, CLK_IGNORE_UNUSED, 0),
3259
3260         /* ENABLE_PCLK_BUS2 */
3261         GATE(CLK_PCLK_BUSSRVND_133, "pclk_bus2srvnd_133", "div_pclk_bus2_133",
3262                         ENABLE_PCLK_BUS, 2, 0, 0),
3263         GATE(CLK_PCLK_PMU_BUS, "pclk_pmu_bus2", "div_pclk_bus2_133",
3264                         ENABLE_PCLK_BUS, 1, CLK_IGNORE_UNUSED, 0),
3265         GATE(CLK_PCLK_SYSREG_BUS, "pclk_sysreg_bus2", "div_pclk_bus2_133",
3266                         ENABLE_PCLK_BUS, 0, CLK_IGNORE_UNUSED, 0),
3267 };
3268
3269 #define CMU_BUS_INFO_CLKS(id)                                           \
3270         .div_clks               = bus##id##_div_clks,                   \
3271         .nr_div_clks            = ARRAY_SIZE(bus##id##_div_clks),       \
3272         .gate_clks              = bus##id##_gate_clks,                  \
3273         .nr_gate_clks           = ARRAY_SIZE(bus##id##_gate_clks),      \
3274         .nr_clk_ids             = BUSx_NR_CLK
3275
3276 static struct samsung_cmu_info bus0_cmu_info __initdata = {
3277         CMU_BUS_INFO_CLKS(0),
3278         .clk_regs               = bus01_clk_regs,
3279         .nr_clk_regs            = ARRAY_SIZE(bus01_clk_regs),
3280 };
3281
3282 static struct samsung_cmu_info bus1_cmu_info __initdata = {
3283         CMU_BUS_INFO_CLKS(1),
3284         .clk_regs               = bus01_clk_regs,
3285         .nr_clk_regs            = ARRAY_SIZE(bus01_clk_regs),
3286 };
3287
3288 static struct samsung_cmu_info bus2_cmu_info __initdata = {
3289         CMU_BUS_INFO_CLKS(2),
3290         .mux_clks               = bus2_mux_clks,
3291         .nr_mux_clks            = ARRAY_SIZE(bus2_mux_clks),
3292         .clk_regs               = bus2_clk_regs,
3293         .nr_clk_regs            = ARRAY_SIZE(bus2_clk_regs),
3294 };
3295
3296 #define exynos5433_cmu_bus_init(id)                                     \
3297 static void __init exynos5433_cmu_bus##id##_init(struct device_node *np)\
3298 {                                                                       \
3299         samsung_cmu_register_one(np, &bus##id##_cmu_info);              \
3300 }                                                                       \
3301 CLK_OF_DECLARE(exynos5433_cmu_bus##id,                                  \
3302                 "samsung,exynos5433-cmu-bus"#id,                        \
3303                 exynos5433_cmu_bus##id##_init)
3304
3305 exynos5433_cmu_bus_init(0);
3306 exynos5433_cmu_bus_init(1);
3307 exynos5433_cmu_bus_init(2);
3308
3309 /*
3310  * Register offset definitions for CMU_G3D
3311  */
3312 #define G3D_PLL_LOCK                    0x0000
3313 #define G3D_PLL_CON0                    0x0100
3314 #define G3D_PLL_CON1                    0x0104
3315 #define G3D_PLL_FREQ_DET                0x010c
3316 #define MUX_SEL_G3D                     0x0200
3317 #define MUX_ENABLE_G3D                  0x0300
3318 #define MUX_STAT_G3D                    0x0400
3319 #define DIV_G3D                         0x0600
3320 #define DIV_G3D_PLL_FREQ_DET            0x0604
3321 #define DIV_STAT_G3D                    0x0700
3322 #define DIV_STAT_G3D_PLL_FREQ_DET       0x0704
3323 #define ENABLE_ACLK_G3D                 0x0800
3324 #define ENABLE_PCLK_G3D                 0x0900
3325 #define ENABLE_SCLK_G3D                 0x0a00
3326 #define ENABLE_IP_G3D0                  0x0b00
3327 #define ENABLE_IP_G3D1                  0x0b04
3328 #define CLKOUT_CMU_G3D                  0x0c00
3329 #define CLKOUT_CMU_G3D_DIV_STAT         0x0c04
3330 #define CLK_STOPCTRL                    0x1000
3331
3332 static unsigned long g3d_clk_regs[] __initdata = {
3333         G3D_PLL_LOCK,
3334         G3D_PLL_CON0,
3335         G3D_PLL_CON1,
3336         G3D_PLL_FREQ_DET,
3337         MUX_SEL_G3D,
3338         MUX_ENABLE_G3D,
3339         DIV_G3D,
3340         DIV_G3D_PLL_FREQ_DET,
3341         ENABLE_ACLK_G3D,
3342         ENABLE_PCLK_G3D,
3343         ENABLE_SCLK_G3D,
3344         ENABLE_IP_G3D0,
3345         ENABLE_IP_G3D1,
3346         CLKOUT_CMU_G3D,
3347         CLKOUT_CMU_G3D_DIV_STAT,
3348         CLK_STOPCTRL,
3349 };
3350
3351 /* list of all parent clock list */
3352 PNAME(mout_aclk_g3d_400_p)      = { "mout_g3d_pll", "aclk_g3d_400", };
3353 PNAME(mout_g3d_pll_p)           = { "oscclk", "fout_g3d_pll", };
3354
3355 static struct samsung_pll_clock g3d_pll_clks[] __initdata = {
3356         PLL(pll_35xx, CLK_FOUT_G3D_PLL, "fout_g3d_pll", "oscclk",
3357                 G3D_PLL_LOCK, G3D_PLL_CON0, exynos5443_pll_rates),
3358 };
3359
3360 static struct samsung_mux_clock g3d_mux_clks[] __initdata = {
3361         /* MUX_SEL_G3D */
3362         MUX_F(CLK_MOUT_ACLK_G3D_400, "mout_aclk_g3d_400", mout_aclk_g3d_400_p,
3363                         MUX_SEL_G3D, 8, 1, CLK_SET_RATE_PARENT, 0),
3364         MUX_F(CLK_MOUT_G3D_PLL, "mout_g3d_pll", mout_g3d_pll_p,
3365                         MUX_SEL_G3D, 0, 1, CLK_SET_RATE_PARENT, 0),
3366 };
3367
3368 static struct samsung_div_clock g3d_div_clks[] __initdata = {
3369         /* DIV_G3D */
3370         DIV(CLK_DIV_SCLK_HPM_G3D, "div_sclk_hpm_g3d", "mout_g3d_pll", DIV_G3D,
3371                         8, 2),
3372         DIV(CLK_DIV_PCLK_G3D, "div_pclk_g3d", "div_aclk_g3d", DIV_G3D,
3373                         4, 3),
3374         DIV_F(CLK_DIV_ACLK_G3D, "div_aclk_g3d", "mout_aclk_g3d_400", DIV_G3D,
3375                         0, 3, CLK_SET_RATE_PARENT, 0),
3376 };
3377
3378 static struct samsung_gate_clock g3d_gate_clks[] __initdata = {
3379         /* ENABLE_ACLK_G3D */
3380         GATE(CLK_ACLK_BTS_G3D1, "aclk_bts_g3d1", "div_aclk_g3d",
3381                         ENABLE_ACLK_G3D, 7, 0, 0),
3382         GATE(CLK_ACLK_BTS_G3D0, "aclk_bts_g3d0", "div_aclk_g3d",
3383                         ENABLE_ACLK_G3D, 6, 0, 0),
3384         GATE(CLK_ACLK_ASYNCAPBS_G3D, "aclk_asyncapbs_g3d", "div_pclk_g3d",
3385                         ENABLE_ACLK_G3D, 5, CLK_IGNORE_UNUSED, 0),
3386         GATE(CLK_ACLK_ASYNCAPBM_G3D, "aclk_asyncapbm_g3d", "div_aclk_g3d",
3387                         ENABLE_ACLK_G3D, 4, CLK_IGNORE_UNUSED, 0),
3388         GATE(CLK_ACLK_AHB2APB_G3DP, "aclk_ahb2apb_g3dp", "div_pclk_g3d",
3389                         ENABLE_ACLK_G3D, 3, CLK_IGNORE_UNUSED, 0),
3390         GATE(CLK_ACLK_G3DNP_150, "aclk_g3dnp_150", "div_pclk_g3d",
3391                         ENABLE_ACLK_G3D, 2, CLK_IGNORE_UNUSED, 0),
3392         GATE(CLK_ACLK_G3DND_600, "aclk_g3dnd_600", "div_aclk_g3d",
3393                         ENABLE_ACLK_G3D, 1, CLK_IGNORE_UNUSED, 0),
3394         GATE(CLK_ACLK_G3D, "aclk_g3d", "div_aclk_g3d",
3395                         ENABLE_ACLK_G3D, 0, CLK_SET_RATE_PARENT, 0),
3396
3397         /* ENABLE_PCLK_G3D */
3398         GATE(CLK_PCLK_BTS_G3D1, "pclk_bts_g3d1", "div_pclk_g3d",
3399                         ENABLE_PCLK_G3D, 3, 0, 0),
3400         GATE(CLK_PCLK_BTS_G3D0, "pclk_bts_g3d0", "div_pclk_g3d",
3401                         ENABLE_PCLK_G3D, 2, 0, 0),
3402         GATE(CLK_PCLK_PMU_G3D, "pclk_pmu_g3d", "div_pclk_g3d",
3403                         ENABLE_PCLK_G3D, 1, CLK_IGNORE_UNUSED, 0),
3404         GATE(CLK_PCLK_SYSREG_G3D, "pclk_sysreg_g3d", "div_pclk_g3d",
3405                         ENABLE_PCLK_G3D, 0, CLK_IGNORE_UNUSED, 0),
3406
3407         /* ENABLE_SCLK_G3D */
3408         GATE(CLK_SCLK_HPM_G3D, "sclk_hpm_g3d", "div_sclk_hpm_g3d",
3409                         ENABLE_SCLK_G3D, 0, 0, 0),
3410 };
3411
3412 static struct samsung_cmu_info g3d_cmu_info __initdata = {
3413         .pll_clks               = g3d_pll_clks,
3414         .nr_pll_clks            = ARRAY_SIZE(g3d_pll_clks),
3415         .mux_clks               = g3d_mux_clks,
3416         .nr_mux_clks            = ARRAY_SIZE(g3d_mux_clks),
3417         .div_clks               = g3d_div_clks,
3418         .nr_div_clks            = ARRAY_SIZE(g3d_div_clks),
3419         .gate_clks              = g3d_gate_clks,
3420         .nr_gate_clks           = ARRAY_SIZE(g3d_gate_clks),
3421         .nr_clk_ids             = G3D_NR_CLK,
3422 };
3423
3424 static void __init exynos5433_cmu_g3d_init(struct device_node *np)
3425 {
3426         samsung_cmu_register_one(np, &g3d_cmu_info);
3427
3428         if (of_get_property(np, "power-domains", NULL))
3429                 exynos5433_cmu_pd_handler_init(np, g3d_clk_regs,
3430                                 ARRAY_SIZE(g3d_clk_regs));
3431 }
3432 CLK_OF_DECLARE(exynos5433_cmu_g3d, "samsung,exynos5433-cmu-g3d",
3433                 exynos5433_cmu_g3d_init);
3434
3435 /*
3436  * Register offset definitions for CMU_GSCL
3437  */
3438 #define MUX_SEL_GSCL                            0x0200
3439 #define MUX_ENABLE_GSCL                         0x0300
3440 #define MUX_STAT_GSCL                           0x0400
3441 #define ENABLE_ACLK_GSCL                        0x0800
3442 #define ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL0      0x0804
3443 #define ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL1      0x0808
3444 #define ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL2      0x080c
3445 #define ENABLE_PCLK_GSCL                        0x0900
3446 #define ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL0      0x0904
3447 #define ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL1      0x0908
3448 #define ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL2      0x090c
3449 #define ENABLE_IP_GSCL0                         0x0b00
3450 #define ENABLE_IP_GSCL1                         0x0b04
3451 #define ENABLE_IP_GSCL_SECURE_SMMU_GSCL0        0x0b08
3452 #define ENABLE_IP_GSCL_SECURE_SMMU_GSCL1        0x0b0c
3453 #define ENABLE_IP_GSCL_SECURE_SMMU_GSCL2        0x0b10
3454
3455 static unsigned long gscl_clk_regs[] __initdata = {
3456         MUX_SEL_GSCL,
3457         MUX_ENABLE_GSCL,
3458         ENABLE_ACLK_GSCL,
3459         ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL0,
3460         ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL1,
3461         ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL2,
3462         ENABLE_PCLK_GSCL,
3463         ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL0,
3464         ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL1,
3465         ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL2,
3466         ENABLE_IP_GSCL0,
3467         ENABLE_IP_GSCL1,
3468         ENABLE_IP_GSCL_SECURE_SMMU_GSCL0,
3469         ENABLE_IP_GSCL_SECURE_SMMU_GSCL1,
3470         ENABLE_IP_GSCL_SECURE_SMMU_GSCL2,
3471 };
3472
3473 /* list of all parent clock list */
3474 PNAME(aclk_gscl_111_user_p)     = { "oscclk", "aclk_gscl_111", };
3475 PNAME(aclk_gscl_333_user_p)     = { "oscclk", "aclk_gscl_333", };
3476
3477 static struct samsung_mux_clock gscl_mux_clks[] __initdata = {
3478         /* MUX_SEL_GSCL */
3479         MUX(CLK_MOUT_ACLK_GSCL_111_USER, "mout_aclk_gscl_111_user",
3480                         aclk_gscl_111_user_p, MUX_SEL_GSCL, 4, 1),
3481         MUX(CLK_MOUT_ACLK_GSCL_333_USER, "mout_aclk_gscl_333_user",
3482                         aclk_gscl_333_user_p, MUX_SEL_GSCL, 0, 1),
3483 };
3484
3485 static struct samsung_gate_clock gscl_gate_clks[] __initdata = {
3486         /* ENABLE_ACLK_GSCL */
3487         GATE(CLK_ACLK_BTS_GSCL2, "aclk_bts_gscl2", "mout_aclk_gscl_333_user",
3488                         ENABLE_ACLK_GSCL, 11, 0, 0),
3489         GATE(CLK_ACLK_BTS_GSCL1, "aclk_bts_gscl1", "mout_aclk_gscl_333_user",
3490                         ENABLE_ACLK_GSCL, 10, 0, 0),
3491         GATE(CLK_ACLK_BTS_GSCL0, "aclk_bts_gscl0", "mout_aclk_gscl_333_user",
3492                         ENABLE_ACLK_GSCL, 9, 0, 0),
3493         GATE(CLK_ACLK_AHB2APB_GSCLP, "aclk_ahb2apb_gsclp",
3494                         "mout_aclk_gscl_111_user", ENABLE_ACLK_GSCL,
3495                         8, CLK_IGNORE_UNUSED, 0),
3496         GATE(CLK_ACLK_XIU_GSCLX, "aclk_xiu_gsclx", "mout_aclk_gscl_333_user",
3497                         ENABLE_ACLK_GSCL, 7, 0, 0),
3498         GATE(CLK_ACLK_GSCLNP_111, "aclk_gsclnp_111", "mout_aclk_gscl_111_user",
3499                         ENABLE_ACLK_GSCL, 6, CLK_IGNORE_UNUSED, 0),
3500         GATE(CLK_ACLK_GSCLRTND_333, "aclk_gsclrtnd_333",
3501                         "mout_aclk_gscl_333_user", ENABLE_ACLK_GSCL, 5,
3502                         CLK_IGNORE_UNUSED, 0),
3503         GATE(CLK_ACLK_GSCLBEND_333, "aclk_gsclbend_333",
3504                         "mout_aclk_gscl_333_user", ENABLE_ACLK_GSCL, 4,
3505                         CLK_IGNORE_UNUSED, 0),
3506         GATE(CLK_ACLK_GSD, "aclk_gsd", "mout_aclk_gscl_333_user",
3507                         ENABLE_ACLK_GSCL, 3, 0, 0),
3508         GATE(CLK_ACLK_GSCL2, "aclk_gscl2", "mout_aclk_gscl_333_user",
3509                         ENABLE_ACLK_GSCL, 2, 0, 0),
3510         GATE(CLK_ACLK_GSCL1, "aclk_gscl1", "mout_aclk_gscl_333_user",
3511                         ENABLE_ACLK_GSCL, 1, 0, 0),
3512         GATE(CLK_ACLK_GSCL0, "aclk_gscl0", "mout_aclk_gscl_333_user",
3513                         ENABLE_ACLK_GSCL, 0, 0, 0),
3514
3515         /* ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL0 */
3516         GATE(CLK_ACLK_SMMU_GSCL0, "aclk_smmu_gscl0", "mout_aclk_gscl_333_user",
3517                         ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL0, 0, 0, 0),
3518
3519         /* ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL1 */
3520         GATE(CLK_ACLK_SMMU_GSCL1, "aclk_smmu_gscl1", "mout_aclk_gscl_333_user",
3521                         ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL1, 0, 0, 0),
3522
3523         /* ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL2 */
3524         GATE(CLK_ACLK_SMMU_GSCL2, "aclk_smmu_gscl2", "mout_aclk_gscl_333_user",
3525                         ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL2, 0, 0, 0),
3526
3527         /* ENABLE_PCLK_GSCL */
3528         GATE(CLK_PCLK_BTS_GSCL2, "pclk_bts_gscl2", "mout_aclk_gscl_111_user",
3529                         ENABLE_PCLK_GSCL, 7, 0, 0),
3530         GATE(CLK_PCLK_BTS_GSCL1, "pclk_bts_gscl1", "mout_aclk_gscl_111_user",
3531                         ENABLE_PCLK_GSCL, 6, 0, 0),
3532         GATE(CLK_PCLK_BTS_GSCL0, "pclk_bts_gscl0", "mout_aclk_gscl_111_user",
3533                         ENABLE_PCLK_GSCL, 5, 0, 0),
3534         GATE(CLK_PCLK_PMU_GSCL, "pclk_pmu_gscl", "mout_aclk_gscl_111_user",
3535                         ENABLE_PCLK_GSCL, 4, CLK_IGNORE_UNUSED, 0),
3536         GATE(CLK_PCLK_SYSREG_GSCL, "pclk_sysreg_gscl",
3537                         "mout_aclk_gscl_111_user", ENABLE_PCLK_GSCL,
3538                         3, CLK_IGNORE_UNUSED, 0),
3539         GATE(CLK_PCLK_GSCL2, "pclk_gscl2", "mout_aclk_gscl_111_user",
3540                         ENABLE_PCLK_GSCL, 2, 0, 0),
3541         GATE(CLK_PCLK_GSCL1, "pclk_gscl1", "mout_aclk_gscl_111_user",
3542                         ENABLE_PCLK_GSCL, 1, 0, 0),
3543         GATE(CLK_PCLK_GSCL0, "pclk_gscl0", "mout_aclk_gscl_111_user",
3544                         ENABLE_PCLK_GSCL, 0, 0, 0),
3545
3546         /* ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL0 */
3547         GATE(CLK_PCLK_SMMU_GSCL0, "pclk_smmu_gscl0", "mout_aclk_gscl_111_user",
3548                 ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL0, 0, 0, 0),
3549
3550         /* ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL1 */
3551         GATE(CLK_PCLK_SMMU_GSCL1, "pclk_smmu_gscl1", "mout_aclk_gscl_111_user",
3552                 ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL1, 0, 0, 0),
3553
3554         /* ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL2 */
3555         GATE(CLK_PCLK_SMMU_GSCL2, "pclk_smmu_gscl2", "mout_aclk_gscl_111_user",
3556                 ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL2, 0, 0, 0),
3557 };
3558
3559 static struct samsung_cmu_info gscl_cmu_info __initdata = {
3560         .mux_clks               = gscl_mux_clks,
3561         .nr_mux_clks            = ARRAY_SIZE(gscl_mux_clks),
3562         .gate_clks              = gscl_gate_clks,
3563         .nr_gate_clks           = ARRAY_SIZE(gscl_gate_clks),
3564         .nr_clk_ids             = GSCL_NR_CLK,
3565         .clk_regs               = gscl_clk_regs,
3566         .nr_clk_regs            = ARRAY_SIZE(gscl_clk_regs),
3567 };
3568
3569 static void __init exynos5433_cmu_gscl_init(struct device_node *np)
3570 {
3571         samsung_cmu_register_one(np, &gscl_cmu_info);
3572 }
3573 CLK_OF_DECLARE(exynos5433_cmu_gscl, "samsung,exynos5433-cmu-gscl",
3574                 exynos5433_cmu_gscl_init);
3575
3576 /*
3577  * Register offset definitions for CMU_APOLLO
3578  */
3579 #define APOLLO_PLL_LOCK                         0x0000
3580 #define APOLLO_PLL_CON0                         0x0100
3581 #define APOLLO_PLL_CON1                         0x0104
3582 #define APOLLO_PLL_FREQ_DET                     0x010c
3583 #define MUX_SEL_APOLLO0                         0x0200
3584 #define MUX_SEL_APOLLO1                         0x0204
3585 #define MUX_SEL_APOLLO2                         0x0208
3586 #define MUX_ENABLE_APOLLO0                      0x0300
3587 #define MUX_ENABLE_APOLLO1                      0x0304
3588 #define MUX_ENABLE_APOLLO2                      0x0308
3589 #define MUX_STAT_APOLLO0                        0x0400
3590 #define MUX_STAT_APOLLO1                        0x0404
3591 #define MUX_STAT_APOLLO2                        0x0408
3592 #define DIV_APOLLO0                             0x0600
3593 #define DIV_APOLLO1                             0x0604
3594 #define DIV_APOLLO_PLL_FREQ_DET                 0x0608
3595 #define DIV_STAT_APOLLO0                        0x0700
3596 #define DIV_STAT_APOLLO1                        0x0704
3597 #define DIV_STAT_APOLLO_PLL_FREQ_DET            0x0708
3598 #define ENABLE_ACLK_APOLLO                      0x0800
3599 #define ENABLE_PCLK_APOLLO                      0x0900
3600 #define ENABLE_SCLK_APOLLO                      0x0a00
3601 #define ENABLE_IP_APOLLO0                       0x0b00
3602 #define ENABLE_IP_APOLLO1                       0x0b04
3603 #define CLKOUT_CMU_APOLLO                       0x0c00
3604 #define CLKOUT_CMU_APOLLO_DIV_STAT              0x0c04
3605 #define ARMCLK_STOPCTRL                         0x1000
3606 #define APOLLO_PWR_CTRL                         0x1020
3607 #define APOLLO_PWR_CTRL2                        0x1024
3608 #define APOLLO_INTR_SPREAD_ENABLE               0x1080
3609 #define APOLLO_INTR_SPREAD_USE_STANDBYWFI       0x1084
3610 #define APOLLO_INTR_SPREAD_BLOCKING_DURATION    0x1088
3611
3612 static unsigned long apollo_clk_regs[] __initdata = {
3613         APOLLO_PLL_LOCK,
3614         APOLLO_PLL_CON0,
3615         APOLLO_PLL_CON1,
3616         APOLLO_PLL_FREQ_DET,
3617         MUX_SEL_APOLLO0,
3618         MUX_SEL_APOLLO1,
3619         MUX_SEL_APOLLO2,
3620         MUX_ENABLE_APOLLO0,
3621         MUX_ENABLE_APOLLO1,
3622         MUX_ENABLE_APOLLO2,
3623         DIV_APOLLO0,
3624         DIV_APOLLO1,
3625         DIV_APOLLO_PLL_FREQ_DET,
3626         ENABLE_ACLK_APOLLO,
3627         ENABLE_PCLK_APOLLO,
3628         ENABLE_SCLK_APOLLO,
3629         ENABLE_IP_APOLLO0,
3630         ENABLE_IP_APOLLO1,
3631         CLKOUT_CMU_APOLLO,
3632         CLKOUT_CMU_APOLLO_DIV_STAT,
3633         ARMCLK_STOPCTRL,
3634         APOLLO_PWR_CTRL,
3635         APOLLO_PWR_CTRL2,
3636         APOLLO_INTR_SPREAD_ENABLE,
3637         APOLLO_INTR_SPREAD_USE_STANDBYWFI,
3638         APOLLO_INTR_SPREAD_BLOCKING_DURATION,
3639 };
3640
3641 /* list of all parent clock list */
3642 PNAME(mout_apollo_pll_p)                = { "oscclk", "fout_apollo_pll", };
3643 PNAME(mout_bus_pll_apollo_user_p)       = { "oscclk", "sclk_bus_pll_apollo", };
3644 PNAME(mout_apollo_p)                    = { "mout_apollo_pll",
3645                                             "mout_bus_pll_apollo_user", };
3646
3647 static struct samsung_pll_clock apollo_pll_clks[] __initdata = {
3648         PLL(pll_35xx, CLK_FOUT_APOLLO_PLL, "fout_apollo_pll", "oscclk",
3649                 APOLLO_PLL_LOCK, APOLLO_PLL_CON0, exynos5443_pll_rates),
3650 };
3651
3652 static struct samsung_mux_clock apollo_mux_clks[] __initdata = {
3653         /* MUX_SEL_APOLLO0 */
3654         MUX_F(CLK_MOUT_APOLLO_PLL, "mout_apollo_pll", mout_apollo_pll_p,
3655                         MUX_SEL_APOLLO0, 0, 1,
3656                         CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT, 0),
3657
3658         /* MUX_SEL_APOLLO1 */
3659         MUX(CLK_MOUT_BUS_PLL_APOLLO_USER, "mout_bus_pll_apollo_user",
3660                         mout_bus_pll_apollo_user_p, MUX_SEL_APOLLO1, 0, 1),
3661
3662         /* MUX_SEL_APOLLO2 */
3663         MUX_F(CLK_MOUT_APOLLO, "mout_apollo", mout_apollo_p, MUX_SEL_APOLLO2,
3664                         0, 1, CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT, 0),
3665 };
3666
3667 static struct samsung_div_clock apollo_div_clks[] __initdata = {
3668         /* DIV_APOLLO0 */
3669         DIV_F(CLK_DIV_CNTCLK_APOLLO, "div_cntclk_apollo", "div_apollo2",
3670                         DIV_APOLLO0, 24, 3, CLK_GET_RATE_NOCACHE,
3671                         CLK_DIVIDER_READ_ONLY),
3672         DIV_F(CLK_DIV_PCLK_DBG_APOLLO, "div_pclk_dbg_apollo", "div_apollo2",
3673                         DIV_APOLLO0, 20, 3, CLK_GET_RATE_NOCACHE,
3674                         CLK_DIVIDER_READ_ONLY),
3675         DIV_F(CLK_DIV_ATCLK_APOLLO, "div_atclk_apollo", "div_apollo2",
3676                         DIV_APOLLO0, 16, 3, CLK_GET_RATE_NOCACHE,
3677                         CLK_DIVIDER_READ_ONLY),
3678         DIV_F(CLK_DIV_PCLK_APOLLO, "div_pclk_apollo", "div_apollo2",
3679                         DIV_APOLLO0, 12, 3, CLK_GET_RATE_NOCACHE,
3680                         CLK_DIVIDER_READ_ONLY),
3681         DIV_F(CLK_DIV_ACLK_APOLLO, "div_aclk_apollo", "div_apollo2",
3682                         DIV_APOLLO0, 8, 3, CLK_GET_RATE_NOCACHE,
3683                         CLK_DIVIDER_READ_ONLY),
3684         DIV_F(CLK_DIV_APOLLO2, "div_apollo2", "div_apollo1",
3685                         DIV_APOLLO0, 4, 3,
3686                         CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT, 0),
3687         DIV_F(CLK_DIV_APOLLO1, "div_apollo1", "mout_apollo",
3688                         DIV_APOLLO0, 0, 3,
3689                         CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT, 0),
3690
3691         /* DIV_APOLLO1 */
3692         DIV_F(CLK_DIV_SCLK_HPM_APOLLO, "div_sclk_hpm_apollo", "mout_apollo",
3693                         DIV_APOLLO1, 4, 3, CLK_GET_RATE_NOCACHE,
3694                         CLK_DIVIDER_READ_ONLY),
3695         DIV_F(CLK_DIV_APOLLO_PLL, "div_apollo_pll", "mout_apollo",
3696                         DIV_APOLLO1, 0, 3, CLK_GET_RATE_NOCACHE,
3697                         CLK_DIVIDER_READ_ONLY),
3698 };
3699
3700 static struct samsung_gate_clock apollo_gate_clks[] __initdata = {
3701         /* ENABLE_ACLK_APOLLO */
3702         GATE(CLK_ACLK_ASATBSLV_APOLLO_3_CSSYS, "aclk_asatbslv_apollo_3_cssys",
3703                         "div_atclk_apollo", ENABLE_ACLK_APOLLO,
3704                         6, CLK_IGNORE_UNUSED, 0),
3705         GATE(CLK_ACLK_ASATBSLV_APOLLO_2_CSSYS, "aclk_asatbslv_apollo_2_cssys",
3706                         "div_atclk_apollo", ENABLE_ACLK_APOLLO,
3707                         5, CLK_IGNORE_UNUSED, 0),
3708         GATE(CLK_ACLK_ASATBSLV_APOLLO_1_CSSYS, "aclk_asatbslv_apollo_1_cssys",
3709                         "div_atclk_apollo", ENABLE_ACLK_APOLLO,
3710                         4, CLK_IGNORE_UNUSED, 0),
3711         GATE(CLK_ACLK_ASATBSLV_APOLLO_0_CSSYS, "aclk_asatbslv_apollo_0_cssys",
3712                         "div_atclk_apollo", ENABLE_ACLK_APOLLO,
3713                         3, CLK_IGNORE_UNUSED, 0),
3714         GATE(CLK_ACLK_ASYNCACES_APOLLO_CCI, "aclk_asyncaces_apollo_cci",
3715                         "div_aclk_apollo", ENABLE_ACLK_APOLLO,
3716                         2, CLK_IGNORE_UNUSED, 0),
3717         GATE(CLK_ACLK_AHB2APB_APOLLOP, "aclk_ahb2apb_apollop",
3718                         "div_pclk_apollo", ENABLE_ACLK_APOLLO,
3719                         1, CLK_IGNORE_UNUSED, 0),
3720         GATE(CLK_ACLK_APOLLONP_200, "aclk_apollonp_200",
3721                         "div_pclk_apollo", ENABLE_ACLK_APOLLO,
3722                         0, CLK_IGNORE_UNUSED, 0),
3723
3724         /* ENABLE_PCLK_APOLLO */
3725         GATE(CLK_PCLK_ASAPBMST_CSSYS_APOLLO, "pclk_asapbmst_cssys_apollo",
3726                         "div_pclk_dbg_apollo", ENABLE_PCLK_APOLLO,
3727                         2, CLK_IGNORE_UNUSED, 0),
3728         GATE(CLK_PCLK_PMU_APOLLO, "pclk_pmu_apollo", "div_pclk_apollo",
3729                         ENABLE_PCLK_APOLLO, 1, CLK_IGNORE_UNUSED, 0),
3730         GATE(CLK_PCLK_SYSREG_APOLLO, "pclk_sysreg_apollo",
3731                         "div_pclk_apollo", ENABLE_PCLK_APOLLO,
3732                         0, CLK_IGNORE_UNUSED, 0),
3733
3734         /* ENABLE_SCLK_APOLLO */
3735         GATE(CLK_CNTCLK_APOLLO, "cntclk_apollo", "div_cntclk_apollo",
3736                         ENABLE_SCLK_APOLLO, 3, CLK_IGNORE_UNUSED, 0),
3737         GATE(CLK_SCLK_HPM_APOLLO, "sclk_hpm_apollo", "div_sclk_hpm_apollo",
3738                         ENABLE_SCLK_APOLLO, 1, CLK_IGNORE_UNUSED, 0),
3739         GATE(CLK_SCLK_APOLLO, "sclk_apollo", "div_apollo2",
3740                         ENABLE_SCLK_APOLLO, 0,
3741                         CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
3742 };
3743
3744 static struct samsung_cmu_info apollo_cmu_info __initdata = {
3745         .pll_clks               = apollo_pll_clks,
3746         .nr_pll_clks            = ARRAY_SIZE(apollo_pll_clks),
3747         .mux_clks               = apollo_mux_clks,
3748         .nr_mux_clks            = ARRAY_SIZE(apollo_mux_clks),
3749         .div_clks               = apollo_div_clks,
3750         .nr_div_clks            = ARRAY_SIZE(apollo_div_clks),
3751         .gate_clks              = apollo_gate_clks,
3752         .nr_gate_clks           = ARRAY_SIZE(apollo_gate_clks),
3753         .nr_clk_ids             = APOLLO_NR_CLK,
3754         .clk_regs               = apollo_clk_regs,
3755         .nr_clk_regs            = ARRAY_SIZE(apollo_clk_regs),
3756 };
3757
3758 static void __init exynos5433_cmu_apollo_init(struct device_node *np)
3759 {
3760         samsung_cmu_register_one(np, &apollo_cmu_info);
3761 }
3762 CLK_OF_DECLARE(exynos5433_cmu_apollo, "samsung,exynos5433-cmu-apollo",
3763                 exynos5433_cmu_apollo_init);
3764
3765 /*
3766  * Register offset definitions for CMU_ATLAS
3767  */
3768 #define ATLAS_PLL_LOCK                          0x0000
3769 #define ATLAS_PLL_CON0                          0x0100
3770 #define ATLAS_PLL_CON1                          0x0104
3771 #define ATLAS_PLL_FREQ_DET                      0x010c
3772 #define MUX_SEL_ATLAS0                          0x0200
3773 #define MUX_SEL_ATLAS1                          0x0204
3774 #define MUX_SEL_ATLAS2                          0x0208
3775 #define MUX_ENABLE_ATLAS0                       0x0300
3776 #define MUX_ENABLE_ATLAS1                       0x0304
3777 #define MUX_ENABLE_ATLAS2                       0x0308
3778 #define MUX_STAT_ATLAS0                         0x0400
3779 #define MUX_STAT_ATLAS1                         0x0404
3780 #define MUX_STAT_ATLAS2                         0x0408
3781 #define DIV_ATLAS0                              0x0600
3782 #define DIV_ATLAS1                              0x0604
3783 #define DIV_ATLAS_PLL_FREQ_DET                  0x0608
3784 #define DIV_STAT_ATLAS0                         0x0700
3785 #define DIV_STAT_ATLAS1                         0x0704
3786 #define DIV_STAT_ATLAS_PLL_FREQ_DET             0x0708
3787 #define ENABLE_ACLK_ATLAS                       0x0800
3788 #define ENABLE_PCLK_ATLAS                       0x0900
3789 #define ENABLE_SCLK_ATLAS                       0x0a00
3790 #define ENABLE_IP_ATLAS0                        0x0b00
3791 #define ENABLE_IP_ATLAS1                        0x0b04
3792 #define CLKOUT_CMU_ATLAS                        0x0c00
3793 #define CLKOUT_CMU_ATLAS_DIV_STAT               0x0c04
3794 #define ARMCLK_STOPCTRL                         0x1000
3795 #define ATLAS_PWR_CTRL                          0x1020
3796 #define ATLAS_PWR_CTRL2                         0x1024
3797 #define ATLAS_INTR_SPREAD_ENABLE                0x1080
3798 #define ATLAS_INTR_SPREAD_USE_STANDBYWFI        0x1084
3799 #define ATLAS_INTR_SPREAD_BLOCKING_DURATION     0x1088
3800
3801 static unsigned long atlas_clk_regs[] __initdata = {
3802         ATLAS_PLL_LOCK,
3803         ATLAS_PLL_CON0,
3804         ATLAS_PLL_CON1,
3805         ATLAS_PLL_FREQ_DET,
3806         MUX_SEL_ATLAS0,
3807         MUX_SEL_ATLAS1,
3808         MUX_SEL_ATLAS2,
3809         MUX_ENABLE_ATLAS0,
3810         MUX_ENABLE_ATLAS1,
3811         MUX_ENABLE_ATLAS2,
3812         DIV_ATLAS0,
3813         DIV_ATLAS1,
3814         DIV_ATLAS_PLL_FREQ_DET,
3815         ENABLE_ACLK_ATLAS,
3816         ENABLE_PCLK_ATLAS,
3817         ENABLE_SCLK_ATLAS,
3818         ENABLE_IP_ATLAS0,
3819         ENABLE_IP_ATLAS1,
3820         CLKOUT_CMU_ATLAS,
3821         CLKOUT_CMU_ATLAS_DIV_STAT,
3822         ARMCLK_STOPCTRL,
3823         ATLAS_PWR_CTRL,
3824         ATLAS_PWR_CTRL2,
3825         ATLAS_INTR_SPREAD_ENABLE,
3826         ATLAS_INTR_SPREAD_USE_STANDBYWFI,
3827         ATLAS_INTR_SPREAD_BLOCKING_DURATION,
3828 };
3829
3830 /* list of all parent clock list */
3831 PNAME(mout_atlas_pll_p)                 = { "oscclk", "fout_atlas_pll", };
3832 PNAME(mout_bus_pll_atlas_user_p)        = { "oscclk", "sclk_bus_pll_atlas", };
3833 PNAME(mout_atlas_p)                     = { "mout_atlas_pll",
3834                                             "mout_bus_pll_atlas_user", };
3835
3836 static struct samsung_pll_clock atlas_pll_clks[] __initdata = {
3837         PLL(pll_35xx, CLK_FOUT_ATLAS_PLL, "fout_atlas_pll", "oscclk",
3838                 ATLAS_PLL_LOCK, ATLAS_PLL_CON0, exynos5443_pll_rates),
3839 };
3840
3841 static struct samsung_mux_clock atlas_mux_clks[] __initdata = {
3842         /* MUX_SEL_ATLAS0 */
3843         MUX_F(CLK_MOUT_ATLAS_PLL, "mout_atlas_pll", mout_atlas_pll_p,
3844                         MUX_SEL_ATLAS0, 0, 1, CLK_SET_RATE_PARENT, 0),
3845
3846         /* MUX_SEL_ATLAS1 */
3847         MUX(CLK_MOUT_BUS_PLL_ATLAS_USER, "mout_bus_pll_atlas_user",
3848                         mout_bus_pll_atlas_user_p, MUX_SEL_ATLAS1, 0, 1),
3849
3850         /* MUX_SEL_ATLAS2 */
3851         MUX_F(CLK_MOUT_ATLAS, "mout_atlas", mout_atlas_p, MUX_SEL_ATLAS2,
3852                         0, 1, CLK_SET_RATE_PARENT, 0),
3853 };
3854
3855 static struct samsung_div_clock atlas_div_clks[] __initdata = {
3856         /* DIV_ATLAS0 */
3857         DIV_F(CLK_DIV_CNTCLK_ATLAS, "div_cntclk_atlas", "div_atlas2",
3858                         DIV_ATLAS0, 24, 3, CLK_GET_RATE_NOCACHE,
3859                         CLK_DIVIDER_READ_ONLY),
3860         DIV_F(CLK_DIV_PCLK_DBG_ATLAS, "div_pclk_dbg_atlas", "div_atclk_atlas",
3861                         DIV_ATLAS0, 20, 3, CLK_GET_RATE_NOCACHE,
3862                         CLK_DIVIDER_READ_ONLY),
3863         DIV_F(CLK_DIV_ATCLK_ATLASO, "div_atclk_atlas", "div_atlas2",
3864                         DIV_ATLAS0, 16, 3, CLK_GET_RATE_NOCACHE,
3865                         CLK_DIVIDER_READ_ONLY),
3866         DIV_F(CLK_DIV_PCLK_ATLAS, "div_pclk_atlas", "div_atlas2",
3867                         DIV_ATLAS0, 12, 3, CLK_GET_RATE_NOCACHE,
3868                         CLK_DIVIDER_READ_ONLY),
3869         DIV_F(CLK_DIV_ACLK_ATLAS, "div_aclk_atlas", "div_atlas2",
3870                         DIV_ATLAS0, 8, 3, CLK_GET_RATE_NOCACHE,
3871                         CLK_DIVIDER_READ_ONLY),
3872         DIV_F(CLK_DIV_ATLAS2, "div_atlas2", "div_atlas1",
3873                         DIV_ATLAS0, 4, 3, CLK_SET_RATE_PARENT, 0),
3874         DIV_F(CLK_DIV_ATLAS1, "div_atlas1", "mout_atlas",
3875                         DIV_ATLAS0, 0, 3, CLK_SET_RATE_PARENT, 0),
3876
3877         /* DIV_ATLAS1 */
3878         DIV_F(CLK_DIV_SCLK_HPM_ATLAS, "div_sclk_hpm_atlas", "mout_atlas",
3879                         DIV_ATLAS1, 4, 3, CLK_GET_RATE_NOCACHE,
3880                         CLK_DIVIDER_READ_ONLY),
3881         DIV_F(CLK_DIV_ATLAS_PLL, "div_atlas_pll", "mout_atlas",
3882                         DIV_ATLAS1, 0, 3, CLK_GET_RATE_NOCACHE,
3883                         CLK_DIVIDER_READ_ONLY),
3884 };
3885
3886 static struct samsung_gate_clock atlas_gate_clks[] __initdata = {
3887         /* ENABLE_ACLK_ATLAS */
3888         GATE(CLK_ACLK_ATB_AUD_CSSYS, "aclk_atb_aud_cssys",
3889                         "div_atclk_atlas", ENABLE_ACLK_ATLAS,
3890                         9, CLK_IGNORE_UNUSED, 0),
3891         GATE(CLK_ACLK_ATB_APOLLO3_CSSYS, "aclk_atb_apollo3_cssys",
3892                         "div_atclk_atlas", ENABLE_ACLK_ATLAS,
3893                         8, CLK_IGNORE_UNUSED, 0),
3894         GATE(CLK_ACLK_ATB_APOLLO2_CSSYS, "aclk_atb_apollo2_cssys",
3895                         "div_atclk_atlas", ENABLE_ACLK_ATLAS,
3896                         7, CLK_IGNORE_UNUSED, 0),
3897         GATE(CLK_ACLK_ATB_APOLLO1_CSSYS, "aclk_atb_apollo1_cssys",
3898                         "div_atclk_atlas", ENABLE_ACLK_ATLAS,
3899                         6, CLK_IGNORE_UNUSED, 0),
3900         GATE(CLK_ACLK_ATB_APOLLO0_CSSYS, "aclk_atb_apollo0_cssys",
3901                         "div_atclk_atlas", ENABLE_ACLK_ATLAS,
3902                         5, CLK_IGNORE_UNUSED, 0),
3903         GATE(CLK_ACLK_ASYNCAHBS_CSSYS_SSS, "aclk_asyncahbs_cssys_sss",
3904                         "div_atclk_atlas", ENABLE_ACLK_ATLAS,
3905                         4, CLK_IGNORE_UNUSED, 0),
3906         GATE(CLK_ACLK_ASYNCAXIS_CSSYS_CCIX, "aclk_asyncaxis_cssys_ccix",
3907                         "div_pclk_dbg_atlas", ENABLE_ACLK_ATLAS,
3908                         3, CLK_IGNORE_UNUSED, 0),
3909         GATE(CLK_ACLK_ASYNCACES_ATLAS_CCI, "aclk_asyncaces_atlas_cci",
3910                         "div_aclk_atlas", ENABLE_ACLK_ATLAS,
3911                         2, CLK_IGNORE_UNUSED, 0),
3912         GATE(CLK_ACLK_AHB2APB_ATLASP, "aclk_ahb2apb_atlasp", "div_pclk_atlas",
3913                         ENABLE_ACLK_ATLAS, 1, CLK_IGNORE_UNUSED, 0),
3914         GATE(CLK_ACLK_ATLASNP_200, "aclk_atlasnp_200", "div_pclk_atlas",
3915                         ENABLE_ACLK_ATLAS, 0, CLK_IGNORE_UNUSED, 0),
3916
3917         /* ENABLE_PCLK_ATLAS */
3918         GATE(CLK_PCLK_ASYNCAPB_AUD_CSSYS, "pclk_asyncapb_aud_cssys",
3919                         "div_pclk_dbg_atlas", ENABLE_PCLK_ATLAS,
3920                         5, CLK_IGNORE_UNUSED, 0),
3921         GATE(CLK_PCLK_ASYNCAPB_ISP_CSSYS, "pclk_asyncapb_isp_cssys",
3922                         "div_pclk_dbg_atlas", ENABLE_PCLK_ATLAS,
3923                         4, CLK_IGNORE_UNUSED, 0),
3924         GATE(CLK_PCLK_ASYNCAPB_APOLLO_CSSYS, "pclk_asyncapb_apollo_cssys",
3925                         "div_pclk_dbg_atlas", ENABLE_PCLK_ATLAS,
3926                         3, CLK_IGNORE_UNUSED, 0),
3927         GATE(CLK_PCLK_PMU_ATLAS, "pclk_pmu_atlas", "div_pclk_atlas",
3928                         ENABLE_PCLK_ATLAS, 2, CLK_IGNORE_UNUSED, 0),
3929         GATE(CLK_PCLK_SYSREG_ATLAS, "pclk_sysreg_atlas", "div_pclk_atlas",
3930                         ENABLE_PCLK_ATLAS, 1, CLK_IGNORE_UNUSED, 0),
3931         GATE(CLK_PCLK_SECJTAG, "pclk_secjtag", "div_pclk_dbg_atlas",
3932                         ENABLE_PCLK_ATLAS, 0, CLK_IGNORE_UNUSED, 0),
3933
3934         /* ENABLE_SCLK_ATLAS */
3935         GATE(CLK_CNTCLK_ATLAS, "cntclk_atlas", "div_cntclk_atlas",
3936                         ENABLE_SCLK_ATLAS, 10, CLK_IGNORE_UNUSED, 0),
3937         GATE(CLK_SCLK_HPM_ATLAS, "sclk_hpm_atlas", "div_sclk_hpm_atlas",
3938                         ENABLE_SCLK_ATLAS, 7, CLK_IGNORE_UNUSED, 0),
3939         GATE(CLK_TRACECLK, "traceclk", "div_atclk_atlas",
3940                         ENABLE_SCLK_ATLAS, 6, CLK_IGNORE_UNUSED, 0),
3941         GATE(CLK_CTMCLK, "ctmclk", "div_atclk_atlas",
3942                         ENABLE_SCLK_ATLAS, 5, CLK_IGNORE_UNUSED, 0),
3943         GATE(CLK_HCLK_CSSYS, "hclk_cssys", "div_atclk_atlas",
3944                         ENABLE_SCLK_ATLAS, 4, CLK_IGNORE_UNUSED, 0),
3945         GATE(CLK_PCLK_DBG_CSSYS, "pclk_dbg_cssys", "div_pclk_dbg_atlas",
3946                         ENABLE_SCLK_ATLAS, 3, CLK_IGNORE_UNUSED, 0),
3947         GATE(CLK_PCLK_DBG, "pclk_dbg", "div_pclk_dbg_atlas",
3948                         ENABLE_SCLK_ATLAS, 2, CLK_IGNORE_UNUSED, 0),
3949         GATE(CLK_ATCLK, "atclk", "div_atclk_atlas",
3950                         ENABLE_SCLK_ATLAS, 1, CLK_IGNORE_UNUSED, 0),
3951         GATE(CLK_SCLK_ATLAS, "sclk_atlas", "div_atlas2",
3952                         ENABLE_SCLK_ATLAS, 0,
3953                         CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
3954 };
3955
3956 static struct samsung_cmu_info atlas_cmu_info __initdata = {
3957         .pll_clks               = atlas_pll_clks,
3958         .nr_pll_clks            = ARRAY_SIZE(atlas_pll_clks),
3959         .mux_clks               = atlas_mux_clks,
3960         .nr_mux_clks            = ARRAY_SIZE(atlas_mux_clks),
3961         .div_clks               = atlas_div_clks,
3962         .nr_div_clks            = ARRAY_SIZE(atlas_div_clks),
3963         .gate_clks              = atlas_gate_clks,
3964         .nr_gate_clks           = ARRAY_SIZE(atlas_gate_clks),
3965         .nr_clk_ids             = ATLAS_NR_CLK,
3966         .clk_regs               = atlas_clk_regs,
3967         .nr_clk_regs            = ARRAY_SIZE(atlas_clk_regs),
3968 };
3969
3970 static void __init exynos5433_cmu_atlas_init(struct device_node *np)
3971 {
3972         samsung_cmu_register_one(np, &atlas_cmu_info);
3973 }
3974 CLK_OF_DECLARE(exynos5433_cmu_atlas, "samsung,exynos5433-cmu-atlas",
3975                 exynos5433_cmu_atlas_init);
3976
3977 /*
3978  * Register offset definitions for CMU_MSCL
3979  */
3980 #define MUX_SEL_MSCL0                                   0x0200
3981 #define MUX_SEL_MSCL1                                   0x0204
3982 #define MUX_ENABLE_MSCL0                                0x0300
3983 #define MUX_ENABLE_MSCL1                                0x0304
3984 #define MUX_STAT_MSCL0                                  0x0400
3985 #define MUX_STAT_MSCL1                                  0x0404
3986 #define DIV_MSCL                                        0x0600
3987 #define DIV_STAT_MSCL                                   0x0700
3988 #define ENABLE_ACLK_MSCL                                0x0800
3989 #define ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER0         0x0804
3990 #define ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER1         0x0808
3991 #define ENABLE_ACLK_MSCL_SECURE_SMMU_JPEG               0x080c
3992 #define ENABLE_PCLK_MSCL                                0x0900
3993 #define ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER0         0x0904
3994 #define ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER1         0x0908
3995 #define ENABLE_PCLK_MSCL_SECURE_SMMU_JPEG               0x090c
3996 #define ENABLE_SCLK_MSCL                                0x0a00
3997 #define ENABLE_IP_MSCL0                                 0x0b00
3998 #define ENABLE_IP_MSCL1                                 0x0b04
3999 #define ENABLE_IP_MSCL_SECURE_SMMU_M2MSCALER0           0x0b08
4000 #define ENABLE_IP_MSCL_SECURE_SMMU_M2MSCALER1           0x0b0c
4001 #define ENABLE_IP_MSCL_SECURE_SMMU_JPEG                 0x0b10
4002
4003 static unsigned long mscl_clk_regs[] __initdata = {
4004         MUX_SEL_MSCL0,
4005         MUX_SEL_MSCL1,
4006         MUX_ENABLE_MSCL0,
4007         MUX_ENABLE_MSCL1,
4008         DIV_MSCL,
4009         ENABLE_ACLK_MSCL,
4010         ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER0,
4011         ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER1,
4012         ENABLE_ACLK_MSCL_SECURE_SMMU_JPEG,
4013         ENABLE_PCLK_MSCL,
4014         ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER0,
4015         ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER1,
4016         ENABLE_PCLK_MSCL_SECURE_SMMU_JPEG,
4017         ENABLE_SCLK_MSCL,
4018         ENABLE_IP_MSCL0,
4019         ENABLE_IP_MSCL1,
4020         ENABLE_IP_MSCL_SECURE_SMMU_M2MSCALER0,
4021         ENABLE_IP_MSCL_SECURE_SMMU_M2MSCALER1,
4022         ENABLE_IP_MSCL_SECURE_SMMU_JPEG,
4023 };
4024
4025 /* list of all parent clock list */
4026 PNAME(mout_sclk_jpeg_user_p)            = { "oscclk", "sclk_jpeg_mscl", };
4027 PNAME(mout_aclk_mscl_400_user_p)        = { "oscclk", "aclk_mscl_400", };
4028 PNAME(mout_sclk_jpeg_p)                 = { "mout_sclk_jpeg_user",
4029                                         "mout_aclk_mscl_400_user", };
4030
4031 static struct samsung_mux_clock mscl_mux_clks[] __initdata = {
4032         /* MUX_SEL_MSCL0 */
4033         MUX(CLK_MOUT_SCLK_JPEG_USER, "mout_sclk_jpeg_user",
4034                         mout_sclk_jpeg_user_p, MUX_SEL_MSCL0, 4, 1),
4035         MUX(CLK_MOUT_ACLK_MSCL_400_USER, "mout_aclk_mscl_400_user",
4036                         mout_aclk_mscl_400_user_p, MUX_SEL_MSCL0, 0, 1),
4037
4038         /* MUX_SEL_MSCL1 */
4039         MUX(CLK_MOUT_SCLK_JPEG, "mout_sclk_jpeg", mout_sclk_jpeg_p,
4040                         MUX_SEL_MSCL1, 0, 1),
4041 };
4042
4043 static struct samsung_div_clock mscl_div_clks[] __initdata = {
4044         /* DIV_MSCL */
4045         DIV(CLK_DIV_PCLK_MSCL, "div_pclk_mscl", "mout_aclk_mscl_400_user",
4046                         DIV_MSCL, 0, 3),
4047 };
4048
4049 static struct samsung_gate_clock mscl_gate_clks[] __initdata = {
4050         /* ENABLE_ACLK_MSCL */
4051         GATE(CLK_ACLK_BTS_JPEG, "aclk_bts_jpeg", "mout_aclk_mscl_400_user",
4052                         ENABLE_ACLK_MSCL, 9, 0, 0),
4053         GATE(CLK_ACLK_BTS_M2MSCALER1, "aclk_bts_m2mscaler1",
4054                         "mout_aclk_mscl_400_user", ENABLE_ACLK_MSCL, 8, 0, 0),
4055         GATE(CLK_ACLK_BTS_M2MSCALER0, "aclk_bts_m2mscaler0",
4056                         "mout_aclk_mscl_400_user", ENABLE_ACLK_MSCL, 7, 0, 0),
4057         GATE(CLK_ACLK_AHB2APB_MSCL0P, "aclk_abh2apb_mscl0p", "div_pclk_mscl",
4058                         ENABLE_ACLK_MSCL, 6, CLK_IGNORE_UNUSED, 0),
4059         GATE(CLK_ACLK_XIU_MSCLX, "aclk_xiu_msclx", "mout_aclk_mscl_400_user",
4060                         ENABLE_ACLK_MSCL, 5, CLK_IGNORE_UNUSED, 0),
4061         GATE(CLK_ACLK_MSCLNP_100, "aclk_msclnp_100", "div_pclk_mscl",
4062                         ENABLE_ACLK_MSCL, 4, CLK_IGNORE_UNUSED, 0),
4063         GATE(CLK_ACLK_MSCLND_400, "aclk_msclnd_400", "mout_aclk_mscl_400_user",
4064                         ENABLE_ACLK_MSCL, 3, CLK_IGNORE_UNUSED, 0),
4065         GATE(CLK_ACLK_JPEG, "aclk_jpeg", "mout_aclk_mscl_400_user",
4066                         ENABLE_ACLK_MSCL, 2, 0, 0),
4067         GATE(CLK_ACLK_M2MSCALER1, "aclk_m2mscaler1", "mout_aclk_mscl_400_user",
4068                         ENABLE_ACLK_MSCL, 1, 0, 0),
4069         GATE(CLK_ACLK_M2MSCALER0, "aclk_m2mscaler0", "mout_aclk_mscl_400_user",
4070                         ENABLE_ACLK_MSCL, 0, 0, 0),
4071
4072         /* ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER0 */
4073         GATE(CLK_ACLK_SMMU_M2MSCALER0, "aclk_smmu_m2mscaler0",
4074                         "mout_aclk_mscl_400_user",
4075                         ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER0,
4076                         0, CLK_IGNORE_UNUSED, 0),
4077
4078         /* ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER1 */
4079         GATE(CLK_ACLK_SMMU_M2MSCALER1, "aclk_smmu_m2mscaler1",
4080                         "mout_aclk_mscl_400_user",
4081                         ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER1,
4082                         0, CLK_IGNORE_UNUSED, 0),
4083
4084         /* ENABLE_ACLK_MSCL_SECURE_SMMU_JPEG */
4085         GATE(CLK_ACLK_SMMU_JPEG, "aclk_smmu_jpeg", "mout_aclk_mscl_400_user",
4086                         ENABLE_ACLK_MSCL_SECURE_SMMU_JPEG,
4087                         0, CLK_IGNORE_UNUSED, 0),
4088
4089         /* ENABLE_PCLK_MSCL */
4090         GATE(CLK_PCLK_BTS_JPEG, "pclk_bts_jpeg", "div_pclk_mscl",
4091                         ENABLE_PCLK_MSCL, 7, 0, 0),
4092         GATE(CLK_PCLK_BTS_M2MSCALER1, "pclk_bts_m2mscaler1", "div_pclk_mscl",
4093                         ENABLE_PCLK_MSCL, 6, 0, 0),
4094         GATE(CLK_PCLK_BTS_M2MSCALER0, "pclk_bts_m2mscaler0", "div_pclk_mscl",
4095                         ENABLE_PCLK_MSCL, 5, 0, 0),
4096         GATE(CLK_PCLK_PMU_MSCL, "pclk_pmu_mscl", "div_pclk_mscl",
4097                         ENABLE_PCLK_MSCL, 4, CLK_IGNORE_UNUSED, 0),
4098         GATE(CLK_PCLK_SYSREG_MSCL, "pclk_sysreg_mscl", "div_pclk_mscl",
4099                         ENABLE_PCLK_MSCL, 3, CLK_IGNORE_UNUSED, 0),
4100         GATE(CLK_PCLK_JPEG, "pclk_jpeg", "div_pclk_mscl",
4101                         ENABLE_PCLK_MSCL, 2, 0, 0),
4102         GATE(CLK_PCLK_M2MSCALER1, "pclk_m2mscaler1", "div_pclk_mscl",
4103                         ENABLE_PCLK_MSCL, 1, 0, 0),
4104         GATE(CLK_PCLK_M2MSCALER0, "pclk_m2mscaler0", "div_pclk_mscl",
4105                         ENABLE_PCLK_MSCL, 0, 0, 0),
4106
4107         /* ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER0 */
4108         GATE(CLK_PCLK_SMMU_M2MSCALER0, "pclk_smmu_m2mscaler0", "div_pclk_mscl",
4109                         ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER0,
4110                         0, CLK_IGNORE_UNUSED, 0),
4111
4112         /* ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER1 */
4113         GATE(CLK_PCLK_SMMU_M2MSCALER1, "pclk_smmu_m2mscaler1", "div_pclk_mscl",
4114                         ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER1,
4115                         0, CLK_IGNORE_UNUSED, 0),
4116
4117         /* ENABLE_PCLK_MSCL_SECURE_SMMU_JPEG */
4118         GATE(CLK_PCLK_SMMU_JPEG, "pclk_smmu_jpeg", "div_pclk_mscl",
4119                         ENABLE_PCLK_MSCL_SECURE_SMMU_JPEG,
4120                         0, CLK_IGNORE_UNUSED, 0),
4121
4122         /* ENABLE_SCLK_MSCL */
4123         GATE(CLK_SCLK_JPEG, "sclk_jpeg", "mout_sclk_jpeg", ENABLE_SCLK_MSCL, 0,
4124                         CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
4125 };
4126
4127 static struct samsung_cmu_info mscl_cmu_info __initdata = {
4128         .mux_clks               = mscl_mux_clks,
4129         .nr_mux_clks            = ARRAY_SIZE(mscl_mux_clks),
4130         .div_clks               = mscl_div_clks,
4131         .nr_div_clks            = ARRAY_SIZE(mscl_div_clks),
4132         .gate_clks              = mscl_gate_clks,
4133         .nr_gate_clks           = ARRAY_SIZE(mscl_gate_clks),
4134         .nr_clk_ids             = MSCL_NR_CLK,
4135         .clk_regs               = mscl_clk_regs,
4136         .nr_clk_regs            = ARRAY_SIZE(mscl_clk_regs),
4137 };
4138
4139 static void __init exynos5433_cmu_mscl_init(struct device_node *np)
4140 {
4141         samsung_cmu_register_one(np, &mscl_cmu_info);
4142 }
4143 CLK_OF_DECLARE(exynos5433_cmu_mscl, "samsung,exynos5433-cmu-mscl",
4144                 exynos5433_cmu_mscl_init);
4145
4146 /*
4147  * Register offset definitions for CMU_MFC
4148  */
4149 #define MUX_SEL_MFC                             0x0200
4150 #define MUX_ENABLE_MFC                          0x0300
4151 #define MUX_STAT_MFC                            0x0400
4152 #define DIV_MFC                                 0x0600
4153 #define DIV_STAT_MFC                            0x0700
4154 #define ENABLE_ACLK_MFC                         0x0800
4155 #define ENABLE_ACLK_MFC_SECURE_SMMU_MFC         0x0804
4156 #define ENABLE_PCLK_MFC                         0x0900
4157 #define ENABLE_PCLK_MFC_SECURE_SMMU_MFC         0x0904
4158 #define ENABLE_IP_MFC0                          0x0b00
4159 #define ENABLE_IP_MFC1                          0x0b04
4160 #define ENABLE_IP_MFC_SECURE_SMMU_MFC           0x0b08
4161
4162 static unsigned long mfc_clk_regs[] __initdata = {
4163         MUX_SEL_MFC,
4164         MUX_ENABLE_MFC,
4165         DIV_MFC,
4166         ENABLE_ACLK_MFC,
4167         ENABLE_ACLK_MFC_SECURE_SMMU_MFC,
4168         ENABLE_PCLK_MFC,
4169         ENABLE_PCLK_MFC_SECURE_SMMU_MFC,
4170         ENABLE_IP_MFC0,
4171         ENABLE_IP_MFC1,
4172         ENABLE_IP_MFC_SECURE_SMMU_MFC,
4173 };
4174
4175 PNAME(mout_aclk_mfc_400_user_p)         = { "oscclk", "aclk_mfc_400", };
4176
4177 static struct samsung_mux_clock mfc_mux_clks[] __initdata = {
4178         /* MUX_SEL_MFC */
4179         MUX(CLK_MOUT_ACLK_MFC_400_USER, "mout_aclk_mfc_400_user",
4180                         mout_aclk_mfc_400_user_p, MUX_SEL_MFC, 0, 0),
4181 };
4182
4183 static struct samsung_div_clock mfc_div_clks[] __initdata = {
4184         /* DIV_MFC */
4185         DIV(CLK_DIV_PCLK_MFC, "div_pclk_mfc", "mout_aclk_mfc_400_user",
4186                         DIV_MFC, 0, 2),
4187 };
4188
4189 static struct samsung_gate_clock mfc_gate_clks[] __initdata = {
4190         /* ENABLE_ACLK_MFC */
4191         GATE(CLK_ACLK_BTS_MFC_1, "aclk_bts_mfc_1", "mout_aclk_mfc_400_user",
4192                         ENABLE_ACLK_MFC, 6, 0, 0),
4193         GATE(CLK_ACLK_BTS_MFC_0, "aclk_bts_mfc_0", "mout_aclk_mfc_400_user",
4194                         ENABLE_ACLK_MFC, 5, 0, 0),
4195         GATE(CLK_ACLK_AHB2APB_MFCP, "aclk_ahb2apb_mfcp", "div_pclk_mfc",
4196                         ENABLE_ACLK_MFC, 4, CLK_IGNORE_UNUSED, 0),
4197         GATE(CLK_ACLK_XIU_MFCX, "aclk_xiu_mfcx", "mout_aclk_mfc_400_user",
4198                         ENABLE_ACLK_MFC, 3, CLK_IGNORE_UNUSED, 0),
4199         GATE(CLK_ACLK_MFCNP_100, "aclk_mfcnp_100", "div_pclk_mfc",
4200                         ENABLE_ACLK_MFC, 2, CLK_IGNORE_UNUSED, 0),
4201         GATE(CLK_ACLK_MFCND_400, "aclk_mfcnd_400", "mout_aclk_mfc_400_user",
4202                         ENABLE_ACLK_MFC, 1, CLK_IGNORE_UNUSED, 0),
4203         GATE(CLK_ACLK_MFC, "aclk_mfc", "mout_aclk_mfc_400_user",
4204                         ENABLE_ACLK_MFC, 0, 0, 0),
4205
4206         /* ENABLE_ACLK_MFC_SECURE_SMMU_MFC */
4207         GATE(CLK_ACLK_SMMU_MFC_1, "aclk_smmu_mfc_1", "mout_aclk_mfc_400_user",
4208                         ENABLE_ACLK_MFC_SECURE_SMMU_MFC,
4209                         1, CLK_IGNORE_UNUSED, 0),
4210         GATE(CLK_ACLK_SMMU_MFC_0, "aclk_smmu_mfc_0", "mout_aclk_mfc_400_user",
4211                         ENABLE_ACLK_MFC_SECURE_SMMU_MFC,
4212                         0, CLK_IGNORE_UNUSED, 0),
4213
4214         /* ENABLE_PCLK_MFC */
4215         GATE(CLK_PCLK_BTS_MFC_1, "pclk_bts_mfc_1", "div_pclk_mfc",
4216                         ENABLE_PCLK_MFC, 4, 0, 0),
4217         GATE(CLK_PCLK_BTS_MFC_0, "pclk_bts_mfc_0", "div_pclk_mfc",
4218                         ENABLE_PCLK_MFC, 3, 0, 0),
4219         GATE(CLK_PCLK_PMU_MFC, "pclk_pmu_mfc", "div_pclk_mfc",
4220                         ENABLE_PCLK_MFC, 2, CLK_IGNORE_UNUSED, 0),
4221         GATE(CLK_PCLK_SYSREG_MFC, "pclk_sysreg_mfc", "div_pclk_mfc",
4222                         ENABLE_PCLK_MFC, 1, CLK_IGNORE_UNUSED, 0),
4223         GATE(CLK_PCLK_MFC, "pclk_mfc", "div_pclk_mfc",
4224                         ENABLE_PCLK_MFC, 4, CLK_IGNORE_UNUSED, 0),
4225
4226         /* ENABLE_PCLK_MFC_SECURE_SMMU_MFC */
4227         GATE(CLK_PCLK_SMMU_MFC_1, "pclk_smmu_mfc_1", "div_pclk_mfc",
4228                         ENABLE_PCLK_MFC_SECURE_SMMU_MFC,
4229                         1, CLK_IGNORE_UNUSED, 0),
4230         GATE(CLK_PCLK_SMMU_MFC_0, "pclk_smmu_mfc_0", "div_pclk_mfc",
4231                         ENABLE_PCLK_MFC_SECURE_SMMU_MFC,
4232                         0, CLK_IGNORE_UNUSED, 0),
4233 };
4234
4235 static struct samsung_cmu_info mfc_cmu_info __initdata = {
4236         .mux_clks               = mfc_mux_clks,
4237         .nr_mux_clks            = ARRAY_SIZE(mfc_mux_clks),
4238         .div_clks               = mfc_div_clks,
4239         .nr_div_clks            = ARRAY_SIZE(mfc_div_clks),
4240         .gate_clks              = mfc_gate_clks,
4241         .nr_gate_clks           = ARRAY_SIZE(mfc_gate_clks),
4242         .nr_clk_ids             = MFC_NR_CLK,
4243         .clk_regs               = mfc_clk_regs,
4244         .nr_clk_regs            = ARRAY_SIZE(mfc_clk_regs),
4245 };
4246
4247 static void __init exynos5433_cmu_mfc_init(struct device_node *np)
4248 {
4249         samsung_cmu_register_one(np, &mfc_cmu_info);
4250 }
4251 CLK_OF_DECLARE(exynos5433_cmu_mfc, "samsung,exynos5433-cmu-mfc",
4252                 exynos5433_cmu_mfc_init);
4253
4254 /*
4255  * Register offset definitions for CMU_HEVC
4256  */
4257 #define MUX_SEL_HEVC                            0x0200
4258 #define MUX_ENABLE_HEVC                         0x0300
4259 #define MUX_STAT_HEVC                           0x0400
4260 #define DIV_HEVC                                0x0600
4261 #define DIV_STAT_HEVC                           0x0700
4262 #define ENABLE_ACLK_HEVC                        0x0800
4263 #define ENABLE_ACLK_HEVC_SECURE_SMMU_HEVC       0x0804
4264 #define ENABLE_PCLK_HEVC                        0x0900
4265 #define ENABLE_PCLK_HEVC_SECURE_SMMU_HEVC       0x0904
4266 #define ENABLE_IP_HEVC0                         0x0b00
4267 #define ENABLE_IP_HEVC1                         0x0b04
4268 #define ENABLE_IP_HEVC_SECURE_SMMU_HEVC         0x0b08
4269
4270 static unsigned long hevc_clk_regs[] __initdata = {
4271         MUX_SEL_HEVC,
4272         MUX_ENABLE_HEVC,
4273         DIV_HEVC,
4274         ENABLE_ACLK_HEVC,
4275         ENABLE_ACLK_HEVC_SECURE_SMMU_HEVC,
4276         ENABLE_PCLK_HEVC,
4277         ENABLE_PCLK_HEVC_SECURE_SMMU_HEVC,
4278         ENABLE_IP_HEVC0,
4279         ENABLE_IP_HEVC1,
4280         ENABLE_IP_HEVC_SECURE_SMMU_HEVC,
4281 };
4282
4283 PNAME(mout_aclk_hevc_400_user_p)        = { "oscclk", "aclk_hevc_400", };
4284
4285 static struct samsung_mux_clock hevc_mux_clks[] __initdata = {
4286         /* MUX_SEL_HEVC */
4287         MUX(CLK_MOUT_ACLK_HEVC_400_USER, "mout_aclk_hevc_400_user",
4288                         mout_aclk_hevc_400_user_p, MUX_SEL_HEVC, 0, 0),
4289 };
4290
4291 static struct samsung_div_clock hevc_div_clks[] __initdata = {
4292         /* DIV_HEVC */
4293         DIV(CLK_DIV_PCLK_HEVC, "div_pclk_hevc", "mout_aclk_hevc_400_user",
4294                         DIV_HEVC, 0, 2),
4295 };
4296
4297 static struct samsung_gate_clock hevc_gate_clks[] __initdata = {
4298         /* ENABLE_ACLK_HEVC */
4299         GATE(CLK_ACLK_BTS_HEVC_1, "aclk_bts_hevc_1", "mout_aclk_hevc_400_user",
4300                         ENABLE_ACLK_HEVC, 6, 0, 0),
4301         GATE(CLK_ACLK_BTS_HEVC_0, "aclk_bts_hevc_0", "mout_aclk_hevc_400_user",
4302                         ENABLE_ACLK_HEVC, 5, 0, 0),
4303         GATE(CLK_ACLK_AHB2APB_HEVCP, "aclk_ahb2apb_hevcp", "div_pclk_hevc",
4304                         ENABLE_ACLK_HEVC, 4, CLK_IGNORE_UNUSED, 0),
4305         GATE(CLK_ACLK_XIU_HEVCX, "aclk_xiu_hevcx", "mout_aclk_hevc_400_user",
4306                         ENABLE_ACLK_HEVC, 3, CLK_IGNORE_UNUSED, 0),
4307         GATE(CLK_ACLK_HEVCNP_100, "aclk_hevcnp_100", "div_pclk_hevc",
4308                         ENABLE_ACLK_HEVC, 2, CLK_IGNORE_UNUSED, 0),
4309         GATE(CLK_ACLK_HEVCND_400, "aclk_hevcnd_400", "mout_aclk_hevc_400_user",
4310                         ENABLE_ACLK_HEVC, 1, CLK_IGNORE_UNUSED, 0),
4311         GATE(CLK_ACLK_HEVC, "aclk_hevc", "mout_aclk_hevc_400_user",
4312                         ENABLE_ACLK_HEVC, 0, 0, 0),
4313
4314         /* ENABLE_ACLK_HEVC_SECURE_SMMU_HEVC */
4315         GATE(CLK_ACLK_SMMU_HEVC_1, "aclk_smmu_hevc_1",
4316                         "mout_aclk_hevc_400_user",
4317                         ENABLE_ACLK_HEVC_SECURE_SMMU_HEVC,
4318                         1, CLK_IGNORE_UNUSED, 0),
4319         GATE(CLK_ACLK_SMMU_HEVC_0, "aclk_smmu_hevc_0",
4320                         "mout_aclk_hevc_400_user",
4321                         ENABLE_ACLK_HEVC_SECURE_SMMU_HEVC,
4322                         0, CLK_IGNORE_UNUSED, 0),
4323
4324         /* ENABLE_PCLK_HEVC */
4325         GATE(CLK_PCLK_BTS_HEVC_1, "pclk_bts_hevc_1", "div_pclk_hevc",
4326                         ENABLE_PCLK_HEVC, 4, 0, 0),
4327         GATE(CLK_PCLK_BTS_HEVC_0, "pclk_bts_hevc_0", "div_pclk_hevc",
4328                         ENABLE_PCLK_HEVC, 3, 0, 0),
4329         GATE(CLK_PCLK_PMU_HEVC, "pclk_pmu_hevc", "div_pclk_hevc",
4330                         ENABLE_PCLK_HEVC, 2, CLK_IGNORE_UNUSED, 0),
4331         GATE(CLK_PCLK_SYSREG_HEVC, "pclk_sysreg_hevc", "div_pclk_hevc",
4332                         ENABLE_PCLK_HEVC, 1, CLK_IGNORE_UNUSED, 0),
4333         GATE(CLK_PCLK_HEVC, "pclk_hevc", "div_pclk_hevc",
4334                         ENABLE_PCLK_HEVC, 4, CLK_IGNORE_UNUSED, 0),
4335
4336         /* ENABLE_PCLK_HEVC_SECURE_SMMU_HEVC */
4337         GATE(CLK_PCLK_SMMU_HEVC_1, "pclk_smmu_hevc_1", "div_pclk_hevc",
4338                         ENABLE_PCLK_HEVC_SECURE_SMMU_HEVC,
4339                         1, CLK_IGNORE_UNUSED, 0),
4340         GATE(CLK_PCLK_SMMU_HEVC_0, "pclk_smmu_hevc_0", "div_pclk_hevc",
4341                         ENABLE_PCLK_HEVC_SECURE_SMMU_HEVC,
4342                         0, CLK_IGNORE_UNUSED, 0),
4343 };
4344
4345 static struct samsung_cmu_info hevc_cmu_info __initdata = {
4346         .mux_clks               = hevc_mux_clks,
4347         .nr_mux_clks            = ARRAY_SIZE(hevc_mux_clks),
4348         .div_clks               = hevc_div_clks,
4349         .nr_div_clks            = ARRAY_SIZE(hevc_div_clks),
4350         .gate_clks              = hevc_gate_clks,
4351         .nr_gate_clks           = ARRAY_SIZE(hevc_gate_clks),
4352         .nr_clk_ids             = HEVC_NR_CLK,
4353         .clk_regs               = hevc_clk_regs,
4354         .nr_clk_regs            = ARRAY_SIZE(hevc_clk_regs),
4355 };
4356
4357 static void __init exynos5433_cmu_hevc_init(struct device_node *np)
4358 {
4359         samsung_cmu_register_one(np, &hevc_cmu_info);
4360 }
4361 CLK_OF_DECLARE(exynos5433_cmu_hevc, "samsung,exynos5433-cmu-hevc",
4362                 exynos5433_cmu_hevc_init);
4363
4364 /*
4365  * Register offset definitions for CMU_ISP
4366  */
4367 #define MUX_SEL_ISP                     0x0200
4368 #define MUX_ENABLE_ISP                  0x0300
4369 #define MUX_STAT_ISP                    0x0400
4370 #define DIV_ISP                         0x0600
4371 #define DIV_STAT_ISP                    0x0700
4372 #define ENABLE_ACLK_ISP0                0x0800
4373 #define ENABLE_ACLK_ISP1                0x0804
4374 #define ENABLE_ACLK_ISP2                0x0808
4375 #define ENABLE_PCLK_ISP                 0x0900
4376 #define ENABLE_SCLK_ISP                 0x0a00
4377 #define ENABLE_IP_ISP0                  0x0b00
4378 #define ENABLE_IP_ISP1                  0x0b04
4379 #define ENABLE_IP_ISP2                  0x0b08
4380 #define ENABLE_IP_ISP3                  0x0b0c
4381
4382 static unsigned long isp_clk_regs[] __initdata = {
4383         MUX_SEL_ISP,
4384         MUX_ENABLE_ISP,
4385         DIV_ISP,
4386         ENABLE_ACLK_ISP0,
4387         ENABLE_ACLK_ISP1,
4388         ENABLE_ACLK_ISP2,
4389         ENABLE_PCLK_ISP,
4390         ENABLE_SCLK_ISP,
4391         ENABLE_IP_ISP0,
4392         ENABLE_IP_ISP1,
4393         ENABLE_IP_ISP2,
4394         ENABLE_IP_ISP3,
4395 };
4396
4397 PNAME(mout_aclk_isp_dis_400_user_p)     = { "oscclk", "aclk_isp_dis_400", };
4398 PNAME(mout_aclk_isp_400_user_p)         = { "oscclk", "aclk_isp_400", };
4399
4400 static struct samsung_mux_clock isp_mux_clks[] __initdata = {
4401         /* MUX_SEL_ISP */
4402         MUX(CLK_MOUT_ACLK_ISP_DIS_400_USER, "mout_aclk_isp_dis_400_user",
4403                         mout_aclk_isp_dis_400_user_p, MUX_SEL_ISP, 4, 0),
4404         MUX(CLK_MOUT_ACLK_ISP_400_USER, "mout_aclk_isp_400_user",
4405                         mout_aclk_isp_400_user_p, MUX_SEL_ISP, 0, 0),
4406 };
4407
4408 static struct samsung_div_clock isp_div_clks[] __initdata = {
4409         /* DIV_ISP */
4410         DIV(CLK_DIV_PCLK_ISP_DIS, "div_pclk_isp_dis",
4411                         "mout_aclk_isp_dis_400_user", DIV_ISP, 12, 3),
4412         DIV(CLK_DIV_PCLK_ISP, "div_pclk_isp", "mout_aclk_isp_400_user",
4413                         DIV_ISP, 8, 3),
4414         DIV(CLK_DIV_ACLK_ISP_D_200, "div_aclk_isp_d_200",
4415                         "mout_aclk_isp_400_user", DIV_ISP, 4, 3),
4416         DIV(CLK_DIV_ACLK_ISP_C_200, "div_aclk_isp_c_200",
4417                         "mout_aclk_isp_400_user", DIV_ISP, 0, 3),
4418 };
4419
4420 static struct samsung_gate_clock isp_gate_clks[] __initdata = {
4421         /* ENABLE_ACLK_ISP0 */
4422         GATE(CLK_ACLK_ISP_D_GLUE, "aclk_isp_d_glue", "mout_aclk_isp_400_user",
4423                         ENABLE_ACLK_ISP0, 6, CLK_IGNORE_UNUSED, 0),
4424         GATE(CLK_ACLK_SCALERP, "aclk_scalerp", "mout_aclk_isp_400_user",
4425                         ENABLE_ACLK_ISP0, 5, CLK_IGNORE_UNUSED, 0),
4426         GATE(CLK_ACLK_3DNR, "aclk_3dnr", "mout_aclk_isp_400_user",
4427                         ENABLE_ACLK_ISP0, 4, CLK_IGNORE_UNUSED, 0),
4428         GATE(CLK_ACLK_DIS, "aclk_dis", "mout_aclk_isp_dis_400_user",
4429                         ENABLE_ACLK_ISP0, 3, CLK_IGNORE_UNUSED, 0),
4430         GATE(CLK_ACLK_SCALERC, "aclk_scalerc", "mout_aclk_isp_400_user",
4431                         ENABLE_ACLK_ISP0, 2, CLK_IGNORE_UNUSED, 0),
4432         GATE(CLK_ACLK_DRC, "aclk_drc", "mout_aclk_isp_400_user",
4433                         ENABLE_ACLK_ISP0, 1, CLK_IGNORE_UNUSED, 0),
4434         GATE(CLK_ACLK_ISP, "aclk_isp", "mout_aclk_isp_400_user",
4435                         ENABLE_ACLK_ISP0, 0, CLK_IGNORE_UNUSED, 0),
4436
4437         /* ENABLE_ACLK_ISP1 */
4438         GATE(CLK_ACLK_AXIUS_SCALERP, "aclk_axius_scalerp",
4439                         "mout_aclk_isp_400_user", ENABLE_ACLK_ISP1,
4440                         17, CLK_IGNORE_UNUSED, 0),
4441         GATE(CLK_ACLK_AXIUS_SCALERC, "aclk_axius_scalerc",
4442                         "mout_aclk_isp_400_user", ENABLE_ACLK_ISP1,
4443                         16, CLK_IGNORE_UNUSED, 0),
4444         GATE(CLK_ACLK_AXIUS_DRC, "aclk_axius_drc",
4445                         "mout_aclk_isp_400_user", ENABLE_ACLK_ISP1,
4446                         15, CLK_IGNORE_UNUSED, 0),
4447         GATE(CLK_ACLK_ASYNCAHBM_ISP2P, "aclk_asyncahbm_isp2p",
4448                         "div_pclk_isp", ENABLE_ACLK_ISP1,
4449                         14, CLK_IGNORE_UNUSED, 0),
4450         GATE(CLK_ACLK_ASYNCAHBM_ISP1P, "aclk_asyncahbm_isp1p",
4451                         "div_pclk_isp", ENABLE_ACLK_ISP1,
4452                         13, CLK_IGNORE_UNUSED, 0),
4453         GATE(CLK_ACLK_ASYNCAXIS_DIS1, "aclk_asyncaxis_dis1",
4454                         "mout_aclk_isp_dis_400_user", ENABLE_ACLK_ISP1,
4455                         12, CLK_IGNORE_UNUSED, 0),
4456         GATE(CLK_ACLK_ASYNCAXIS_DIS0, "aclk_asyncaxis_dis0",
4457                         "mout_aclk_isp_dis_400_user", ENABLE_ACLK_ISP1,
4458                         11, CLK_IGNORE_UNUSED, 0),
4459         GATE(CLK_ACLK_ASYNCAXIM_DIS1, "aclk_asyncaxim_dis1",
4460                         "mout_aclk_isp_400_user", ENABLE_ACLK_ISP1,
4461                         10, CLK_IGNORE_UNUSED, 0),
4462         GATE(CLK_ACLK_ASYNCAXIM_DIS0, "aclk_asyncaxim_dis0",
4463                         "mout_aclk_isp_400_user", ENABLE_ACLK_ISP1,
4464                         9, CLK_IGNORE_UNUSED, 0),
4465         GATE(CLK_ACLK_ASYNCAXIM_ISP2P, "aclk_asyncaxim_isp2p",
4466                         "div_aclk_isp_d_200", ENABLE_ACLK_ISP1,
4467                         8, CLK_IGNORE_UNUSED, 0),
4468         GATE(CLK_ACLK_ASYNCAXIM_ISP1P, "aclk_asyncaxim_isp1p",
4469                         "div_aclk_isp_c_200", ENABLE_ACLK_ISP1,
4470                         7, CLK_IGNORE_UNUSED, 0),
4471         GATE(CLK_ACLK_AHB2APB_ISP2P, "aclk_ahb2apb_isp2p", "div_pclk_isp",
4472                         ENABLE_ACLK_ISP1, 6, CLK_IGNORE_UNUSED, 0),
4473         GATE(CLK_ACLK_AHB2APB_ISP1P, "aclk_ahb2apb_isp1p", "div_pclk_isp",
4474                         ENABLE_ACLK_ISP1, 5, CLK_IGNORE_UNUSED, 0),
4475         GATE(CLK_ACLK_AXI2APB_ISP2P, "aclk_axi2apb_isp2p",
4476                         "div_aclk_isp_d_200", ENABLE_ACLK_ISP1,
4477                         4, CLK_IGNORE_UNUSED, 0),
4478         GATE(CLK_ACLK_AXI2APB_ISP1P, "aclk_axi2apb_isp1p",
4479                         "div_aclk_isp_c_200", ENABLE_ACLK_ISP1,
4480                         3, CLK_IGNORE_UNUSED, 0),
4481         GATE(CLK_ACLK_XIU_ISPEX1, "aclk_xiu_ispex1", "mout_aclk_isp_400_user",
4482                         ENABLE_ACLK_ISP1, 2, CLK_IGNORE_UNUSED, 0),
4483         GATE(CLK_ACLK_XIU_ISPEX0, "aclk_xiu_ispex0", "mout_aclk_isp_400_user",
4484                         ENABLE_ACLK_ISP1, 1, CLK_IGNORE_UNUSED, 0),
4485         GATE(CLK_ACLK_ISPND_400, "aclk_ispnd_400", "mout_aclk_isp_400_user",
4486                         ENABLE_ACLK_ISP1, 1, CLK_IGNORE_UNUSED, 0),
4487
4488         /* ENABLE_ACLK_ISP2 */
4489         GATE(CLK_ACLK_SMMU_SCALERP, "aclk_smmu_scalerp",
4490                         "mout_aclk_isp_400_user", ENABLE_ACLK_ISP2,
4491                         13, CLK_IGNORE_UNUSED, 0),
4492         GATE(CLK_ACLK_SMMU_3DNR, "aclk_smmu_3dnr", "mout_aclk_isp_400_user",
4493                         ENABLE_ACLK_ISP2, 12, CLK_IGNORE_UNUSED, 0),
4494         GATE(CLK_ACLK_SMMU_DIS1, "aclk_smmu_dis1", "mout_aclk_isp_400_user",
4495                         ENABLE_ACLK_ISP2, 11, CLK_IGNORE_UNUSED, 0),
4496         GATE(CLK_ACLK_SMMU_DIS0, "aclk_smmu_dis0", "mout_aclk_isp_400_user",
4497                         ENABLE_ACLK_ISP2, 10, CLK_IGNORE_UNUSED, 0),
4498         GATE(CLK_ACLK_SMMU_SCALERC, "aclk_smmu_scalerc",
4499                         "mout_aclk_isp_400_user", ENABLE_ACLK_ISP2,
4500                         9, CLK_IGNORE_UNUSED, 0),
4501         GATE(CLK_ACLK_SMMU_DRC, "aclk_smmu_drc", "mout_aclk_isp_400_user",
4502                         ENABLE_ACLK_ISP2, 8, CLK_IGNORE_UNUSED, 0),
4503         GATE(CLK_ACLK_SMMU_ISP, "aclk_smmu_isp", "mout_aclk_isp_400_user",
4504                         ENABLE_ACLK_ISP2, 7, CLK_IGNORE_UNUSED, 0),
4505         GATE(CLK_ACLK_BTS_SCALERP, "aclk_bts_scalerp",
4506                         "mout_aclk_isp_400_user", ENABLE_ACLK_ISP2,
4507                         6, CLK_IGNORE_UNUSED, 0),
4508         GATE(CLK_ACLK_BTS_3DR, "aclk_bts_3dnr", "mout_aclk_isp_400_user",
4509                         ENABLE_ACLK_ISP2, 5, CLK_IGNORE_UNUSED, 0),
4510         GATE(CLK_ACLK_BTS_DIS1, "aclk_bts_dis1", "mout_aclk_isp_400_user",
4511                         ENABLE_ACLK_ISP2, 4, CLK_IGNORE_UNUSED, 0),
4512         GATE(CLK_ACLK_BTS_DIS0, "aclk_bts_dis0", "mout_aclk_isp_400_user",
4513                         ENABLE_ACLK_ISP2, 3, CLK_IGNORE_UNUSED, 0),
4514         GATE(CLK_ACLK_BTS_SCALERC, "aclk_bts_scalerc",
4515                         "mout_aclk_isp_400_user", ENABLE_ACLK_ISP2,
4516                         2, CLK_IGNORE_UNUSED, 0),
4517         GATE(CLK_ACLK_BTS_DRC, "aclk_bts_drc", "mout_aclk_isp_400_user",
4518                         ENABLE_ACLK_ISP2, 1, CLK_IGNORE_UNUSED, 0),
4519         GATE(CLK_ACLK_BTS_ISP, "aclk_bts_isp", "mout_aclk_isp_400_user",
4520                         ENABLE_ACLK_ISP2, 0, CLK_IGNORE_UNUSED, 0),
4521
4522         /* ENABLE_PCLK_ISP */
4523         GATE(CLK_PCLK_SMMU_SCALERP, "pclk_smmu_scalerp", "div_aclk_isp_d_200",
4524                         ENABLE_PCLK_ISP, 25, CLK_IGNORE_UNUSED, 0),
4525         GATE(CLK_PCLK_SMMU_3DNR, "pclk_smmu_3dnr", "div_aclk_isp_d_200",
4526                         ENABLE_PCLK_ISP, 24, CLK_IGNORE_UNUSED, 0),
4527         GATE(CLK_PCLK_SMMU_DIS1, "pclk_smmu_dis1", "div_aclk_isp_d_200",
4528                         ENABLE_PCLK_ISP, 23, CLK_IGNORE_UNUSED, 0),
4529         GATE(CLK_PCLK_SMMU_DIS0, "pclk_smmu_dis0", "div_aclk_isp_d_200",
4530                         ENABLE_PCLK_ISP, 22, CLK_IGNORE_UNUSED, 0),
4531         GATE(CLK_PCLK_SMMU_SCALERC, "pclk_smmu_scalerc", "div_aclk_isp_c_200",
4532                         ENABLE_PCLK_ISP, 21, CLK_IGNORE_UNUSED, 0),
4533         GATE(CLK_PCLK_SMMU_DRC, "pclk_smmu_drc", "div_aclk_isp_c_200",
4534                         ENABLE_PCLK_ISP, 20, CLK_IGNORE_UNUSED, 0),
4535         GATE(CLK_PCLK_SMMU_ISP, "pclk_smmu_isp", "div_aclk_isp_c_200",
4536                         ENABLE_PCLK_ISP, 19, CLK_IGNORE_UNUSED, 0),
4537         GATE(CLK_PCLK_BTS_SCALERP, "pclk_bts_scalerp", "div_pclk_isp",
4538                         ENABLE_PCLK_ISP, 18, CLK_IGNORE_UNUSED, 0),
4539         GATE(CLK_PCLK_BTS_3DNR, "pclk_bts_3dnr", "div_pclk_isp",
4540                         ENABLE_PCLK_ISP, 17, CLK_IGNORE_UNUSED, 0),
4541         GATE(CLK_PCLK_BTS_DIS1, "pclk_bts_dis1", "div_pclk_isp",
4542                         ENABLE_PCLK_ISP, 16, CLK_IGNORE_UNUSED, 0),
4543         GATE(CLK_PCLK_BTS_DIS0, "pclk_bts_dis0", "div_pclk_isp",
4544                         ENABLE_PCLK_ISP, 15, CLK_IGNORE_UNUSED, 0),
4545         GATE(CLK_PCLK_BTS_SCALERC, "pclk_bts_scalerc", "div_pclk_isp",
4546                         ENABLE_PCLK_ISP, 14, CLK_IGNORE_UNUSED, 0),
4547         GATE(CLK_PCLK_BTS_DRC, "pclk_bts_drc", "div_pclk_isp",
4548                         ENABLE_PCLK_ISP, 13, CLK_IGNORE_UNUSED, 0),
4549         GATE(CLK_PCLK_BTS_ISP, "pclk_bts_isp", "div_pclk_isp",
4550                         ENABLE_PCLK_ISP, 12, CLK_IGNORE_UNUSED, 0),
4551         GATE(CLK_PCLK_ASYNCAXI_DIS1, "pclk_asyncaxi_dis1", "div_pclk_isp",
4552                         ENABLE_PCLK_ISP, 11, CLK_IGNORE_UNUSED, 0),
4553         GATE(CLK_PCLK_ASYNCAXI_DIS0, "pclk_asyncaxi_dis0", "div_pclk_isp",
4554                         ENABLE_PCLK_ISP, 10, CLK_IGNORE_UNUSED, 0),
4555         GATE(CLK_PCLK_PMU_ISP, "pclk_pmu_isp", "div_pclk_isp",
4556                         ENABLE_PCLK_ISP, 9, CLK_IGNORE_UNUSED, 0),
4557         GATE(CLK_PCLK_SYSREG_ISP, "pclk_sysreg_isp", "div_pclk_isp",
4558                         ENABLE_PCLK_ISP, 8, CLK_IGNORE_UNUSED, 0),
4559         GATE(CLK_PCLK_CMU_ISP_LOCAL, "pclk_cmu_isp_local",
4560                         "div_aclk_isp_c_200", ENABLE_PCLK_ISP,
4561                         7, CLK_IGNORE_UNUSED, 0),
4562         GATE(CLK_PCLK_SCALERP, "pclk_scalerp", "div_aclk_isp_d_200",
4563                         ENABLE_PCLK_ISP, 6, CLK_IGNORE_UNUSED, 0),
4564         GATE(CLK_PCLK_3DNR, "pclk_3dnr", "div_aclk_isp_d_200",
4565                         ENABLE_PCLK_ISP, 5, CLK_IGNORE_UNUSED, 0),
4566         GATE(CLK_PCLK_DIS_CORE, "pclk_dis_core", "div_pclk_isp_dis",
4567                         ENABLE_PCLK_ISP, 4, CLK_IGNORE_UNUSED, 0),
4568         GATE(CLK_PCLK_DIS, "pclk_dis", "div_aclk_isp_d_200",
4569                         ENABLE_PCLK_ISP, 3, CLK_IGNORE_UNUSED, 0),
4570         GATE(CLK_PCLK_SCALERC, "pclk_scalerc", "div_aclk_isp_c_200",
4571                         ENABLE_PCLK_ISP, 2, CLK_IGNORE_UNUSED, 0),
4572         GATE(CLK_PCLK_DRC, "pclk_drc", "div_aclk_isp_c_200",
4573                         ENABLE_PCLK_ISP, 1, CLK_IGNORE_UNUSED, 0),
4574         GATE(CLK_PCLK_ISP, "pclk_isp", "div_aclk_isp_c_200",
4575                         ENABLE_PCLK_ISP, 0, CLK_IGNORE_UNUSED, 0),
4576
4577         /* ENABLE_SCLK_ISP */
4578         GATE(CLK_SCLK_PIXELASYNCS_DIS, "sclk_pixelasyncs_dis",
4579                         "mout_aclk_isp_dis_400_user", ENABLE_SCLK_ISP,
4580                         5, CLK_IGNORE_UNUSED, 0),
4581         GATE(CLK_SCLK_PIXELASYNCM_DIS, "sclk_pixelasyncm_dis",
4582                         "mout_aclk_isp_dis_400_user", ENABLE_SCLK_ISP,
4583                         4, CLK_IGNORE_UNUSED, 0),
4584         GATE(CLK_SCLK_PIXELASYNCS_SCALERP, "sclk_pixelasyncs_scalerp",
4585                         "mout_aclk_isp_400_user", ENABLE_SCLK_ISP,
4586                         3, CLK_IGNORE_UNUSED, 0),
4587         GATE(CLK_SCLK_PIXELASYNCM_ISPD, "sclk_pixelasyncm_ispd",
4588                         "mout_aclk_isp_400_user", ENABLE_SCLK_ISP,
4589                         2, CLK_IGNORE_UNUSED, 0),
4590         GATE(CLK_SCLK_PIXELASYNCS_ISPC, "sclk_pixelasyncs_ispc",
4591                         "mout_aclk_isp_400_user", ENABLE_SCLK_ISP,
4592                         1, CLK_IGNORE_UNUSED, 0),
4593         GATE(CLK_SCLK_PIXELASYNCM_ISPC, "sclk_pixelasyncm_ispc",
4594                         "mout_aclk_isp_400_user", ENABLE_SCLK_ISP,
4595                         0, CLK_IGNORE_UNUSED, 0),
4596
4597         /* ENABLE_IP_ISP2 */
4598         GATE(CLK_BTS_3DNR, "clk_bts_3dnr", "",
4599                         ENABLE_IP_ISP2, 5, CLK_IGNORE_UNUSED, 0),
4600         GATE(CLK_BTS_DIS1, "clk_bts_dis1", "",
4601                         ENABLE_IP_ISP2, 4, CLK_IGNORE_UNUSED, 0),
4602         GATE(CLK_BTS_DIS0, "clk_bts_dis0", "",
4603                         ENABLE_IP_ISP2, 3, CLK_IGNORE_UNUSED, 0),
4604         GATE(CLK_BTS_SCALERC, "clk_bts_scalerc", "",
4605                         ENABLE_IP_ISP2, 2, CLK_IGNORE_UNUSED, 0),
4606         GATE(CLK_BTS_DRC, "clk_bts_drc", "",
4607                         ENABLE_IP_ISP2, 1, CLK_IGNORE_UNUSED, 0),
4608         GATE(CLK_BTS_ISP, "clk_bts_isp", "",
4609                         ENABLE_IP_ISP2, 0, CLK_IGNORE_UNUSED, 0),
4610 };
4611
4612 static struct samsung_cmu_info isp_cmu_info __initdata = {
4613         .mux_clks               = isp_mux_clks,
4614         .nr_mux_clks            = ARRAY_SIZE(isp_mux_clks),
4615         .div_clks               = isp_div_clks,
4616         .nr_div_clks            = ARRAY_SIZE(isp_div_clks),
4617         .gate_clks              = isp_gate_clks,
4618         .nr_gate_clks           = ARRAY_SIZE(isp_gate_clks),
4619         .nr_clk_ids             = ISP_NR_CLK,
4620         .clk_regs               = isp_clk_regs,
4621         .nr_clk_regs            = ARRAY_SIZE(isp_clk_regs),
4622 };
4623
4624 static void __init exynos5433_cmu_isp_init(struct device_node *np)
4625 {
4626         samsung_cmu_register_one(np, &isp_cmu_info);
4627 }
4628 CLK_OF_DECLARE(exynos5433_cmu_isp, "samsung,exynos5433-cmu-isp",
4629                 exynos5433_cmu_isp_init);
4630
4631 /*
4632  * Register offset definitions for CMU_CAM0
4633  */
4634 #define MUX_SEL_CAM00                   0x0200
4635 #define MUX_SEL_CAM01                   0x0204
4636 #define MUX_SEL_CAM02                   0x0208
4637 #define MUX_SEL_CAM03                   0x020c
4638 #define MUX_SEL_CAM04                   0x0210
4639 #define MUX_ENABLE_CAM00                0x0300
4640 #define MUX_ENABLE_CAM01                0x0304
4641 #define MUX_ENABLE_CAM02                0x0308
4642 #define MUX_ENABLE_CAM03                0x030c
4643 #define MUX_ENABLE_CAM04                0x0310
4644 #define MUX_STAT_CAM00                  0x0400
4645 #define MUX_STAT_CAM01                  0x0404
4646 #define MUX_STAT_CAM02                  0x0408
4647 #define MUX_STAT_CAM03                  0x040c
4648 #define MUX_STAT_CAM04                  0x0410
4649 #define MUX_IGNORE_CAM01                0x0504
4650 #define DIV_CAM00                       0x0600
4651 #define DIV_CAM01                       0x0604
4652 #define DIV_CAM02                       0x0608
4653 #define DIV_CAM03                       0x060c
4654 #define DIV_STAT_CAM00                  0x0700
4655 #define DIV_STAT_CAM01                  0x0704
4656 #define DIV_STAT_CAM02                  0x0708
4657 #define DIV_STAT_CAM03                  0x070c
4658 #define ENABLE_ACLK_CAM00               0X0800
4659 #define ENABLE_ACLK_CAM01               0X0804
4660 #define ENABLE_ACLK_CAM02               0X0808
4661 #define ENABLE_PCLK_CAM0                0X0900
4662 #define ENABLE_SCLK_CAM0                0X0a00
4663 #define ENABLE_IP_CAM00                 0X0b00
4664 #define ENABLE_IP_CAM01                 0X0b04
4665 #define ENABLE_IP_CAM02                 0X0b08
4666 #define ENABLE_IP_CAM03                 0X0b0C
4667
4668 static unsigned long cam0_clk_regs[] __initdata = {
4669         MUX_SEL_CAM00,
4670         MUX_SEL_CAM01,
4671         MUX_SEL_CAM02,
4672         MUX_SEL_CAM03,
4673         MUX_SEL_CAM04,
4674         MUX_ENABLE_CAM00,
4675         MUX_ENABLE_CAM01,
4676         MUX_ENABLE_CAM02,
4677         MUX_ENABLE_CAM03,
4678         MUX_ENABLE_CAM04,
4679         MUX_IGNORE_CAM01,
4680         DIV_CAM00,
4681         DIV_CAM01,
4682         DIV_CAM02,
4683         DIV_CAM03,
4684         ENABLE_ACLK_CAM00,
4685         ENABLE_ACLK_CAM01,
4686         ENABLE_ACLK_CAM02,
4687         ENABLE_PCLK_CAM0,
4688         ENABLE_SCLK_CAM0,
4689         ENABLE_IP_CAM00,
4690         ENABLE_IP_CAM01,
4691         ENABLE_IP_CAM02,
4692         ENABLE_IP_CAM03,
4693 };
4694 PNAME(mout_aclk_cam0_333_user_p)        = { "oscclk", "aclk_cam0_333", };
4695 PNAME(mout_aclk_cam0_400_user_p)        = { "oscclk", "aclk_cam0_400", };
4696 PNAME(mout_aclk_cam0_552_user_p)        = { "oscclk", "aclk_cam0_552", };
4697
4698 PNAME(mout_phyclk_rxbyteclkhs0_s4_user_p) = { "oscclk",
4699                                               "phyclk_rxbyteclkhs0_s4_phy", };
4700 PNAME(mout_phyclk_rxbyteclkhs0_s2a_user_p) = { "oscclk",
4701                                                "phyclk_rxbyteclkhs0_s2a_phy", };
4702
4703 PNAME(mout_aclk_lite_d_b_p)             = { "mout_aclk_lite_d_a",
4704                                             "mout_aclk_cam0_333_user", };
4705 PNAME(mout_aclk_lite_d_a_p)             = { "mout_aclk_cam0_552_user",
4706                                             "mout_aclk_cam0_400_user", };
4707 PNAME(mout_aclk_lite_b_b_p)             = { "mout_aclk_lite_b_a",
4708                                             "mout_aclk_cam0_333_user", };
4709 PNAME(mout_aclk_lite_b_a_p)             = { "mout_aclk_cam0_552_user",
4710                                             "mout_aclk_cam0_400_user", };
4711 PNAME(mout_aclk_lite_a_b_p)             = { "mout_aclk_lite_a_a",
4712                                             "mout_aclk_cam0_333_user", };
4713 PNAME(mout_aclk_lite_a_a_p)             = { "mout_aclk_cam0_552_user",
4714                                             "mout_aclk_cam0_400_user", };
4715 PNAME(mout_aclk_cam0_400_p)             = { "mout_aclk_cam0_400_user",
4716                                             "mout_aclk_cam0_333_user", };
4717
4718 PNAME(mout_aclk_csis1_b_p)              = { "mout_aclk_csis1_a",
4719                                             "mout_aclk_cam0_333_user" };
4720 PNAME(mout_aclk_csis1_a_p)              = { "mout_aclk_cam0_552_user",
4721                                             "mout_aclk_cam0_400_user", };
4722 PNAME(mout_aclk_csis0_b_p)              = { "mout_aclk_csis0_a",
4723                                             "mout_aclk_cam0_333_user", };
4724 PNAME(mout_aclk_csis0_a_p)              = { "mout_aclk_cam0_552_user",
4725                                             "mout_aclk-cam0_400_user", };
4726 PNAME(mout_aclk_3aa1_b_p)               = { "mout_aclk_3aa1_a",
4727                                             "mout_aclk_cam0_333_user", };
4728 PNAME(mout_aclk_3aa1_a_p)               = { "mout_aclk_cam0_552_user",
4729                                             "mout_aclk_cam0_400_user", };
4730 PNAME(mout_aclk_3aa0_b_p)               = { "mout_aclk_3aa0_a",
4731                                             "mout_aclk_cam0_333_user", };
4732 PNAME(mout_aclk_3aa0_a_p)               = { "mout_aclk_cam0_552_user",
4733                                             "mout_aclk_cam0_400_user", };
4734
4735 PNAME(mout_sclk_lite_freecnt_c_p)       = { "mout_sclk_lite_freecnt_b",
4736                                             "div_pclk_lite_d", };
4737 PNAME(mout_sclk_lite_freecnt_b_p)       = { "mout_sclk_lite_freecnt_a",
4738                                             "div_pclk_pixelasync_lite_c", };
4739 PNAME(mout_sclk_lite_freecnt_a_p)       = { "div_pclk_lite_a",
4740                                             "div_pclk_lite_b", };
4741 PNAME(mout_sclk_pixelasync_lite_c_b_p)  = { "mout_sclk_pixelasync_lite_c_a",
4742                                             "mout_aclk_cam0_333_user", };
4743 PNAME(mout_sclk_pixelasync_lite_c_a_p)  = { "mout_aclk_cam0_552_user",
4744                                             "mout_aclk_cam0_400_user", };
4745 PNAME(mout_sclk_pixelasync_lite_c_init_b_p) = {
4746                                         "mout_sclk_pixelasync_lite_c_init_a",
4747                                         "mout_aclk_cam0_400_user", };
4748 PNAME(mout_sclk_pixelasync_lite_c_init_a_p) = {
4749                                         "mout_aclk_cam0_552_user",
4750                                         "mout_aclk_cam0_400_user", };
4751
4752 static struct samsung_fixed_rate_clock cam0_fixed_clks[] __initdata = {
4753         FRATE(CLK_PHYCLK_RXBYTEECLKHS0_S4_PHY, "phyclk_rxbyteclkhs0_s4_phy",
4754                         NULL, CLK_IS_ROOT, 188000000),
4755         FRATE(CLK_PHYCLK_RXBYTEECLKHS0_S2A_PHY, "phyclk_rxbyteclkhs0_s2a_phy",
4756                         NULL, CLK_IS_ROOT, 188000000),
4757 };
4758
4759 static struct samsung_mux_clock cam0_mux_clks[] __initdata = {
4760         /* MUX_SEL_CAM00 */
4761         MUX(CLK_MOUT_ACLK_CAM0_333_USER, "mout_aclk_cam0_333_user",
4762                         mout_aclk_cam0_333_user_p, MUX_SEL_CAM00, 8, 1),
4763         MUX(CLK_MOUT_ACLK_CAM0_400_USER, "mout_aclk_cam0_400_user",
4764                         mout_aclk_cam0_400_user_p, MUX_SEL_CAM00, 4, 1),
4765         MUX(CLK_MOUT_ACLK_CAM0_552_USER, "mout_aclk_cam0_552_user",
4766                         mout_aclk_cam0_552_user_p, MUX_SEL_CAM00, 0, 1),
4767
4768         /* MUX_SEL_CAM01 */
4769         MUX(CLK_MOUT_PHYCLK_RXBYTECLKHS0_S4_USER,
4770                         "mout_phyclk_rxbyteclkhs0_s4_user",
4771                         mout_phyclk_rxbyteclkhs0_s4_user_p,
4772                         MUX_SEL_CAM01, 4, 1),
4773         MUX(CLK_MOUT_PHYCLK_RXBYTECLKHS0_S2A_USER,
4774                         "mout_phyclk_rxbyteclkhs0_s2a_user",
4775                         mout_phyclk_rxbyteclkhs0_s2a_user_p,
4776                         MUX_SEL_CAM01, 0, 1),
4777
4778         /* MUX_SEL_CAM02 */
4779         MUX(CLK_MOUT_ACLK_LITE_D_B, "mout_aclk_lite_d_b", mout_aclk_lite_d_b_p,
4780                         MUX_SEL_CAM02, 24, 1),
4781         MUX(CLK_MOUT_ACLK_LITE_D_A, "mout_aclk_lite_d_a", mout_aclk_lite_d_a_p,
4782                         MUX_SEL_CAM02, 20, 1),
4783         MUX(CLK_MOUT_ACLK_LITE_B_B, "mout_aclk_lite_b_b", mout_aclk_lite_b_b_p,
4784                         MUX_SEL_CAM02, 16, 1),
4785         MUX(CLK_MOUT_ACLK_LITE_B_A, "mout_aclk_lite_b_a", mout_aclk_lite_b_a_p,
4786                         MUX_SEL_CAM02, 12, 1),
4787         MUX(CLK_MOUT_ACLK_LITE_A_B, "mout_aclk_lite_a_b", mout_aclk_lite_a_b_p,
4788                         MUX_SEL_CAM02, 8, 1),
4789         MUX(CLK_MOUT_ACLK_LITE_A_A, "mout_aclk_lite_a_a", mout_aclk_lite_a_a_p,
4790                         MUX_SEL_CAM02, 4, 1),
4791         MUX(CLK_MOUT_ACLK_CAM0_400, "mout_aclk_cam0_400", mout_aclk_cam0_400_p,
4792                         MUX_SEL_CAM02, 0, 1),
4793
4794         /* MUX_SEL_CAM03 */
4795         MUX(CLK_MOUT_ACLK_CSIS1_B, "mout_aclk_csis1_b", mout_aclk_csis1_b_p,
4796                         MUX_SEL_CAM03, 28, 1),
4797         MUX(CLK_MOUT_ACLK_CSIS1_A, "mout_aclk_csis1_a", mout_aclk_csis1_a_p,
4798                         MUX_SEL_CAM03, 24, 1),
4799         MUX(CLK_MOUT_ACLK_CSIS0_B, "mout_aclk_csis0_b", mout_aclk_csis0_b_p,
4800                         MUX_SEL_CAM03, 20, 1),
4801         MUX(CLK_MOUT_ACLK_CSIS0_A, "mout_aclk_csis0_a", mout_aclk_csis0_a_p,
4802                         MUX_SEL_CAM03, 16, 1),
4803         MUX(CLK_MOUT_ACLK_3AA1_B, "mout_aclk_3aa1_b", mout_aclk_3aa1_b_p,
4804                         MUX_SEL_CAM03, 12, 1),
4805         MUX(CLK_MOUT_ACLK_3AA1_A, "mout_aclk_3aa1_a", mout_aclk_3aa1_a_p,
4806                         MUX_SEL_CAM03, 8, 1),
4807         MUX(CLK_MOUT_ACLK_3AA0_B, "mout_aclk_3aa0_b", mout_aclk_3aa0_b_p,
4808                         MUX_SEL_CAM03, 4, 1),
4809         MUX(CLK_MOUT_ACLK_3AA0_A, "mout_aclk_3aa0_a", mout_aclk_3aa0_a_p,
4810                         MUX_SEL_CAM03, 0, 1),
4811
4812         /* MUX_SEL_CAM04 */
4813         MUX(CLK_MOUT_SCLK_LITE_FREECNT_C, "mout_sclk_lite_freecnt_c",
4814                         mout_sclk_lite_freecnt_c_p, MUX_SEL_CAM04, 24, 1),
4815         MUX(CLK_MOUT_SCLK_LITE_FREECNT_B, "mout_sclk_lite_freecnt_b",
4816                         mout_sclk_lite_freecnt_b_p, MUX_SEL_CAM04, 20, 1),
4817         MUX(CLK_MOUT_SCLK_LITE_FREECNT_A, "mout_sclk_lite_freecnt_a",
4818                         mout_sclk_lite_freecnt_a_p, MUX_SEL_CAM04, 16, 1),
4819         MUX(CLK_MOUT_SCLK_PIXELASYNC_LITE_C_B, "mout_sclk_pixelasync_lite_c_b",
4820                         mout_sclk_pixelasync_lite_c_b_p, MUX_SEL_CAM04, 12, 1),
4821         MUX(CLK_MOUT_SCLK_PIXELASYNC_LITE_C_A, "mout_sclk_pixelasync_lite_c_a",
4822                         mout_sclk_pixelasync_lite_c_a_p, MUX_SEL_CAM04, 8, 1),
4823         MUX(CLK_MOUT_SCLK_PIXELASYNC_LITE_C_INIT_B,
4824                         "mout_sclk_pixelasync_lite_c_init_b",
4825                         mout_sclk_pixelasync_lite_c_init_b_p,
4826                         MUX_SEL_CAM04, 4, 1),
4827         MUX(CLK_MOUT_SCLK_PIXELASYNC_LITE_C_INIT_A,
4828                         "mout_sclk_pixelasync_lite_c_init_a",
4829                         mout_sclk_pixelasync_lite_c_init_a_p,
4830                         MUX_SEL_CAM04, 0, 1),
4831 };
4832
4833 static struct samsung_div_clock cam0_div_clks[] __initdata = {
4834         /* DIV_CAM00 */
4835         DIV(CLK_DIV_PCLK_CAM0_50, "div_pclk_cam0_50", "div_aclk_cam0_200",
4836                         DIV_CAM00, 8, 2),
4837         DIV(CLK_DIV_ACLK_CAM0_200, "div_aclk_cam0_200", "mout_aclk_cam0_400",
4838                         DIV_CAM00, 4, 3),
4839         DIV(CLK_DIV_ACLK_CAM0_BUS_400, "div_aclk_cam0_bus_400",
4840                         "mout_aclk_cam0_400", DIV_CAM00, 0, 3),
4841
4842         /* DIV_CAM01 */
4843         DIV(CLK_DIV_PCLK_LITE_D, "div_pclk_lite_d", "div_aclk_lite_d",
4844                         DIV_CAM01, 20, 2),
4845         DIV(CLK_DIV_ACLK_LITE_D, "div_aclk_lite_d", "mout_aclk_lite_d_b",
4846                         DIV_CAM01, 16, 3),
4847         DIV(CLK_DIV_PCLK_LITE_B, "div_pclk_lite_b", "div_aclk_lite_b",
4848                         DIV_CAM01, 12, 2),
4849         DIV(CLK_DIV_ACLK_LITE_B, "div_aclk_lite_b", "mout_aclk_lite_b_b",
4850                         DIV_CAM01, 8, 3),
4851         DIV(CLK_DIV_PCLK_LITE_A, "div_pclk_lite_a", "div_aclk_lite_a",
4852                         DIV_CAM01, 4, 2),
4853         DIV(CLK_DIV_ACLK_LITE_A, "div_aclk_lite_a", "mout_aclk_lite_a_b",
4854                         DIV_CAM01, 0, 3),
4855
4856         /* DIV_CAM02 */
4857         DIV(CLK_DIV_ACLK_CSIS1, "div_aclk_csis1", "mout_aclk_csis1_b",
4858                         DIV_CAM02, 20, 3),
4859         DIV(CLK_DIV_ACLK_CSIS0, "div_aclk_csis0", "mout_aclk_csis0_b",
4860                         DIV_CAM02, 16, 3),
4861         DIV(CLK_DIV_PCLK_3AA1, "div_pclk_3aa1", "div_aclk_3aa1",
4862                         DIV_CAM02, 12, 2),
4863         DIV(CLK_DIV_ACLK_3AA1, "div_aclk_3aa1", "mout_aclk_3aa1_b",
4864                         DIV_CAM02, 8, 3),
4865         DIV(CLK_DIV_PCLK_3AA0, "div_pclk_3aa0", "div_aclk_3aa0",
4866                         DIV_CAM02, 4, 2),
4867         DIV(CLK_DIV_ACLK_3AA0, "div_aclk_3aa0", "mout_aclk_3aa0_b",
4868                         DIV_CAM02, 0, 3),
4869
4870         /* DIV_CAM03 */
4871         DIV(CLK_DIV_SCLK_PIXELASYNC_LITE_C, "div_sclk_pixelasync_lite_c",
4872                         "mout_sclk_pixelasync_lite_c_b", DIV_CAM03, 8, 3),
4873         DIV(CLK_DIV_PCLK_PIXELASYNC_LITE_C, "div_pclk_pixelasync_lite_c",
4874                         "div_sclk_pixelasync_lite_c_init", DIV_CAM03, 4, 2),
4875         DIV(CLK_DIV_SCLK_PIXELASYNC_LITE_C_INIT,
4876                         "div_sclk_pixelasync_lite_c_init",
4877                         "mout_sclk_pixelasync_lite_c_init_b", DIV_CAM03, 0, 3),
4878 };
4879
4880 static struct samsung_gate_clock cam0_gate_clks[] __initdata = {
4881         /* ENABLE_ACLK_CAM00 */
4882         GATE(CLK_ACLK_CSIS1, "aclk_csis1", "div_aclk_csis1", ENABLE_ACLK_CAM00,
4883                         6, CLK_IGNORE_UNUSED, 0),
4884         GATE(CLK_ACLK_CSIS0, "aclk_csis0", "div_aclk_csis0", ENABLE_ACLK_CAM00,
4885                         5, CLK_IGNORE_UNUSED, 0),
4886         GATE(CLK_ACLK_3AA1, "aclk_3aa1", "div_aclk_3aa1", ENABLE_ACLK_CAM00,
4887                         4, CLK_IGNORE_UNUSED, 0),
4888         GATE(CLK_ACLK_3AA0, "aclk_3aa0", "div_aclk_3aa0", ENABLE_ACLK_CAM00,
4889                         3, CLK_IGNORE_UNUSED, 0),
4890         GATE(CLK_ACLK_LITE_D, "aclk_lite_d", "div_aclk_lite_d",
4891                         ENABLE_ACLK_CAM00, 2, CLK_IGNORE_UNUSED, 0),
4892         GATE(CLK_ACLK_LITE_B, "aclk_lite_b", "div_aclk_lite_b",
4893                         ENABLE_ACLK_CAM00, 1, CLK_IGNORE_UNUSED, 0),
4894         GATE(CLK_ACLK_LITE_A, "aclk_lite_a", "div_aclk_lite_a",
4895                         ENABLE_ACLK_CAM00, 0, CLK_IGNORE_UNUSED, 0),
4896
4897         /* ENABLE_ACLK_CAM01 */
4898         GATE(CLK_ACLK_AHBSYNCDN, "aclk_ahbsyncdn", "div_aclk_cam0_200",
4899                         ENABLE_ACLK_CAM01, 31, CLK_IGNORE_UNUSED, 0),
4900         GATE(CLK_ACLK_AXIUS_LITE_D, "aclk_axius_lite_d", "div_aclk_cam0_bus_400",
4901                         ENABLE_ACLK_CAM01, 30, CLK_IGNORE_UNUSED, 0),
4902         GATE(CLK_ACLK_AXIUS_LITE_B, "aclk_axius_lite_b", "div_aclk_cam0_bus_400",
4903                         ENABLE_ACLK_CAM01, 29, CLK_IGNORE_UNUSED, 0),
4904         GATE(CLK_ACLK_AXIUS_LITE_A, "aclk_axius_lite_a", "div_aclk_cam0_bus_400",
4905                         ENABLE_ACLK_CAM01, 28, CLK_IGNORE_UNUSED, 0),
4906         GATE(CLK_ACLK_ASYNCAPBM_3AA1, "aclk_asyncapbm_3aa1", "div_pclk_3aa1",
4907                         ENABLE_ACLK_CAM01, 27, CLK_IGNORE_UNUSED, 0),
4908         GATE(CLK_ACLK_ASYNCAPBS_3AA1, "aclk_asyncapbs_3aa1", "div_aclk_3aa1",
4909                         ENABLE_ACLK_CAM01, 26, CLK_IGNORE_UNUSED, 0),
4910         GATE(CLK_ACLK_ASYNCAPBM_3AA0, "aclk_asyncapbm_3aa0", "div_pclk_3aa0",
4911                         ENABLE_ACLK_CAM01, 25, CLK_IGNORE_UNUSED, 0),
4912         GATE(CLK_ACLK_ASYNCAPBS_3AA0, "aclk_asyncapbs_3aa0", "div_aclk_3aa0",
4913                         ENABLE_ACLK_CAM01, 24, CLK_IGNORE_UNUSED, 0),
4914         GATE(CLK_ACLK_ASYNCAPBM_LITE_D, "aclk_asyncapbm_lite_d",
4915                         "div_pclk_lite_d", ENABLE_ACLK_CAM01,
4916                         23, CLK_IGNORE_UNUSED, 0),
4917         GATE(CLK_ACLK_ASYNCAPBS_LITE_D, "aclk_asyncapbs_lite_d",
4918                         "div_aclk_cam0_200", ENABLE_ACLK_CAM01,
4919                         22, CLK_IGNORE_UNUSED, 0),
4920         GATE(CLK_ACLK_ASYNCAPBM_LITE_B, "aclk_asyncapbm_lite_b",
4921                         "div_pclk_lite_b", ENABLE_ACLK_CAM01,
4922                         21, CLK_IGNORE_UNUSED, 0),
4923         GATE(CLK_ACLK_ASYNCAPBS_LITE_B, "aclk_asyncapbs_lite_b",
4924                         "div_aclk_cam0_200", ENABLE_ACLK_CAM01,
4925                         20, CLK_IGNORE_UNUSED, 0),
4926         GATE(CLK_ACLK_ASYNCAPBM_LITE_A, "aclk_asyncapbm_lite_a",
4927                         "div_pclk_lite_a", ENABLE_ACLK_CAM01,
4928                         19, CLK_IGNORE_UNUSED, 0),
4929         GATE(CLK_ACLK_ASYNCAPBS_LITE_A, "aclk_asyncapbs_lite_a",
4930                         "div_aclk_cam0_200", ENABLE_ACLK_CAM01,
4931                         18, CLK_IGNORE_UNUSED, 0),
4932         GATE(CLK_ACLK_ASYNCAXIM_ISP0P, "aclk_asyncaxim_isp0p",
4933                         "div_aclk_cam0_200", ENABLE_ACLK_CAM01,
4934                         17, CLK_IGNORE_UNUSED, 0),
4935         GATE(CLK_ACLK_ASYNCAXIM_3AA1, "aclk_asyncaxim_3aa1",
4936                         "div_aclk_cam0_bus_400", ENABLE_ACLK_CAM01,
4937                         16, CLK_IGNORE_UNUSED, 0),
4938         GATE(CLK_ACLK_ASYNCAXIS_3AA1, "aclk_asyncaxis_3aa1",
4939                         "div_aclk_3aa1", ENABLE_ACLK_CAM01,
4940                         15, CLK_IGNORE_UNUSED, 0),
4941         GATE(CLK_ACLK_ASYNCAXIM_3AA0, "aclk_asyncaxim_3aa0",
4942                         "div_aclk_cam0_bus_400", ENABLE_ACLK_CAM01,
4943                         14, CLK_IGNORE_UNUSED, 0),
4944         GATE(CLK_ACLK_ASYNCAXIS_3AA0, "aclk_asyncaxis_3aa0",
4945                         "div_aclk_3aa0", ENABLE_ACLK_CAM01,
4946                         13, CLK_IGNORE_UNUSED, 0),
4947         GATE(CLK_ACLK_ASYNCAXIM_LITE_D, "aclk_asyncaxim_lite_d",
4948                         "div_aclk_cam0_bus_400", ENABLE_ACLK_CAM01,
4949                         12, CLK_IGNORE_UNUSED, 0),
4950         GATE(CLK_ACLK_ASYNCAXIS_LITE_D, "aclk_asyncaxis_lite_d",
4951                         "div_aclk_lite_d", ENABLE_ACLK_CAM01,
4952                         11, CLK_IGNORE_UNUSED, 0),
4953         GATE(CLK_ACLK_ASYNCAXIM_LITE_B, "aclk_asyncaxim_lite_b",
4954                         "div_aclk_cam0_bus_400", ENABLE_ACLK_CAM01,
4955                         10, CLK_IGNORE_UNUSED, 0),
4956         GATE(CLK_ACLK_ASYNCAXIS_LITE_B, "aclk_asyncaxis_lite_b",
4957                         "div_aclk_lite_b", ENABLE_ACLK_CAM01,
4958                         9, CLK_IGNORE_UNUSED, 0),
4959         GATE(CLK_ACLK_ASYNCAXIM_LITE_A, "aclk_asyncaxim_lite_a",
4960                         "div_aclk_cam0_bus_400", ENABLE_ACLK_CAM01,
4961                         8, CLK_IGNORE_UNUSED, 0),
4962         GATE(CLK_ACLK_ASYNCAXIS_LITE_A, "aclk_asyncaxis_lite_a",
4963                         "div_aclk_lite_a", ENABLE_ACLK_CAM01,
4964                         7, CLK_IGNORE_UNUSED, 0),
4965         GATE(CLK_ACLK_AHB2APB_ISPSFRP, "aclk_ahb2apb_ispsfrp",
4966                         "div_pclk_cam0_50", ENABLE_ACLK_CAM01,
4967                         6, CLK_IGNORE_UNUSED, 0),
4968         GATE(CLK_ACLK_AXI2APB_ISP0P, "aclk_axi2apb_isp0p", "div_aclk_cam0_200",
4969                         ENABLE_ACLK_CAM01, 5, CLK_IGNORE_UNUSED, 0),
4970         GATE(CLK_ACLK_AXI2AHB_ISP0P, "aclk_axi2ahb_isp0p", "div_aclk_cam0_200",
4971                         ENABLE_ACLK_CAM01, 4, CLK_IGNORE_UNUSED, 0),
4972         GATE(CLK_ACLK_XIU_IS0X, "aclk_xiu_is0x", "div_aclk_cam0_200",
4973                         ENABLE_ACLK_CAM01, 3, CLK_IGNORE_UNUSED, 0),
4974         GATE(CLK_ACLK_XIU_ISP0EX, "aclk_xiu_isp0ex", "div_aclk_cam0_bus_400",
4975                         ENABLE_ACLK_CAM01, 2, CLK_IGNORE_UNUSED, 0),
4976         GATE(CLK_ACLK_CAM0NP_276, "aclk_cam0np_276", "div_aclk_cam0_200",
4977                         ENABLE_ACLK_CAM01, 1, CLK_IGNORE_UNUSED, 0),
4978         GATE(CLK_ACLK_CAM0ND_400, "aclk_cam0nd_400", "div_aclk_cam0_bus_400",
4979                         ENABLE_ACLK_CAM01, 0, CLK_IGNORE_UNUSED, 0),
4980
4981         /* ENABLE_ACLK_CAM02 */
4982         GATE(CLK_ACLK_SMMU_3AA1, "aclk_smmu_3aa1", "div_aclk_cam0_bus_400",
4983                         ENABLE_ACLK_CAM02, 9, CLK_IGNORE_UNUSED, 0),
4984         GATE(CLK_ACLK_SMMU_3AA0, "aclk_smmu_3aa0", "div_aclk_cam0_bus_400",
4985                         ENABLE_ACLK_CAM02, 8, CLK_IGNORE_UNUSED, 0),
4986         GATE(CLK_ACLK_SMMU_LITE_D, "aclk_smmu_lite_d", "div_aclk_cam0_bus_400",
4987                         ENABLE_ACLK_CAM02, 7, CLK_IGNORE_UNUSED, 0),
4988         GATE(CLK_ACLK_SMMU_LITE_B, "aclk_smmu_lite_b", "div_aclk_cam0_bus_400",
4989                         ENABLE_ACLK_CAM02, 6, CLK_IGNORE_UNUSED, 0),
4990         GATE(CLK_ACLK_SMMU_LITE_A, "aclk_smmu_lite_a", "div_aclk_cam0_bus_400",
4991                         ENABLE_ACLK_CAM02, 5, CLK_IGNORE_UNUSED, 0),
4992         GATE(CLK_ACLK_BTS_3AA1, "aclk_bts_3aa1", "div_aclk_cam0_bus_400",
4993                         ENABLE_ACLK_CAM02, 4, CLK_IGNORE_UNUSED, 0),
4994         GATE(CLK_ACLK_BTS_3AA0, "aclk_bts_3aa0", "div_aclk_cam0_bus_400",
4995                         ENABLE_ACLK_CAM02, 3, CLK_IGNORE_UNUSED, 0),
4996         GATE(CLK_ACLK_BTS_LITE_D, "aclk_bts_lite_d", "div_aclk_cam0_bus_400",
4997                         ENABLE_ACLK_CAM02, 2, CLK_IGNORE_UNUSED, 0),
4998         GATE(CLK_ACLK_BTS_LITE_B, "aclk_bts_lite_b", "div_aclk_cam0_bus_400",
4999                         ENABLE_ACLK_CAM02, 1, CLK_IGNORE_UNUSED, 0),
5000         GATE(CLK_ACLK_BTS_LITE_A, "aclk_bts_lite_a", "div_aclk_cam0_bus_400",
5001                         ENABLE_ACLK_CAM02, 0, CLK_IGNORE_UNUSED, 0),
5002
5003         /* ENABLE_PCLK_CAM0 */
5004         GATE(CLK_PCLK_SMMU_3AA1, "pclk_smmu_3aa1", "div_aclk_cam0_200",
5005                         ENABLE_PCLK_CAM0, 25, CLK_IGNORE_UNUSED, 0),
5006         GATE(CLK_PCLK_SMMU_3AA0, "pclk_smmu_3aa0", "div_aclk_cam0_200",
5007                         ENABLE_PCLK_CAM0, 24, CLK_IGNORE_UNUSED, 0),
5008         GATE(CLK_PCLK_SMMU_LITE_D, "pclk_smmu_lite_d", "div_aclk_cam0_200",
5009                         ENABLE_PCLK_CAM0, 23, CLK_IGNORE_UNUSED, 0),
5010         GATE(CLK_PCLK_SMMU_LITE_B, "pclk_smmu_lite_b", "div_aclk_cam0_200",
5011                         ENABLE_PCLK_CAM0, 22, CLK_IGNORE_UNUSED, 0),
5012         GATE(CLK_PCLK_SMMU_LITE_A, "pclk_smmu_lite_a", "div_aclk_cam0_200",
5013                         ENABLE_PCLK_CAM0, 21, CLK_IGNORE_UNUSED, 0),
5014         GATE(CLK_PCLK_BTS_3AA1, "pclk_bts_3aa1", "div_pclk_cam0_50",
5015                         ENABLE_PCLK_CAM0, 20, CLK_IGNORE_UNUSED, 0),
5016         GATE(CLK_PCLK_BTS_3AA0, "pclk_bts_3aa0", "div_pclk_cam0_50",
5017                         ENABLE_PCLK_CAM0, 19, CLK_IGNORE_UNUSED, 0),
5018         GATE(CLK_PCLK_BTS_LITE_D, "pclk_bts_lite_d", "div_pclk_cam0_50",
5019                         ENABLE_PCLK_CAM0, 18, CLK_IGNORE_UNUSED, 0),
5020         GATE(CLK_PCLK_BTS_LITE_B, "pclk_bts_lite_b", "div_pclk_cam0_50",
5021                         ENABLE_PCLK_CAM0, 17, CLK_IGNORE_UNUSED, 0),
5022         GATE(CLK_PCLK_BTS_LITE_A, "pclk_bts_lite_a", "div_pclk_cam0_50",
5023                         ENABLE_PCLK_CAM0, 16, CLK_IGNORE_UNUSED, 0),
5024         GATE(CLK_PCLK_ASYNCAXI_CAM1, "pclk_asyncaxi_cam1", "div_pclk_cam0_50",
5025                         ENABLE_PCLK_CAM0, 15, CLK_IGNORE_UNUSED, 0),
5026         GATE(CLK_PCLK_ASYNCAXI_3AA1, "pclk_asyncaxi_3aa1", "div_pclk_cam0_50",
5027                         ENABLE_PCLK_CAM0, 14, CLK_IGNORE_UNUSED, 0),
5028         GATE(CLK_PCLK_ASYNCAXI_3AA0, "pclk_asyncaxi_3aa0", "div_pclk_cam0_50",
5029                         ENABLE_PCLK_CAM0, 13, CLK_IGNORE_UNUSED, 0),
5030         GATE(CLK_PCLK_ASYNCAXI_LITE_D, "pclk_asyncaxi_lite_d",
5031                         "div_pclk_cam0_50", ENABLE_PCLK_CAM0,
5032                         12, CLK_IGNORE_UNUSED, 0),
5033         GATE(CLK_PCLK_ASYNCAXI_LITE_B, "pclk_asyncaxi_lite_b",
5034                         "div_pclk_cam0_50", ENABLE_PCLK_CAM0,
5035                         11, CLK_IGNORE_UNUSED, 0),
5036         GATE(CLK_PCLK_ASYNCAXI_LITE_A, "pclk_asyncaxi_lite_a",
5037                         "div_pclk_cam0_50", ENABLE_PCLK_CAM0,
5038                         10, CLK_IGNORE_UNUSED, 0),
5039         GATE(CLK_PCLK_PMU_CAM0, "pclk_pmu_cam0", "div_pclk_cam0_50",
5040                         ENABLE_PCLK_CAM0, 9, CLK_IGNORE_UNUSED, 0),
5041         GATE(CLK_PCLK_SYSREG_CAM0, "pclk_sysreg_cam0", "div_pclk_cam0_50",
5042                         ENABLE_PCLK_CAM0, 8, CLK_IGNORE_UNUSED, 0),
5043         GATE(CLK_PCLK_CMU_CAM0_LOCAL, "pclk_cmu_cam0_local",
5044                         "div_aclk_cam0_200", ENABLE_PCLK_CAM0,
5045                         7, CLK_IGNORE_UNUSED, 0),
5046         GATE(CLK_PCLK_CSIS1, "pclk_csis1", "div_aclk_cam0_200",
5047                         ENABLE_PCLK_CAM0, 6, CLK_IGNORE_UNUSED, 0),
5048         GATE(CLK_PCLK_CSIS0, "pclk_csis0", "div_aclk_cam0_200",
5049                         ENABLE_PCLK_CAM0, 5, CLK_IGNORE_UNUSED, 0),
5050         GATE(CLK_PCLK_3AA1, "pclk_3aa1", "div_pclk_3aa1",
5051                         ENABLE_PCLK_CAM0, 4, CLK_IGNORE_UNUSED, 0),
5052         GATE(CLK_PCLK_3AA0, "pclk_3aa0", "div_pclk_3aa0",
5053                         ENABLE_PCLK_CAM0, 3, CLK_IGNORE_UNUSED, 0),
5054         GATE(CLK_PCLK_LITE_D, "pclk_lite_d", "div_pclk_lite_d",
5055                         ENABLE_PCLK_CAM0, 2, CLK_IGNORE_UNUSED, 0),
5056         GATE(CLK_PCLK_LITE_B, "pclk_lite_b", "div_pclk_lite_b",
5057                         ENABLE_PCLK_CAM0, 1, CLK_IGNORE_UNUSED, 0),
5058         GATE(CLK_PCLK_LITE_A, "pclk_lite_a", "div_pclk_lite_a",
5059                         ENABLE_PCLK_CAM0, 0, CLK_IGNORE_UNUSED, 0),
5060
5061         /* ENABLE_SCLK_CAM0 */
5062         GATE(CLK_PHYCLK_RXBYTECLKHS0_S4, "phyclk_rxbyteclkhs0_s4",
5063                         "mout_phyclk_rxbyteclkhs0_s4_user",
5064                         ENABLE_SCLK_CAM0, 8, CLK_IGNORE_UNUSED, 0),
5065         GATE(CLK_PHYCLK_RXBYTECLKHS0_S2A, "phyclk_rxbyteclkhs0_s2a",
5066                         "mout_phyclk_rxbyteclkhs0_s2a_user",
5067                         ENABLE_SCLK_CAM0, 7, CLK_IGNORE_UNUSED, 0),
5068         GATE(CLK_SCLK_LITE_FREECNT, "sclk_lite_freecnt",
5069                         "mout_sclk_lite_freecnt_c", ENABLE_SCLK_CAM0, 6,
5070                         CLK_IGNORE_UNUSED, 0),
5071         GATE(CLK_SCLK_PIXELASYNCM_3AA1, "sclk_pixelasycm_3aa1",
5072                         "div_aclk_3aa1", ENABLE_SCLK_CAM0, 5,
5073                         CLK_IGNORE_UNUSED, 0),
5074         GATE(CLK_SCLK_PIXELASYNCM_3AA0, "sclk_pixelasycm_3aa0",
5075                         "div_aclk_3aa0", ENABLE_SCLK_CAM0, 4,
5076                         CLK_IGNORE_UNUSED, 0),
5077         GATE(CLK_SCLK_PIXELASYNCS_3AA0, "sclk_pixelasycs_3aa0",
5078                         "div_aclk_3aa0", ENABLE_SCLK_CAM0, 3,
5079                         CLK_IGNORE_UNUSED, 0),
5080         GATE(CLK_SCLK_PIXELASYNCM_LITE_C, "sclk_pixelasyncm_lite_c",
5081                         "div_sclk_pixelasync_lite_c",
5082                         ENABLE_SCLK_CAM0, 2, CLK_IGNORE_UNUSED, 0),
5083         GATE(CLK_SCLK_PIXELASYNCM_LITE_C_INIT, "sclk_pixelasyncm_lite_c_init",
5084                         "div_sclk_pixelasync_lite_c_init",
5085                         ENABLE_SCLK_CAM0, 1, CLK_IGNORE_UNUSED, 0),
5086         GATE(CLK_SCLK_PIXELASYNCS_LITE_C_INIT, "sclk_pixelasyncs_lite_c_init",
5087                         "div_sclk_pixelasync_lite_c",
5088                         ENABLE_SCLK_CAM0, 0, CLK_IGNORE_UNUSED, 0),
5089
5090         /* ENABLE_IP_CAM03 */
5091         GATE(CLK_LITE_FREECNT, "clk_lite_freecnt", "",
5092                         ENABLE_IP_CAM03, 4, CLK_IGNORE_UNUSED, 0),
5093         GATE(CLK_PIXELASYNC_3AA1, "clk_pixelasync_3aa1", "",
5094                         ENABLE_IP_CAM03, 3, CLK_IGNORE_UNUSED, 0),
5095         GATE(CLK_PIXELASYNC_3AA0, "clk_pixelasync_3aa0", "",
5096                         ENABLE_IP_CAM03, 2, CLK_IGNORE_UNUSED, 0),
5097         GATE(CLK_PIXELASYNC_LITE_C, "clk_pixelasync_lite_c", "",
5098                         ENABLE_IP_CAM03, 1, CLK_IGNORE_UNUSED, 0),
5099         GATE(CLK_PIXELASYNC_LITE_C_INIT, "clk_pixelasync_lite_c_init", "",
5100                         ENABLE_IP_CAM03, 0, CLK_IGNORE_UNUSED, 0),
5101         /* ENABLE_IP_CAM02 */
5102         GATE(CLK_BTS_3AA1, "clk_bts_3aa1", "",
5103                         ENABLE_IP_CAM02, 4, CLK_IGNORE_UNUSED, 0),
5104         GATE(CLK_BTS_3AA0, "clk_bts_3aa0", "",
5105                         ENABLE_IP_CAM02, 3, CLK_IGNORE_UNUSED, 0),
5106
5107         /* ENABLE_IP_CAM01 */
5108         GATE(CLK_AXIUS_LITE_D, "clk_axius_lite_d", "",
5109                         ENABLE_IP_CAM01, 21, CLK_IGNORE_UNUSED, 0),
5110         GATE(CLK_AXIUS_LITE_B, "clk_axius_lite_b", "",
5111                         ENABLE_IP_CAM01, 20, CLK_IGNORE_UNUSED, 0),
5112         GATE(CLK_AXIUS_LITE_A, "clk_axius_lite_a", "",
5113                         ENABLE_IP_CAM01, 19, CLK_IGNORE_UNUSED, 0),
5114
5115         GATE(CLK_ASYNCAXI_3AA1, "clk_asyncaxi_3aa1", "",
5116                         ENABLE_IP_CAM01, 11, CLK_IGNORE_UNUSED, 0),
5117         GATE(CLK_ASYNCAXI_3AA0, "clk_asyncaxi_3aa0", "",
5118                         ENABLE_IP_CAM01, 10, CLK_IGNORE_UNUSED, 0),
5119         GATE(CLK_ASYNCAXI_LITE_D, "clk_asyncaxi_lite_d", "",
5120                         ENABLE_IP_CAM01, 9, CLK_IGNORE_UNUSED, 0),
5121         GATE(CLK_ASYNCAXI_LITE_B, "clk_asyncaxi_lite_b", "",
5122                         ENABLE_IP_CAM01, 8, CLK_IGNORE_UNUSED, 0),
5123         GATE(CLK_ASYNCAXI_LITE_A, "clk_asyncaxi_lite_a", "",
5124                         ENABLE_IP_CAM01, 7, CLK_IGNORE_UNUSED, 0),
5125
5126         /* ENABLE_IP_CAM00 */
5127         GATE(CLK_PMU_CAM0, "clk_pmu_cam0", "",
5128                         ENABLE_IP_CAM00, 9, CLK_IGNORE_UNUSED, 0),
5129         GATE(CLK_SYSREG_CAM0, "clk_sysreg_cam0", "",
5130                         ENABLE_IP_CAM00, 8, CLK_IGNORE_UNUSED, 0),
5131         GATE(CLK_CMU_CAM0_LOCAL, "clk_cmu_cam0_local", "",
5132                         ENABLE_IP_CAM00, 7, CLK_IGNORE_UNUSED, 0),
5133         GATE(CLK_CSIS1, "clk_csis1", "",
5134                         ENABLE_IP_CAM00, 6, CLK_IGNORE_UNUSED, 0),
5135         GATE(CLK_CSIS0, "clk_csis0", "",
5136                         ENABLE_IP_CAM00, 5, CLK_IGNORE_UNUSED, 0),
5137         GATE(CLK_3AA1, "clk_3aa1", "",
5138                         ENABLE_IP_CAM00, 4, CLK_IGNORE_UNUSED, 0),
5139         GATE(CLK_3AA0, "clk_3aa0", "",
5140                         ENABLE_IP_CAM00, 3, CLK_IGNORE_UNUSED, 0),
5141         GATE(CLK_LITE_D, "clk_lite_d", "",
5142                         ENABLE_IP_CAM00, 2, CLK_IGNORE_UNUSED, 0),
5143         GATE(CLK_LITE_B, "clk_lite_b", "",
5144                         ENABLE_IP_CAM00, 1, CLK_IGNORE_UNUSED, 0),
5145         GATE(CLK_LITE_A, "clk_lite_a", "",
5146                         ENABLE_IP_CAM00, 0, CLK_IGNORE_UNUSED, 0),
5147 };
5148
5149 static struct samsung_cmu_info cam0_cmu_info __initdata = {
5150         .mux_clks               = cam0_mux_clks,
5151         .nr_mux_clks            = ARRAY_SIZE(cam0_mux_clks),
5152         .div_clks               = cam0_div_clks,
5153         .nr_div_clks            = ARRAY_SIZE(cam0_div_clks),
5154         .gate_clks              = cam0_gate_clks,
5155         .nr_gate_clks           = ARRAY_SIZE(cam0_gate_clks),
5156         .fixed_clks             = cam0_fixed_clks,
5157         .nr_fixed_clks          = ARRAY_SIZE(cam0_fixed_clks),
5158         .nr_clk_ids             = CAM0_NR_CLK,
5159         .clk_regs               = cam0_clk_regs,
5160         .nr_clk_regs            = ARRAY_SIZE(cam0_clk_regs),
5161 };
5162
5163 static void __init exynos5433_cmu_cam0_init(struct device_node *np)
5164 {
5165         samsung_cmu_register_one(np, &cam0_cmu_info);
5166 }
5167 CLK_OF_DECLARE(exynos5433_cmu_cam0, "samsung,exynos5433-cmu-cam0",
5168                 exynos5433_cmu_cam0_init);
5169
5170 /*
5171  * Register offset definitions for CMU_CAM1
5172  */
5173 #define MUX_SEL_CAM10                   0x0200
5174 #define MUX_SEL_CAM11                   0x0204
5175 #define MUX_SEL_CAM12                   0x0208
5176 #define MUX_ENABLE_CAM10                0x0300
5177 #define MUX_ENABLE_CAM11                0x0304
5178 #define MUX_ENABLE_CAM12                0x0308
5179 #define MUX_STAT_CAM10                  0x0400
5180 #define MUX_STAT_CAM11                  0x0404
5181 #define MUX_STAT_CAM12                  0x0408
5182 #define MUX_IGNORE_CAM11                0x0504
5183 #define DIV_CAM10                       0x0600
5184 #define DIV_CAM11                       0x0604
5185 #define DIV_STAT_CAM10                  0x0700
5186 #define DIV_STAT_CAM11                  0x0704
5187 #define ENABLE_ACLK_CAM10               0X0800
5188 #define ENABLE_ACLK_CAM11               0X0804
5189 #define ENABLE_ACLK_CAM12               0X0808
5190 #define ENABLE_PCLK_CAM1                0X0900
5191 #define ENABLE_SCLK_CAM1                0X0a00
5192 #define ENABLE_IP_CAM10                 0X0b00
5193 #define ENABLE_IP_CAM11                 0X0b04
5194 #define ENABLE_IP_CAM12                 0X0b08
5195
5196 static unsigned long cam1_clk_regs[] __initdata = {
5197         MUX_SEL_CAM10,
5198         MUX_SEL_CAM11,
5199         MUX_SEL_CAM12,
5200         MUX_ENABLE_CAM10,
5201         MUX_ENABLE_CAM11,
5202         MUX_ENABLE_CAM12,
5203         MUX_IGNORE_CAM11,
5204         DIV_CAM10,
5205         DIV_CAM11,
5206         ENABLE_ACLK_CAM10,
5207         ENABLE_ACLK_CAM11,
5208         ENABLE_ACLK_CAM12,
5209         ENABLE_PCLK_CAM1,
5210         ENABLE_SCLK_CAM1,
5211         ENABLE_IP_CAM10,
5212         ENABLE_IP_CAM11,
5213         ENABLE_IP_CAM12,
5214 };
5215
5216 PNAME(mout_sclk_isp_uart_user_p)        = { "oscclk", "sclk_isp_uart_cam1", };
5217 PNAME(mout_sclk_isp_spi1_user_p)        = { "oscclk", "sclk_isp_spi1_cam1", };
5218 PNAME(mout_sclk_isp_spi0_user_p)        = { "oscclk", "sclk_isp_spi0_cam1", };
5219
5220 PNAME(mout_aclk_cam1_333_user_p)        = { "oscclk", "aclk_cam1_333", };
5221 PNAME(mout_aclk_cam1_400_user_p)        = { "oscclk", "aclk_cam1_400", };
5222 PNAME(mout_aclk_cam1_552_user_p)        = { "oscclk", "aclk_cam1_552", };
5223
5224 PNAME(mout_phyclk_rxbyteclkhs0_s2b_user_p) = { "oscclk",
5225                                                "phyclk_rxbyteclkhs0_s2b_phy", };
5226
5227 PNAME(mout_aclk_csis2_b_p)              = { "mout_aclk_csis2_a",
5228                                             "mout_aclk_cam1_333_user", };
5229 PNAME(mout_aclk_csis2_a_p)              = { "mout_aclk_cam1_552_user",
5230                                             "mout_aclk_cam1_400_user", };
5231
5232 PNAME(mout_aclk_fd_b_p)                 = { "mout_aclk_fd_a",
5233                                             "mout_aclk_cam1_333_user", };
5234 PNAME(mout_aclk_fd_a_p)                 = { "mout_aclk_cam1_552_user",
5235                                             "mout_aclk_cam1_400_user", };
5236
5237 PNAME(mout_aclk_lite_c_b_p)             = { "mout_aclk_lite_c_a",
5238                                             "mout_aclk_cam1_333_user", };
5239 PNAME(mout_aclk_lite_c_a_p)             = { "mout_aclk_cam1_552_user",
5240                                             "mout_aclk_cam1_400_user", };
5241
5242 static struct samsung_fixed_rate_clock cam1_fixed_clks[] __initdata = {
5243         FRATE(CLK_PHYCLK_RXBYTEECLKHS0_S2B, "phyclk_rxbyteclkhs0_s2b_phy", NULL,
5244                         CLK_IS_ROOT, 188000000),
5245 };
5246
5247 static struct samsung_mux_clock cam1_mux_clks[] __initdata = {
5248         /* MUX_SEL_CAM10 */
5249         MUX(CLK_MOUT_SCLK_ISP_UART_USER, "mout_sclk_isp_uart_user",
5250                         mout_sclk_isp_uart_user_p, MUX_SEL_CAM10, 20, 1),
5251         MUX(CLK_MOUT_SCLK_ISP_SPI1_USER, "mout_sclk_isp_spi1_user",
5252                         mout_sclk_isp_spi1_user_p, MUX_SEL_CAM10, 16, 1),
5253         MUX(CLK_MOUT_SCLK_ISP_SPI0_USER, "mout_sclk_isp_spi0_user",
5254                         mout_sclk_isp_spi0_user_p, MUX_SEL_CAM10, 12, 1),
5255         MUX(CLK_MOUT_ACLK_CAM1_333_USER, "mout_aclk_cam1_333_user",
5256                         mout_aclk_cam1_333_user_p, MUX_SEL_CAM10, 8, 1),
5257         MUX(CLK_MOUT_ACLK_CAM1_400_USER, "mout_aclk_cam1_400_user",
5258                         mout_aclk_cam1_400_user_p, MUX_SEL_CAM10, 4, 1),
5259         MUX(CLK_MOUT_ACLK_CAM1_552_USER, "mout_aclk_cam1_552_user",
5260                         mout_aclk_cam1_552_user_p, MUX_SEL_CAM10, 0, 1),
5261
5262         /* MUX_SEL_CAM11 */
5263         MUX(CLK_MOUT_PHYCLK_RXBYTECLKHS0_S2B_USER,
5264                         "mout_phyclk_rxbyteclkhs0_s2b_user",
5265                         mout_phyclk_rxbyteclkhs0_s2b_user_p,
5266                         MUX_SEL_CAM11, 0, 1),
5267
5268         /* MUX_SEL_CAM12 */
5269         MUX(CLK_MOUT_ACLK_CSIS2_B, "mout_aclk_csis2_b", mout_aclk_csis2_b_p,
5270                         MUX_SEL_CAM12, 20, 1),
5271         MUX(CLK_MOUT_ACLK_CSIS2_A, "mout_aclk_csis2_a", mout_aclk_csis2_a_p,
5272                         MUX_SEL_CAM12, 16, 1),
5273         MUX(CLK_MOUT_ACLK_FD_B, "mout_aclk_fd_b", mout_aclk_fd_b_p,
5274                         MUX_SEL_CAM12, 12, 1),
5275         MUX(CLK_MOUT_ACLK_FD_A, "mout_aclk_fd_a", mout_aclk_fd_a_p,
5276                         MUX_SEL_CAM12, 8, 1),
5277         MUX(CLK_MOUT_ACLK_LITE_C_B, "mout_aclk_lite_c_b", mout_aclk_lite_c_b_p,
5278                         MUX_SEL_CAM12, 4, 1),
5279         MUX(CLK_MOUT_ACLK_LITE_C_A, "mout_aclk_lite_c_a", mout_aclk_lite_c_a_p,
5280                         MUX_SEL_CAM12, 0, 1),
5281 };
5282
5283 static struct samsung_div_clock cam1_div_clks[] __initdata = {
5284         /* DIV_CAM10 */
5285         DIV(CLK_DIV_SCLK_ISP_MPWM, "div_sclk_isp_mpwm",
5286                         "div_pclk_cam1_83", DIV_CAM10, 16, 2),
5287         DIV(CLK_DIV_PCLK_CAM1_83, "div_pclk_cam1_83",
5288                         "mout_aclk_cam1_333_user", DIV_CAM10, 12, 2),
5289         DIV(CLK_DIV_PCLK_CAM1_166, "div_pclk_cam1_166",
5290                         "mout_aclk_cam1_333_user", DIV_CAM10, 8, 2),
5291         DIV(CLK_DIV_PCLK_DBG_CAM1, "div_pclk_dbg_cam1",
5292                         "mout_aclk_cam1_552_user", DIV_CAM10, 4, 3),
5293         DIV(CLK_DIV_ATCLK_CAM1, "div_atclk_cam1", "mout_aclk_cam1_552_user",
5294                         DIV_CAM10, 0, 3),
5295
5296         /* DIV_CAM11 */
5297         DIV(CLK_DIV_ACLK_CSIS2, "div_aclk_csis2", "mout_aclk_csis2_b",
5298                         DIV_CAM11, 16, 3),
5299         DIV(CLK_DIV_PCLK_FD, "div_pclk_fd", "div_aclk_fd", DIV_CAM11, 12, 2),
5300         DIV(CLK_DIV_ACLK_FD, "div_aclk_fd", "mout_aclk_fd_b", DIV_CAM11, 8, 3),
5301         DIV(CLK_DIV_PCLK_LITE_C, "div_pclk_lite_c", "div_aclk_lite_c",
5302                         DIV_CAM11, 4, 2),
5303         DIV(CLK_DIV_ACLK_LITE_C, "div_aclk_lite_c", "mout_aclk_lite_c_b",
5304                         DIV_CAM11, 0, 3),
5305 };
5306
5307 static struct samsung_gate_clock cam1_gate_clks[] __initdata = {
5308         /* ENABLE_ACLK_CAM10 */
5309         GATE(CLK_ACLK_ISP_GIC, "aclk_isp_gic", "mout_aclk_cam1_333_user",
5310                         ENABLE_ACLK_CAM10, 4, CLK_IGNORE_UNUSED, 0),
5311         GATE(CLK_ACLK_FD, "aclk_fd", "div_aclk_fd",
5312                         ENABLE_ACLK_CAM10, 3, CLK_IGNORE_UNUSED, 0),
5313         GATE(CLK_ACLK_LITE_C, "aclk_lite_c", "div_aclk_lite_c",
5314                         ENABLE_ACLK_CAM10, 1, CLK_IGNORE_UNUSED, 0),
5315         GATE(CLK_ACLK_CSIS2, "aclk_csis2", "div_aclk_csis2",
5316                         ENABLE_ACLK_CAM10, 0, CLK_IGNORE_UNUSED, 0),
5317
5318         /* ENABLE_ACLK_CAM11 */
5319         GATE(CLK_ACLK_ASYNCAPBM_FD, "aclk_asyncapbm_fd", "div_pclk_fd",
5320                         ENABLE_ACLK_CAM11, 29, CLK_IGNORE_UNUSED, 0),
5321         GATE(CLK_ACLK_ASYNCAPBS_FD, "aclk_asyncapbs_fd", "div_pclk_cam1_166",
5322                         ENABLE_ACLK_CAM11, 28, CLK_IGNORE_UNUSED, 0),
5323         GATE(CLK_ACLK_ASYNCAPBM_LITE_C, "aclk_asyncapbm_lite_c",
5324                         "div_pclk_lite_c", ENABLE_ACLK_CAM11,
5325                         27, CLK_IGNORE_UNUSED, 0),
5326         GATE(CLK_ACLK_ASYNCAPBS_LITE_C, "aclk_asyncapbs_lite_c",
5327                         "div_pclk_cam1_166", ENABLE_ACLK_CAM11,
5328                         26, CLK_IGNORE_UNUSED, 0),
5329         GATE(CLK_ACLK_ASYNCAHBS_SFRISP2H2, "aclk_asyncahbs_sfrisp2h2",
5330                         "div_pclk_cam1_83", ENABLE_ACLK_CAM11,
5331                         25, CLK_IGNORE_UNUSED, 0),
5332         GATE(CLK_ACLK_ASYNCAHBS_SFRISP2H1, "aclk_asyncahbs_sfrisp2h1",
5333                         "div_pclk_cam1_83", ENABLE_ACLK_CAM11,
5334                         24, CLK_IGNORE_UNUSED, 0),
5335         GATE(CLK_ACLK_ASYNCAXIM_CA5, "aclk_asyncaxim_ca5",
5336                         "mout_aclk_cam1_333_user", ENABLE_ACLK_CAM11,
5337                         23, CLK_IGNORE_UNUSED, 0),
5338         GATE(CLK_ACLK_ASYNCAXIS_CA5, "aclk_asyncaxis_ca5",
5339                         "mout_aclk_cam1_552_user", ENABLE_ACLK_CAM11,
5340                         22, CLK_IGNORE_UNUSED, 0),
5341         GATE(CLK_ACLK_ASYNCAXIS_ISPX2, "aclk_asyncaxis_ispx2",
5342                         "mout_aclk_cam1_333_user", ENABLE_ACLK_CAM11,
5343                         21, CLK_IGNORE_UNUSED, 0),
5344         GATE(CLK_ACLK_ASYNCAXIS_ISPX1, "aclk_asyncaxis_ispx1",
5345                         "mout_aclk_cam1_333_user", ENABLE_ACLK_CAM11,
5346                         20, CLK_IGNORE_UNUSED, 0),
5347         GATE(CLK_ACLK_ASYNCAXIS_ISPX0, "aclk_asyncaxis_ispx0",
5348                         "mout_aclk_cam1_333_user", ENABLE_ACLK_CAM11,
5349                         19, CLK_IGNORE_UNUSED, 0),
5350         GATE(CLK_ACLK_ASYNCAXIM_ISPEX, "aclk_asyncaxim_ispex",
5351                         "mout_aclk_cam1_400_user", ENABLE_ACLK_CAM11,
5352                         18, CLK_IGNORE_UNUSED, 0),
5353         GATE(CLK_ACLK_ASYNCAXIM_ISP3P, "aclk_asyncaxim_isp3p",
5354                         "mout_aclk_cam1_400_user", ENABLE_ACLK_CAM11,
5355                         17, CLK_IGNORE_UNUSED, 0),
5356         GATE(CLK_ACLK_ASYNCAXIS_ISP3P, "aclk_asyncaxis_isp3p",
5357                         "mout_aclk_cam1_333_user", ENABLE_ACLK_CAM11,
5358                         16, CLK_IGNORE_UNUSED, 0),
5359         GATE(CLK_ACLK_ASYNCAXIM_FD, "aclk_asyncaxim_fd",
5360                         "mout_aclk_cam1_400_user", ENABLE_ACLK_CAM11,
5361                         15, CLK_IGNORE_UNUSED, 0),
5362         GATE(CLK_ACLK_ASYNCAXIS_FD, "aclk_asyncaxis_fd", "div_aclk_fd",
5363                         ENABLE_ACLK_CAM11, 14, CLK_IGNORE_UNUSED, 0),
5364         GATE(CLK_ACLK_ASYNCAXIM_LITE_C, "aclk_asyncaxim_lite_c",
5365                         "mout_aclk_cam1_400_user", ENABLE_ACLK_CAM11,
5366                         13, CLK_IGNORE_UNUSED, 0),
5367         GATE(CLK_ACLK_ASYNCAXIS_LITE_C, "aclk_asyncaxis_lite_c",
5368                         "div_aclk_lite_c", ENABLE_ACLK_CAM11,
5369                         12, CLK_IGNORE_UNUSED, 0),
5370         GATE(CLK_ACLK_AHB2APB_ISP5P, "aclk_ahb2apb_isp5p", "div_pclk_cam1_83",
5371                         ENABLE_ACLK_CAM11, 11, CLK_IGNORE_UNUSED, 0),
5372         GATE(CLK_ACLK_AHB2APB_ISP3P, "aclk_ahb2apb_isp3p", "div_pclk_cam1_83",
5373                         ENABLE_ACLK_CAM11, 10, CLK_IGNORE_UNUSED, 0),
5374         GATE(CLK_ACLK_AXI2APB_ISP3P, "aclk_axi2apb_isp3p",
5375                         "mout_aclk_cam1_333_user", ENABLE_ACLK_CAM11,
5376                         9, CLK_IGNORE_UNUSED, 0),
5377         GATE(CLK_ACLK_AHB_SFRISP2H, "aclk_ahb_sfrisp2h", "div_pclk_cam1_83",
5378                         ENABLE_ACLK_CAM11, 8, CLK_IGNORE_UNUSED, 0),
5379         GATE(CLK_ACLK_AXI_ISP_HX_R, "aclk_axi_isp_hx_r", "div_pclk_cam1_166",
5380                         ENABLE_ACLK_CAM11, 7, CLK_IGNORE_UNUSED, 0),
5381         GATE(CLK_ACLK_AXI_ISP_CX_R, "aclk_axi_isp_cx_r", "div_pclk_cam1_166",
5382                         ENABLE_ACLK_CAM11, 6, CLK_IGNORE_UNUSED, 0),
5383         GATE(CLK_ACLK_AXI_ISP_HX, "aclk_axi_isp_hx", "mout_aclk_cam1_333_user",
5384                         ENABLE_ACLK_CAM11, 5, CLK_IGNORE_UNUSED, 0),
5385         GATE(CLK_ACLK_AXI_ISP_CX, "aclk_axi_isp_cx", "mout_aclk_cam1_333_user",
5386                         ENABLE_ACLK_CAM11, 4, CLK_IGNORE_UNUSED, 0),
5387         GATE(CLK_ACLK_XIU_ISPX, "aclk_xiu_ispx", "mout_aclk_cam1_333_user",
5388                         ENABLE_ACLK_CAM11, 3, CLK_IGNORE_UNUSED, 0),
5389         GATE(CLK_ACLK_XIU_ISPEX, "aclk_xiu_ispex", "mout_aclk_cam1_400_user",
5390                         ENABLE_ACLK_CAM11, 2, CLK_IGNORE_UNUSED, 0),
5391         GATE(CLK_ACLK_CAM1NP_333, "aclk_cam1np_333", "mout_aclk_cam1_333_user",
5392                         ENABLE_ACLK_CAM11, 1, CLK_IGNORE_UNUSED, 0),
5393         GATE(CLK_ACLK_CAM1ND_400, "aclk_cam1nd_400", "mout_aclk_cam1_400_user",
5394                         ENABLE_ACLK_CAM11, 0, CLK_IGNORE_UNUSED, 0),
5395
5396         /* ENABLE_ACLK_CAM12 */
5397         GATE(CLK_ACLK_SMMU_ISPCPU, "aclk_smmu_ispcpu",
5398                         "mout_aclk_cam1_400_user", ENABLE_ACLK_CAM12,
5399                         10, CLK_IGNORE_UNUSED, 0),
5400         GATE(CLK_ACLK_SMMU_FD, "aclk_smmu_fd", "mout_aclk_cam1_400_user",
5401                         ENABLE_ACLK_CAM12, 9, CLK_IGNORE_UNUSED, 0),
5402         GATE(CLK_ACLK_SMMU_LITE_C, "aclk_smmu_lite_c",
5403                         "mout_aclk_cam1_400_user", ENABLE_ACLK_CAM12,
5404                         8, CLK_IGNORE_UNUSED, 0),
5405         GATE(CLK_ACLK_BTS_ISP3P, "aclk_bts_isp3p", "mout_aclk_cam1_400_user",
5406                         ENABLE_ACLK_CAM12, 7, CLK_IGNORE_UNUSED, 0),
5407         GATE(CLK_ACLK_BTS_FD, "aclk_bts_fd", "mout_aclk_cam1_400_user",
5408                         ENABLE_ACLK_CAM12, 6, CLK_IGNORE_UNUSED, 0),
5409         GATE(CLK_ACLK_BTS_LITE_C, "aclk_bts_lite_c", "mout_aclk_cam1_400_user",
5410                         ENABLE_ACLK_CAM12, 5, CLK_IGNORE_UNUSED, 0),
5411         GATE(CLK_ACLK_AHBDN_SFRISP2H, "aclk_ahbdn_sfrisp2h",
5412                         "mout_aclk_cam1_333_user", ENABLE_ACLK_CAM12,
5413                         4, CLK_IGNORE_UNUSED, 0),
5414         GATE(CLK_ACLK_AHBDN_ISP5P, "aclk_aclk-shbdn_isp5p",
5415                         "mout_aclk_cam1_333_user", ENABLE_ACLK_CAM12,
5416                         3, CLK_IGNORE_UNUSED, 0),
5417         GATE(CLK_ACLK_AXIUS_ISP3P, "aclk_axius_isp3p",
5418                         "mout_aclk_cam1_400_user", ENABLE_ACLK_CAM12,
5419                         2, CLK_IGNORE_UNUSED, 0),
5420         GATE(CLK_ACLK_AXIUS_FD, "aclk_axius_fd", "mout_aclk_cam1_400_user",
5421                         ENABLE_ACLK_CAM12, 1, CLK_IGNORE_UNUSED, 0),
5422         GATE(CLK_ACLK_AXIUS_LITE_C, "aclk_axius_lite_c",
5423                         "mout_aclk_cam1_400_user", ENABLE_ACLK_CAM12,
5424                         0, CLK_IGNORE_UNUSED, 0),
5425
5426         /* ENABLE_PCLK_CAM1 */
5427         GATE(CLK_PCLK_SMMU_ISPCPU, "pclk_smmu_ispcpu", "div_pclk_cam1_166",
5428                         ENABLE_PCLK_CAM1, 27, CLK_IGNORE_UNUSED, 0),
5429         GATE(CLK_PCLK_SMMU_FD, "pclk_smmu_fd", "div_pclk_cam1_166",
5430                         ENABLE_PCLK_CAM1, 26, CLK_IGNORE_UNUSED, 0),
5431         GATE(CLK_PCLK_SMMU_LITE_C, "pclk_smmu_lite_c", "div_pclk_cam1_166",
5432                         ENABLE_PCLK_CAM1, 25, CLK_IGNORE_UNUSED, 0),
5433         GATE(CLK_PCLK_BTS_ISP3P, "pclk_bts_isp3p", "div_pclk_cam1_83",
5434                         ENABLE_PCLK_CAM1, 24, CLK_IGNORE_UNUSED, 0),
5435         GATE(CLK_PCLK_BTS_FD, "pclk_bts_fd", "div_pclk_cam1_83",
5436                         ENABLE_PCLK_CAM1, 23, CLK_IGNORE_UNUSED, 0),
5437         GATE(CLK_PCLK_BTS_LITE_C, "pclk_bts_lite_c", "div_pclk_cam1_83",
5438                         ENABLE_PCLK_CAM1, 22, CLK_IGNORE_UNUSED, 0),
5439         GATE(CLK_PCLK_ASYNCAXIM_CA5, "pclk_asyncaxim_ca5", "div_pclk_cam1_166",
5440                         ENABLE_PCLK_CAM1, 21, CLK_IGNORE_UNUSED, 0),
5441         GATE(CLK_PCLK_ASYNCAXIM_ISPEX, "pclk_asyncaxim_ispex",
5442                         "div_pclk_cam1_83", ENABLE_PCLK_CAM1,
5443                         20, CLK_IGNORE_UNUSED, 0),
5444         GATE(CLK_PCLK_ASYNCAXIM_ISP3P, "pclk_asyncaxim_isp3p",
5445                         "div_pclk_cam1_83", ENABLE_PCLK_CAM1,
5446                         19, CLK_IGNORE_UNUSED, 0),
5447         GATE(CLK_PCLK_ASYNCAXIM_FD, "pclk_asyncaxim_fd", "div_pclk_cam1_83",
5448                         ENABLE_PCLK_CAM1, 18, CLK_IGNORE_UNUSED, 0),
5449         GATE(CLK_PCLK_ASYNCAXIM_LITE_C, "pclk_asyncaxim_lite_c",
5450                         "div_pclk_cam1_83", ENABLE_PCLK_CAM1,
5451                         17, CLK_IGNORE_UNUSED, 0),
5452         GATE(CLK_PCLK_PMU_CAM1, "pclk_pmu_cam1", "div_pclk_cam1_83",
5453                         ENABLE_PCLK_CAM1, 16, CLK_IGNORE_UNUSED, 0),
5454         GATE(CLK_PCLK_SYSREG_CAM1, "pclk_sysreg_cam1", "div_pclk_cam1_83",
5455                         ENABLE_PCLK_CAM1, 15, CLK_IGNORE_UNUSED, 0),
5456         GATE(CLK_PCLK_CMU_CAM1_LOCAL, "pclk_cmu_cam1_local",
5457                         "div_pclk_cam1_166", ENABLE_PCLK_CAM1,
5458                         14, CLK_IGNORE_UNUSED, 0),
5459         GATE(CLK_PCLK_ISP_MCTADC, "pclk_isp_mctadc", "div_pclk_cam1_83",
5460                         ENABLE_PCLK_CAM1, 13, CLK_IGNORE_UNUSED, 0),
5461         GATE(CLK_PCLK_ISP_WDT, "pclk_isp_wdt", "div_pclk_cam1_83",
5462                         ENABLE_PCLK_CAM1, 12, CLK_IGNORE_UNUSED, 0),
5463         GATE(CLK_PCLK_ISP_PWM, "pclk_isp_pwm", "div_pclk_cam1_83",
5464                         ENABLE_PCLK_CAM1, 11, CLK_IGNORE_UNUSED, 0),
5465         GATE(CLK_PCLK_ISP_UART, "pclk_isp_uart", "div_pclk_cam1_83",
5466                         ENABLE_PCLK_CAM1, 10, CLK_IGNORE_UNUSED, 0),
5467         GATE(CLK_PCLK_ISP_MCUCTL, "pclk_isp_mcuctl", "div_pclk_cam1_83",
5468                         ENABLE_PCLK_CAM1, 9, CLK_IGNORE_UNUSED, 0),
5469         GATE(CLK_PCLK_ISP_SPI1, "pclk_isp_spi1", "div_pclk_cam1_83",
5470                         ENABLE_PCLK_CAM1, 8, CLK_IGNORE_UNUSED, 0),
5471         GATE(CLK_PCLK_ISP_SPI0, "pclk_isp_spi0", "div_pclk_cam1_83",
5472                         ENABLE_PCLK_CAM1, 7, CLK_IGNORE_UNUSED, 0),
5473         GATE(CLK_PCLK_ISP_I2C2, "pclk_isp_i2c2", "div_pclk_cam1_83",
5474                         ENABLE_PCLK_CAM1, 6, CLK_IGNORE_UNUSED, 0),
5475         GATE(CLK_PCLK_ISP_I2C1, "pclk_isp_i2c1", "div_pclk_cam1_83",
5476                         ENABLE_PCLK_CAM1, 5, CLK_IGNORE_UNUSED, 0),
5477         GATE(CLK_PCLK_ISP_I2C0, "pclk_isp_i2c0", "div_pclk_cam1_83",
5478                         ENABLE_PCLK_CAM1, 4, CLK_IGNORE_UNUSED, 0),
5479         GATE(CLK_PCLK_ISP_MPWM, "pclk_isp_mpwm", "div_pclk_cam1_83",
5480                         ENABLE_PCLK_CAM1, 3, CLK_IGNORE_UNUSED, 0),
5481         GATE(CLK_PCLK_FD, "pclk_fd", "div_pclk_fd",
5482                         ENABLE_PCLK_CAM1, 3, CLK_IGNORE_UNUSED, 0),
5483         GATE(CLK_PCLK_LITE_C, "pclk_lite_c", "div_pclk_lite_c",
5484                         ENABLE_PCLK_CAM1, 1, CLK_IGNORE_UNUSED, 0),
5485         GATE(CLK_PCLK_CSIS2, "pclk_csis2", "div_pclk_cam1_166",
5486                         ENABLE_PCLK_CAM1, 0, CLK_IGNORE_UNUSED, 0),
5487
5488         /* ENABLE_SCLK_CAM1 */
5489         GATE(CLK_SCLK_ISP_I2C2, "sclk_isp_i2c2", "oscclk", ENABLE_SCLK_CAM1,
5490                         15, CLK_IGNORE_UNUSED, 0),
5491         GATE(CLK_SCLK_ISP_I2C1, "sclk_isp_i2c1", "oscclk", ENABLE_SCLK_CAM1,
5492                         14, CLK_IGNORE_UNUSED, 0),
5493         GATE(CLK_SCLK_ISP_I2C0, "sclk_isp_i2c0", "oscclk", ENABLE_SCLK_CAM1,
5494                         13, CLK_IGNORE_UNUSED, 0),
5495         GATE(CLK_SCLK_ISP_PWM, "sclk_isp_pwm", "oscclk", ENABLE_SCLK_CAM1,
5496                         12, CLK_IGNORE_UNUSED, 0),
5497         GATE(CLK_PHYCLK_RXBYTECLKHS0_S2B, "phyclk_rxbyteclkhs0_s2b",
5498                         "mout_phyclk_rxbyteclkhs0_s2b_user",
5499                         ENABLE_SCLK_CAM1, 11, CLK_IGNORE_UNUSED, 0),
5500         GATE(CLK_SCLK_LITE_C_FREECNT, "sclk_lite_c_freecnt", "div_pclk_lite_c",
5501                         ENABLE_SCLK_CAM1, 10, CLK_IGNORE_UNUSED, 0),
5502         GATE(CLK_SCLK_PIXELASYNCM_FD, "sclk_pixelasyncm_fd", "div_aclk_fd",
5503                         ENABLE_SCLK_CAM1, 9, CLK_IGNORE_UNUSED, 0),
5504         GATE(CLK_SCLK_ISP_MCTADC, "sclk_isp_mctadc", "sclk_isp_mctadc_cam1",
5505                         ENABLE_SCLK_CAM1, 7, CLK_IGNORE_UNUSED, 0),
5506         GATE(CLK_SCLK_ISP_UART, "sclk_isp_uart", "mout_sclk_isp_uart_user",
5507                         ENABLE_SCLK_CAM1, 6, CLK_IGNORE_UNUSED, 0),
5508         GATE(CLK_SCLK_ISP_SPI1, "sclk_isp_spi1", "mout_sclk_isp_spi1_user",
5509                         ENABLE_SCLK_CAM1, 5, CLK_IGNORE_UNUSED, 0),
5510         GATE(CLK_SCLK_ISP_SPI0, "sclk_isp_spi0", "mout_sclk_isp_spi0_user",
5511                         ENABLE_SCLK_CAM1, 4, CLK_IGNORE_UNUSED, 0),
5512         GATE(CLK_SCLK_ISP_MPWM, "sclk_isp_mpwm", "div_sclk_isp_mpwm",
5513                         ENABLE_SCLK_CAM1, 3, CLK_IGNORE_UNUSED, 0),
5514         GATE(CLK_PCLK_DBG_ISP, "sclk_dbg_isp", "div_pclk_dbg_cam1",
5515                         ENABLE_SCLK_CAM1, 2, CLK_IGNORE_UNUSED, 0),
5516         GATE(CLK_ATCLK_ISP, "atclk_isp", "div_atclk_cam1",
5517                         ENABLE_SCLK_CAM1, 1, CLK_IGNORE_UNUSED, 0),
5518         GATE(CLK_SCLK_ISP_CA5, "sclk_isp_ca5", "mout_aclk_cam1_552_user",
5519                         ENABLE_SCLK_CAM1, 0, CLK_IGNORE_UNUSED, 0),
5520
5521         /* IP_CAM12 */
5522         GATE(CLK_BTS_FD, "clk_bts_fd", "",
5523                         ENABLE_IP_CAM12, 6, CLK_IGNORE_UNUSED, 0),
5524
5525         /* IP_CAM10 */
5526         GATE(CLK_RXBYTECLKHS0_S2B, "clk_rxbyteclkhs0_s2b", "",
5527                         ENABLE_IP_CAM10, 23, CLK_IGNORE_UNUSED, 0),
5528         GATE(CLK_LITE_C_FREECNT, "clk_lite_c_freecnt", "",
5529                         ENABLE_IP_CAM10, 22, CLK_IGNORE_UNUSED, 0),
5530         GATE(CLK_PIXELASYNCS_LITE_C, "clk_pixelasyncs_lite_c", "",
5531                         ENABLE_IP_CAM10, 20, CLK_IGNORE_UNUSED, 0),
5532         GATE(CLK_ISP_SPI1, "clk_isp_spi1", "",
5533                         ENABLE_IP_CAM10, 10, CLK_IGNORE_UNUSED, 0),
5534         GATE(CLK_ISP_SPI0, "clk_isp_spi0", "",
5535                         ENABLE_IP_CAM10, 9, CLK_IGNORE_UNUSED, 0),
5536         GATE(CLK_LITE_C, "clk_lite_c", "",
5537                         ENABLE_IP_CAM10, 2, CLK_IGNORE_UNUSED, 0),
5538         GATE(CLK_CSIS2, "clk_csis2", "",
5539                         ENABLE_IP_CAM10, 1, CLK_IGNORE_UNUSED, 0),
5540 };
5541
5542 static struct samsung_cmu_info cam1_cmu_info __initdata = {
5543         .mux_clks               = cam1_mux_clks,
5544         .nr_mux_clks            = ARRAY_SIZE(cam1_mux_clks),
5545         .div_clks               = cam1_div_clks,
5546         .nr_div_clks            = ARRAY_SIZE(cam1_div_clks),
5547         .gate_clks              = cam1_gate_clks,
5548         .nr_gate_clks           = ARRAY_SIZE(cam1_gate_clks),
5549         .fixed_clks             = cam1_fixed_clks,
5550         .nr_fixed_clks          = ARRAY_SIZE(cam1_fixed_clks),
5551         .nr_clk_ids             = CAM1_NR_CLK,
5552         .clk_regs               = cam1_clk_regs,
5553         .nr_clk_regs            = ARRAY_SIZE(cam1_clk_regs),
5554 };
5555
5556 static void __init exynos5433_cmu_cam1_init(struct device_node *np)
5557 {
5558         samsung_cmu_register_one(np, &cam1_cmu_info);
5559 }
5560 CLK_OF_DECLARE(exynos5433_cmu_cam1, "samsung,exynos5433-cmu-cam1",
5561                 exynos5433_cmu_cam1_init);
5562
5563 static struct clk **suspend_enable_clks;
5564 static int nr_suspend_on;
5565 static struct clk ***suspend_reparent_clks;
5566 static int nr_suspend_reparent;
5567
5568 static int exynos5433_clk_suspend_prepare(void)
5569 {
5570         int i;
5571
5572         for (i = 0; i < nr_suspend_on; i++) {
5573                 if (!suspend_enable_clks[i])
5574                         continue;
5575                 clk_prepare_enable(suspend_enable_clks[i]);
5576         }
5577
5578         for (i = 0; i < nr_suspend_reparent; i++) {
5579                 if (!suspend_reparent_clks[i][0])
5580                         continue;
5581
5582                 suspend_reparent_clks[i][2] =
5583                         clk_get_parent(suspend_reparent_clks[i][0]);
5584                 clk_set_parent(suspend_reparent_clks[i][0],
5585                                 suspend_reparent_clks[i][1]);
5586         }
5587
5588         return 0;
5589 }
5590
5591 static int exynos5433_clk_suspend_unprepare(void)
5592 {
5593         int i;
5594
5595         for (i = 0; i < nr_suspend_on; i++) {
5596                 if (!suspend_enable_clks[i])
5597                         continue;
5598                 clk_disable_unprepare(suspend_enable_clks[i]);
5599         }
5600
5601         for (i = 0; i < nr_suspend_reparent; i++) {
5602                 if (!suspend_reparent_clks[i][0])
5603                         continue;
5604
5605                 clk_set_parent(suspend_reparent_clks[i][0],
5606                                 suspend_reparent_clks[i][2]);
5607         }
5608
5609         return 0;
5610 }
5611
5612 static struct samsung_clk_suspend_ops exynos5433_clk_suspend_ops = {
5613         .suspend_prepare = exynos5433_clk_suspend_prepare,
5614         .suspend_unprepare = exynos5433_clk_suspend_unprepare,
5615 };
5616
5617 static int __init exynos5433_suspend_init(void)
5618 {
5619         struct clk *clk, *parent;
5620         int i, ret;
5621         struct device_node *np;
5622         struct of_phandle_args clkspec;
5623
5624         np = of_find_compatible_node(NULL, NULL, "exynos5433-cmu-suspend");
5625         if (!np)
5626                 return -ENOENT;
5627
5628         nr_suspend_on = of_count_phandle_with_args(np,
5629                         "suspend-on-clks","#clock-cells");
5630         if (nr_suspend_on > 0) {
5631                 suspend_enable_clks = kcalloc(sizeof(struct clk *),
5632                                         nr_suspend_on, GFP_KERNEL);
5633
5634                 for (i = 0; i < nr_suspend_on; i++) {
5635                         ret = of_parse_phandle_with_args(np,
5636                                 "suspend-on-clks","#clock-cells", i, &clkspec);
5637                         if (ret < 0)
5638                                 continue;
5639
5640                         clk = of_clk_get_from_provider(&clkspec);
5641                         if (IS_ERR(clk))
5642                                 continue;
5643
5644                         suspend_enable_clks[i] = clk;
5645                 }
5646         } else {
5647                 nr_suspend_on = 0;
5648         }
5649
5650         nr_suspend_reparent = of_count_phandle_with_args(np,
5651                         "suspend-reparent-clks","#clock-cells");
5652         if (nr_suspend_reparent > 0) {
5653                 nr_suspend_reparent /= 2;
5654
5655                 suspend_reparent_clks = kcalloc(sizeof(struct clk **),
5656                                         nr_suspend_reparent, GFP_KERNEL);
5657
5658                 for (i = 0; i < nr_suspend_reparent; i++) {
5659                         ret = of_parse_phandle_with_args(np,
5660                                 "suspend-reparent-clks","#clock-cells",
5661                                 (2 * i), &clkspec);
5662                         if (ret < 0)
5663                                 continue;
5664
5665                         clk = of_clk_get_from_provider(&clkspec);
5666                         if (IS_ERR(clk))
5667                                 continue;
5668
5669                         ret = of_parse_phandle_with_args(np,
5670                                 "suspend-reparent-clks","#clock-cells",
5671                                 (2 * i) + 1, &clkspec);
5672                         if (ret < 0)
5673                                 continue;
5674
5675                         parent = of_clk_get_from_provider(&clkspec);
5676                         if (IS_ERR(parent))
5677                                 continue;
5678
5679                         /*
5680                          * suspend_reparent_clks[0] = target clock
5681                          * suspend_reparent_clks[1] = new parent
5682                          * suspend_reparent_clks[2] = old parent
5683                          */
5684                         suspend_reparent_clks[i] = kcalloc(sizeof(struct clk *),
5685                                                 3, GFP_KERNEL);
5686
5687                         suspend_reparent_clks[i][0] = clk;
5688                         suspend_reparent_clks[i][1] = parent;
5689                 }
5690         } else {
5691                 nr_suspend_reparent = 0;
5692         }
5693
5694         of_node_put(np);
5695
5696         return samsung_clk_register_suspend_ops(&exynos5433_clk_suspend_ops);
5697 }
5698 late_initcall(exynos5433_suspend_init);